JPS59169180A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the margins of a withstand voltage of a gate insulating film of an MISFET to operate as a circuit element and a voltage to be clamped in a gate protective element and to improve the reliability by providing a region which has an impurity density higher than that of a substrate under the gate electrode of the protecting element. CONSTITUTION:An input stage circuit element 1 is formed of MISFETs Q1, Q2, an input protecting circuit 2 provided between an input terminal BP and the element 1 is formed of a gate protective element Q2 made of a resistor R and the MISFET. One end of the gate electrode 10B of the MISFETQ1 of the element 1 is extended and connected through a contacting hole 9 with the circuit 2. The spread of a depletion layer due to the P-N junction between the part 11 having a P<+> type impurity formed on the surface of a P type semiconductor substrate 3 under the gate electrode 10A of the protective element Q3 and the drain 15B is suppressed to readily cause a surface breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor [hereinafter referred to as
M I S F E T (Metal Insula
torSemiconductor Field Ef
The present invention relates to a semiconductor device using a semiconductor device (called a fect transistor) and a method for manufacturing the same.

By integrating MISFET into a semiconductor chip,
The semiconductor device made with rated C1rcuit is
Generally widely used.

In such a semiconductor device, the above 10 may be destroyed (hereinafter referred to as electrostatic damage) due to excessive voltage due to static electricity induced by a worker or handler during the manufacturing process. This electrostatic breakdown is caused by M
This is a phenomenon that occurs in the gate portion of an ISFET and causes destruction of the gate insulating film (hereinafter referred to as gate destruction). In order to prevent gate damage due to excessive voltage, external terminals and MIS where gate damage is likely to occur must be
It is known to insert a gate protection element between the FET and the FET to clamp an excessive voltage. This gate protection element generally utilizes Zener breakdown that occurs at a pn junction in a semiconductor substrate or surface breakdown that occurs at a pn junction on the surface of a semiconductor substrate.

It is well known that a MISFET is used as a gate protection element that utilizes surface breakdown. In this structure, the gate electrode and the source electrode are connected together to form one terminal of the gate protection element, and the drain electrode serves as the other terminal of the gate protection element. By inserting this gate protection element into the gate input circuit of the MISFET to be protected, a recoverable breakdown is caused at the pn junction on the surface of the semiconductor substrate on the drain side of the gate protection element to clamp the excessive voltage. This prevents the MISFET, which acts as a circuit element, from being destroyed. This gate protection element acts as a circuit element.
Since the MI 5FET for gate protection can be formed at the same time as the ISFET, it is extremely advantageous in that there is no need to add additional manufacturing process costs, and is generally widely used.

However, in the manufacturing process of semiconductor devices, the gate insulating film of the MISFET that acts as a circuit element has a breakdown voltage that is lower than the overvoltage that should be clamped by the gate protection element. It will be done. For this purpose, the MISFE, which should act as a circuit element,
There is a drawback that unnecessary abnormal input electrons higher than the operating voltage of T and lower than the voltage to be clamped by the gate protection element cause the gate breakdown of the MiSFET that should function as a circuit element. This phenomenon becomes more significant as integration improves, the gate insulating film of the MISFET becomes thinner, and the margin between the withstand voltage of the gate insulating film and the voltage to be clamped by the gate protection element becomes smaller.

An object of the present invention is to eliminate the above-mentioned drawbacks, improve the margin between the withstand voltage of the gate insulating film of the MISFET that functions as a circuit element and the voltage to be clamped by the gate protection element, and improve yield and reliability. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

Hereinafter, the present invention will be described in detail along with one embodiment.

Components having similar functions in all figures are given the same symbols, and repeated explanations will be omitted.

FIG. 1 is an equivalent circuit diagram for explaining the outline of an input protection circuit according to the present invention.

In FIG. 1, BP is an external terminal for inputting an input voltage from the outside into the semiconductor device.

1 is a circuit element that is the input stage of the IC, and the two MI
It is composed of 5FETQ, ,Q2.

P-ccC is a vcc voltage power supply terminal, and P-Qut is an output terminal of the circuit element 1. 2 is external terminal BP and circuit element l
It is a human power protection circuit provided between the resistor R and MI
Consisting of gate protection @ element Q3 consisting of SFET1
1. ing. The input protection circuit 2 is the MISF of the circuit element 1.
It is connected to the gate of ETQ. G is ground.

2 and 3 are schematic diagrams for explaining an embodiment of the present invention constructed based on the equivalent circuit diagram shown in FIG. 1, and FIG. 2 shows an input protection circuit section and an input stage. FIG. 3 is a top view showing a part of the circuit element in FIG. 2, and FIG.
FIG.

2nd [1: t5-] and FIG. 3j are p-type semiconductor substrates having impurities of ions (3 is made of silicon single crystal and is boron). Reference numeral 6 indicates an insulating film (field insulating film) for electrically isolating semiconductor elements, and is made of silicon dioxide (SIO2), for example. Reference numeral 7 indicates an insulating film provided in the semiconductor substrate 3 under the insulating film 6. There is a p+ type channel stopper region 8 for more complete isolation between semiconductor elements.An insulating film 8 is provided on the semiconductor substrate 3 in the semiconductor element part or between conductors. For example, silicon dioxide, nitride (S
i, N,). Reference numeral 9 denotes a connection hole provided at a predetermined position of the input protection circuit section for connection between the input protection circuit section and the input stage circuit element. IOA is the gate electrode of MISFET (Q3) II, which is a gate protection element in the input protection circuit section, and is connected to its north and further grounded. I
OB is a gate electrode of MISFETQ, which is a manual stage circuit element, and one end thereof extends and is connected to the input protection circuit section through a contact hole 9. Each gate electrode is formed by forming an inversion layer (channel region) near the surface of the semiconductor substrate 3 below the gate electrode.
There are four electrical connections between the drain and source in lt.
It is designed to call and shut off.

11 is a gate protection element CMIS which is an embodiment of the present invention.
A region containing p+ type impurities (hereinafter referred to as fS p
+ Territory area (・U). This suppresses the expansion of the depletion layer due to the pn junction between that part and the drain (<15I3), and makes surface breakdown more likely to occur in that part. However, it must be higher than the operating voltage of the internal circuit elements.

12 is a phosphorus silicate glass (
This is an insulating film made of PSG) that improves the coverage of the upper layer by relaxing protrusions formed by multiple stacked layers.

In addition, sodium (N), which affects the characteristics of semiconductor devices,
a) It also serves as a getter for ions, etc. Reference numeral 14A denotes a wiring, one end of which is connected to an external terminal and the other end of which is connected via a contact hole 13A to an n'''' type semiconductor region 15A which becomes a resistor (8) of the input protection circuit section. 14B and 140 are wiring (also electrodes) and a connection hole 13B.

130 through the drain n''W semiconductor region 15D.

It is connected to the source n+ type semiconductor region 15B.

Next, a manufacturing method of the above-mentioned embodiment will be explained.

Note that this embodiment applies to a semiconductor device having a memory function, for example, a horizontal ROM (Read Only) as shown in FIG.
It can be applied to the manufacturing process of

FIG. 4 relates to this embodiment and is an equivalent circuit diagram of the main part of the horizontal ROM.

In FIG. 4, BL and BL are focus lines arranged in rows for transmitting potentials serving as information;
Sense amplifier SA for increasing information in each of them.
,,SA, are connected.

WL, ~WL are word lines arranged in a row intersecting bit lines BL, BL2, and the semiconductor substrate below the gate electrode is connected to the word line by injecting charge thereto. An inversion layer is formed on the surface, and the inversion layer connects the source and drain of MI 5FET.
We are becoming familiar with each other.

The word lines WL, ~WL are provided with word drivers WD, ~WD in order to amplify their charges.

is provided. At the intersections of the bit lines BL, BL, and word lines WL, ~WL3, there are MIs having a memory function.
SFETQ, .about.Q0 are arranged, and their drain sides are connected to each bit line, their gates are connected to each word line, and their sources are connected to ground. Bit lines BL,, BL.

The MI 5FETQ, o, Q, connected to is a resistor.

The horizontal ROM allows the user to set information. M I S B" E T Qp, Qa are circuit elements without information, which can be easily formed. These MISFETQ,.

During the manufacturing process, Q8 is applied at the threshold 1 of the inversion layer (channel region) formed on the surface of the semiconductor substrate below the gate electrode.
ltage) is higher than the operating voltage of other Nl I S F E Ts. For this purpose, MISFET
The drain and source of Q= and Qs are in a conductive state, acting as if they were circuit elements with no information.

If the input protection circuit of this embodiment is formed at the same time as manufacturing the horizontal ROM, the result will be as shown in FIGS. 5 to 15.

5 to 15 are cross-sectional views of main parts of the semiconductor device in each manufacturing process for explaining the manufacturing method of this embodiment.

First, it is made of silicon single crystal and has an IX10. ``A p-type semiconductor substrate 3 containing an impurity of boron (B) ions in an amount of about atoms/cut is prepared.

After this, as shown in FIG. 5, 1. A heat treatment is performed at about -000° C. to form an insulating film 4 made of silicon dioxide with a thickness of about 500 A on the semiconductor substrate 3.

In this embodiment, as shown in FIG. 3, the left side is the input protection circuit section (cross-sectional view taken along line XX in FIG. 2), and the right side is the input stage circuit element MI 5FETQ (second FIG.

After the process shown in Figure 5, nitride (Siq
A mask 5 for ion implantation resistance 2 and heat resistance treatment is formed by forming a film with a thickness of 500Aa and removing nitride in areas other than the semiconductor element formation area. Using this mask 5, impurities are implanted by ion implantation to form a channel stopper region for more complete isolation between semiconductor elements, resulting in the result as shown in FIG. In this ion implantation method, boron ion impurities of approximately 3.5×10 12 atoms/cml may be implanted with an energy of approximately 75 [KeV].

After the step shown in FIG. 6, heat treatment is performed using a mask 5 to form an insulating film 6 for isolating semiconductor elements,
At the same time, the implanted impurity is stretched and diffused to form a p+ type channel stopper region 7. Then the seventh
As shown in the figure, the mask 5 is removed and the insulating film 4 below it is removed to expose the surface of the semiconductor substrate 30 that will become the semiconductor element. The heat treatment may be performed at about 1200°C, and the insulating film 6 may have a thickness of 14 μm and 8°C.

After the step shown in FIG. 7, heat treatment is performed at about 1000° C. so that the semiconductor element portion becomes an insulating film 8 of about 650A. Thereafter, impurities for adjusting the threshold voltage of the MISFET are implanted by ion implantation (not shown). Then, as shown in FIG. 8, a contact hole 9 is formed by removing the insulating film 8 at a portion where the input protection circuit section connects to the input stage circuit element MISFETQ.

After the process shown in FIG. 8, polysilicon 10 that will become the gate electrode is deposited to a thickness of about 5000A, and phosphorus (PJ ions are diffused (phosphorous treatment) into it to make it conductive) to make it an n-type. The result will be as shown in Figure 9.Also, instead of using polysilicon as the upper electrode, high-melting point metals such as molybdenum (Mo) + tungsten (W) or silicide (a compound with silicon) of good.

After the step shown in FIG. 9, as shown in FIG. 10, unnecessary polysilicon lO is removed to form a gate electrode 10A of the gate protection element and a gate electrode 10B of the MISFETQ of the input stage circuit element.

After the process shown in FIG. 10, the gate electrode 10A is formed.

When the insulating film 8 other than the F part of 10B is removed, the result is as shown in FIG. 11.

After the step shown in FIG. 11, the entire surface is subjected to heat treatment at about 1000° C. to form an insulating film 8 of silicon dioxide so as to cover the surface portion 2 of the semiconductor substrate 3 of the semiconductor element portion and the gate electrodes 10A and 10B. After this, as shown in FIG. 12, the gate electrode 10A is formed.

Semiconductor substrate 3 using part 10B and insulation 6 as a mask.
N+ type impurities are implanted near the inner surface to form semiconductor regions that will serve as resistances for the drain, source, and input protection circuit sections. This can be done by implanting an impurity of arsenic (As) ions of about 1X10'' atoms/cffl with an energy of about 80 [KeV] by ion implantation.

After the step '1' shown in FIG. 12, a photoresist is formed on the entire surface, the photoresist on the gate electrode 10A of the input protection circuit section is removed, and a mask for ion implantation resistance is formed. Using this mask, p+ type impurity 11 is implanted into the vicinity of the surface of semiconductor substrate 3 below gate electrode 10A, and when the mask is removed, the result is as shown in FIG. 13. This p
The +-type impurity is boron (Bl ion) of about lXl0'' atom/cf, which is ion-implanted to 13
It is sufficient to implant it with an energy of about 0 [KeV]. As a result, p+ type impurities form a p+ region on the surface portion of semiconductor substrate 3 via insulating film 8 and gate electrode 10A. It is desirable that the threshold voltage at this portion be higher than the operating voltage of the semiconductor device.

After the process shown in Fig. 13, the lath CP is shown in Fig. 14.
An insulating film 12 made of SO) is deposited, and the insulating film 12 is subjected to heat treatment (glass flow). Further, by this heat treatment, the impurities implanted for forming the semiconductor region are stretched and diffused, and the n+ type semiconductor region 15A is
~15B is formed. The phosphosilicate glass softens the protrusion formed by the multiple stacked layers on the semiconductor substrate 3 and improves the coverage of the two-part layer.

In addition, sodium (N), which affects the characteristics of semiconductor devices,
a) It also serves as a getter for ions, etc.

After the step shown in FIG. 14, the insulating films 8 and 12 at the connection portions between the upper wiring and the semiconductor regions 15A to 15B, which will be formed in a later step, are removed, and the connection holes 13A, 13B, 13 are removed.
form 0. Wirings 14A, 14B, and 140 made of aluminum (Al) are formed so as to be connected to the semiconductor regions 15A) and 1.5B through the connection holes 13A, 13B, and 130.

The wirings 14A, 1.4B, +140 may have a film thickness of about 1 μm. 15A is the resistor of the input protection circuit section (semiconductor region that will be used; 15B and 150 are semiconductor regions that will be the drain and source of the gate protection element [MIS: F'E'l' (Q3)] of the input protection circuit) , 5D and 15g are the input stage circuit elements M I S F E T
This is a semiconductor region that becomes the drain and source of Q +.

Through these series of steps, the semiconductor device of this example is completed. After this, a protective film or other treatment may be applied.

Although the semiconductor regions 15A to 15E in this embodiment were formed by ion implantation technology, an insulating film 8 was formed after the process shown in FIG.
It may also be formed by removing the insulating film 8 in the forming portion and diffusing from the exposed semiconductor substrate 3.

FIG. 16 is an equivalent circuit diagram showing an outline of an input protection circuit for explaining another embodiment of the present invention.

In this example, a gate protection element [M I S F E T
(The gate electrode of QJ is Vcc voltage voltage power supply terminal -1oc
If an overvoltage is likely to occur, the voltage cannot be applied to the gate electrode and the gate electrode is clamped at a low voltage. Also, when operating the internal circuit elements, no excessive voltage is generated, so V is applied to the gate electrode. The voltage of C is set to 17J[], and the clamping voltage is increased.

Further, when the withstand voltage of the gate insulating film of the gate protection element [MI 5FET (Q,)] can sufficiently cope with excessive voltage, the gate electrode is set to the above-mentioned V. , voltage power supply terminal P,
-V. Instead of C, it may be connected to an external terminal and the gate electrode and drain may be made common.

It goes without saying that this embodiment is not limited to the above embodiment, and can be modified in various ways without changing the gist thereof. For example, although the above embodiment uses surface breakdown to control the clap voltage of the gate protection element, the position where the depletion layer is suppressed may be changed so that Zener breakdown can be used.

As explained above, according to the present invention, by providing a region near the surface of the semiconductor substrate below the gate electrode of the gate protection element Q3, which has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, The expansion of the depletion layer due to the pn junction between the portion and the semiconductor region on the input side of the excessive voltage can be suppressed more than in other portions. By rubbing, the recoverable breakdown voltage of the gate protection element can be lowered. That is, it is possible to generate a surface breakdown that operates at a sufficiently low voltage against an unnecessary voltage higher than the operating voltage of the internal circuit elements. Therefore, the margin between the withstand voltage of the gate insulating film of the manual stage circuit element and the clap voltage of the gate protection element is improved, and a highly reliable semiconductor device can be provided.

In addition to improving reliability, the yield of semiconductor devices can also be improved.

Furthermore, no special manufacturing process is required to provide the gate protection element, and the gate protection element can be easily provided through normal processes.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram according to the present invention, FIGS. 2 and 3 are diagrams for explaining an embodiment of the present invention, and FIG. 4 is a diagram showing a manufacturing method of an embodiment of the present invention. The related equivalent circuit diagrams, FIGS. 5 to 15 are diagrams for explaining the manufacturing method of one embodiment of the present invention, and FIG. 16 is a diagram for explaining another embodiment of the present invention. . In the figure, 1... circuit element, 2... input protection circuit, 3...
...Semiconductor substrate, 4,6.8.12...Insulating film, 5.
...Mask, 7...Channel stopper IA area, 9.
13A to 130... Connection hole, 10... Polysilicon, IOA. 10B...gate electrode, 11...p+ region, 14A~
140... Wiring, 15A-15E... Semiconductor region. Agent Patent Attorney Akio Takahashi Figure 16 No. 1)-64f

Claims (1)

[Claims] 1. It has an insulated gate field effect transistor. In the semiconductor device, a region having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate is provided on the surface of the semiconductor substrate below the gate electrode of at least one of the insulated gate field effect transistors. semiconductor devices. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the insulated gate field effect transistor is used as a gate protection element. 3. In the method of manufacturing a semiconductor device having an insulated gate field effect transistor, a small amount (of the same conductivity type as the semiconductor substrate) on the surface of the semiconductor substrate of a portion of the gate electrode of one of the insulated gate field effect transistors is used. A method for manufacturing a semiconductor device, comprising the step of forming a region having an impurity concentration higher than that of the semiconductor substrate. 4. In the method 1 for manufacturing a semiconductor device according to claim 3, A method for manufacturing a semiconductor device characterized by using an insulated gate field effect transistor as a gate protection element.