JPS59167899A - Refresh method of dynamic random access memory - Google Patents

Abstract

PURPOSE:To hold surely and simply a CRT screen even at power supply interruption by changing over the mode to a self-refresh mode when a dynamic RAM is not in the operation of a normal access mode. CONSTITUTION:A high level signal via a line l18 is impressed to a data terminal D at power supply ON, a Q output of a D FF7B goes to a high level, a terminal RFSH of a dynamic RAM9 for CRT display goes to a high level and the RAM9 is selected to the normal access mode. On the other hand, when the power supply is interrupted and the terminal D is inverted to a low level, a horizontal synchronizing signal via a line l11 and an inverter 7A by the backup of a battery or the like is impressed, the FF7B is latched in synchronizing with the blanking period of the horizontal synchronizing signal, the output Q is inverted to a low level, and the RAM9 is brought into the self-refresh mode during a period not in the normal access mode operating period. As a result, even if the power supply interruption is generated at any timing, the holding of the CRT screen is performed simply and surely.

Description

TECHNICAL FIELD The present invention relates to a dynamic random access memory refresh method for switching the dynamic random access memory to a refresh mode.゛In conventional dynamic random access memory (hereinafter referred to as D-RAM), a read/write cycle and a refresh cycle are distinguished, and no read/write operation is performed when switching to refresh mode. is required as a timing condition. However, when performing a full backup of D-RAM during a power outage, if the power outage is detected and the mode is immediately switched to refresh mode, the D-RAM may be in read/write operation at that time, and the above timing conditions are not met. You won't be completely satisfied.

One object of the present invention is to provide an entire D-RAM refresh method that can easily maintain a CRT screen during a power outage.

Structure and Effects of the Present Invention In the dynamic random access memory of the present invention, when switching between read/write normal access mode and refresh mode, the dynamic random access performs a switching operation when the normal access mode is not operating.・Please use the memory refresh method.

According to the present invention, by switching the D-RAM to the refresh mode when the full normal access mode is not in operation, the CRT control circuit for image processing can easily maintain the CRT screen even during a power outage. can be realized. Furthermore, the simple circuit configuration facilitates mass production and reduces costs.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. C.P.
The UI is Passline I! 1! It is connected to the decoder 2 via r. However, CPU is an abbreviation for central processing unit. C
Terminal RD of PUI is connected to decoder 2 via line 12, and terminal WR is connected to decoder 2 via line 13f.

Also, the CPUI is Passline I! 4 to CR, terminal DO-D of T controller 3 (product name μPD7220)
Connected to 7. CRT is an abbreviation for cathode ray tube. CRT controller is line I! 6. The terminals AO are connected to the decoder 2 via lines 7 to 7, respectively, and the terminals 'ADO to AD15 are connected to the buffer circuit 4 and the latch circuit 5 via the pass line 14f. In the CRT controller 3, the terminal DB rN is connected to the timing circuit 6 via the line 19, the terminal RAS is connected to the timing circuit 6 via the line 110, and the terminal H8YNC is connected to the refresh switching circuit 7 and the terminal H8YNC of the video monitor circuit 10 via the line llll. connected, terminal VS
YNC is Line I! Video monitor circuit 1 via 121r
0 terminal VSYNC. The buffer circuit 4 is
The video signal conversion circuit 8 and the terminal DO of the D-RAM 9 (product name μPO4168) are connected via the pass line 113'.
Connected to D15. The latch circuit 5 connects the pass line l!
It is connected to terminals AO to A12 of the D-RAM 9 via 14'. The timing circuit 6 is connected to line J15'! 5 to the terminal DE of the D7RAM 9, and the line 116 to the terminal CE of the D-RAM 9. The refresh switching circuit 7 connects the D-RAM 9 via the line 117'
are connected to the timing circuit 6 through the terminals RFSH and LIFE 118'fc, respectively. The video signal conversion circuit 8 is connected to the line l! It is connected to the terminal VIDEO of the video monitor circuit 10 via the terminal 19'e.

Here, the entire operation of the embodiment shown in FIG. 1 will be explained. Pass line l from CPU1! The address signal applied to the decoder 2 via lTr is sent to the decoder 2 as a read signal on line 12 and a line l! In response to the write signal No. 3, the CRT controller 3 applies a read signal to the terminal RDK, a write signal to the terminal WR, and an address signal to the terminal AO, respectively.

These signals control the CPUI and CRT controller 3.
That is, data signal transmission is performed via the pass line 14f. When the CRT controller 3 reads data, the data signal from the terminals ADO-AD15 is applied to the buffer circuit 4 and latch circuit 5.

The data signal from buffer circuit 4 is on line l! 13 to terminals DO to D15 of the video signal conversion circuit 8 and the D-RAM 9. The data signal from latch circuit 5 is on line l! 14-i to the D-RAM9om child AO-A12.

When the CRT controller 3 writes, the D-RAM
The data signals from terminals DO to D15 of 9 are connected to lines I!
13'i to the buffer circuit 4 and video signal conversion circuit 8. The data signal applied to buffer circuit 4 is applied to CRT controller 3 and launch circuit 5. Is terminal H8YNC of CRT controller 3 a horizontal periodic signal and terminal VSYNC a vertical synchronization signal? Send each.

FIG. 2 is a logic circuit diagram of the refresh switching circuit 7, which is a feature of the present invention. The input terminal a of the pass inverter 7A is connected to the line 111. Pass inverter 7
The output terminal of A is the terminal T of the D type slip 70 tube 7B.
connected to. The terminals of the D-type 7rig flop 7B are as follows:
Line l! 18. D type 7 limp 70 tube 7
A voltage of Ov, which is a low level, is applied to terminals SD and RD of B. The output terminal Q of the D-type flip-flop 7B is connected to the terminal R of the D-RAM 9 via a line 117'.
Connected to FSH.

The operation at the time of power outage will be described below with reference to FIGS. 1 to 3. It is assumed that all the elements constituting the entire circuit included in FIG. 2 are banked up by a battery at the time of power outage. As shown in FIG. 3 +1+, when the power is turned on, line 19 and line l! supplied to the timing circuit 6 are applied. Line I! by a signal of 10! Figure 3 (2
), a signal of level 1 is sent out. In the D-type slip-flop 7B, while a high level signal is applied to the terminal Q, the output terminal Q outputs the signal as shown in Fig. 3 (4).
A high level signal is sent as shown in . Therefore, since the signal applied to the terminal RFSH of the D-RAM 9 is at a high level, the D-RAM 9 operates in the normal access mode.

Next, a case will be described in which a power outage occurs at the arrow P as shown in FIG. 3 +1+. When a power outage occurs, Figure 3 +
The signal shown in FIG. 3(2), which is applied to the terminal of the D-type flip-flop 7B a little later than the point of arrow P of 1+, switches from high level to low level.

Therefore, the D-type flip-flop 7B is shown in FIG. 3 (3).
It is launched in synchronization with the retrace period of the horizontal periodic signal, and a low level signal is sent from the output terminal Q as shown in FIG. 3(4). However, the broken line in FIG. 3 (t1) is the TTL operation level, and the horizontal periodic signal in FIG. 3 (3) is normally created up to time T. D, RAM9 is the terminal RF
The low level signal applied to Sf (0) switches to self-refresh mode. During the low level period of the synchronization signal) - Switches from high level to low level. That is, D-RAM9 is
The normal access mode is switched to the self-refresh mode during a period when neither a read operation nor a write operation is performed.

In the video motor circuit 10, a video signal, line I!, is provided on line 119'. It receives a horizontal periodic signal through line f12' and a vertical periodic signal through line f12', performs an image reproduction operation, and supplies each signal to cathode ray tube 11.

FIG. 4 is a block diagram of another embodiment of the invention. In the above embodiment, a D-RAM with a self-refresh function is used.
However, in this embodiment, a D-RAM without a self-refresh function is used. In the fourth (8), the refresh switching circuit 7 has the same circuit configuration as in the previous embodiment. The output terminal Q of the D-type 7 lip-flop 7B is connected to the refresh control circuit 13. Refresh control circuit 13 is connected to D=RAM 14 via address bus line /21i.

Further, the refresh control circuit 13H1 control signal is applied to the D-RAM 14 through all lines 122. D-R
Since AM14 does not have a self-refresh function, the refresh control time M13 is required. A signal from the output terminal Q of the D-type slip flop of the refresh switching circuit 7 shown in FIG. 2 is applied to the refresh control circuit 13, and this signal switches the D-RAM 14 to the power-off refresh mode.

In this embodiment, it is used for a CRT control circuit, but it may also be used for other circuits using D-RAMi.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a logic circuit diagram of the refresh switching circuit 7, and FIG. 3 is a signal waveform diagram for explaining the entire operation of the refresh switching circuit 7.
FIG. 4 is a block diagram of another embodiment of the invention. 1...Central processing unit, 2...Decoder, 3...C
RT controller, 4... Bank up, 5... Launch circuit, 6... Timing circuit, 7... Refresh switching circuit, 7A... Pass inverter, 7B...
- D-type flip-flop, 8... video signal conversion circuit, 9... dynamic random access memory, 10... video monitor circuit, 11... cathode ray tube, 13... refresh control circuit, 14・・・
・Dynamic Random Access Memo L, I! 1
~122...Line Agent Patent Attorney Kei Nishi Part Figure 2 Figure 3 ■ 542- Figure 4

Claims (1)

[Claims] In dynamic random access memory,
A refresh method for a dynamic random access memory in which, when switching between read/write normal access mode and refresh mode, all switching operations are performed when the normal access mode is not in operation.