JPS59165440A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS59165440A
JPS59165440A JP3985183A JP3985183A JPS59165440A JP S59165440 A JPS59165440 A JP S59165440A JP 3985183 A JP3985183 A JP 3985183A JP 3985183 A JP3985183 A JP 3985183A JP S59165440 A JPS59165440 A JP S59165440A
Authority
JP
Japan
Prior art keywords
wiring
layer
wirings
input
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3985183A
Other languages
Japanese (ja)
Inventor
Osao Yoshimura
吉村　長生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3985183A priority Critical patent/JPS59165440A/en
Publication of JPS59165440A publication Critical patent/JPS59165440A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain the integrated circuit which is electrically good by reducing the line impedance by providing a multi-layer substrate and grouping the internal wirings and the pad parts which are connected with the external terminals for the substrate of each layer to arrange them. CONSTITUTION:An external terminal for grounding 2 and a power external terminal 5 are connected with pad parts 4a and 7a through internal wirings 3 and 6 which have large areas respectively. The pad parts 4a and 7a also have large areas and are wire-bonded with an IC chip 1. The wiring for input and output signals are arranged in the lower layer and since there are not wirings for a power supply and for grounding, said wirings are arranged widely and still have enough room. External terminals 8 and 11 for input and output signals occupy substantially large area as internal wirings 9 and 12, thereby reducing the impedance.

Description

【発明の詳細な説明】 本発明は集積回路パッケージの内部配線およびパッド部
の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of internal wiring and pad portions of integrated circuit packages.

従来の集積回路パッケージでは、電源・グランドおよび
入出力信号のための内部配線およびワイヤボンディング
のためのパッド部はすべて同一基板上に配設された構造
になっている。そして相互の内部配線が相互インダクタ
ンス効果をさけるためになるべく近接しないように配置
するが、配置は平面上に限定されるから各個の内部配線
の幅は自ずと狭くなシ、配線のインピーダンスが高く電
気的特性の悪化の原因となっている。すべての内部配線
の直流・交流インピーダイδを低下することは困難であ
るから、特に問題となる内部配線を幅広くしようとする
と、そのしわよせが他の配線にくるから充分効果的に行
なうことができない。In conventional integrated circuit packages, internal wiring for power supply/ground, input/output signals, and pads for wire bonding are all arranged on the same substrate. In order to avoid the mutual inductance effect, the internal wirings are placed as close as possible to each other, but since the arrangement is limited to a flat surface, the width of each internal wiring is naturally narrow, and the impedance of the wiring is high and electrical This causes deterioration of characteristics. It is difficult to lower the DC/AC impedance δ of all internal wiring, so if you try to widen the internal wiring, which is a particular problem, the wrinkling will affect other wiring, so it cannot be done effectively. .

本発明は上述の欠点を除去し、配線が多層にできるよう
にして設計の自由度を増し、特性の向上をはかった集積
回路パッケージを提供することにある 本発明による集積回路パッケージは多層の基板を設け、
外部端子に接続される内部配線およびパッド部を前記各
層の基板に組みわけして配設したことを特徴とする。An object of the present invention is to provide an integrated circuit package which eliminates the above-mentioned drawbacks, increases the degree of freedom in design by allowing wiring to be formed in multiple layers, and improves characteristics. established,
The present invention is characterized in that internal wiring and pad portions connected to external terminals are arranged in separate groups on each layer of the substrate.

以下本発明を図面を参照して詳しく説明する。The present invention will be explained in detail below with reference to the drawings.

先ず、第１図に従来の集積回路パッケージ（以下ＩＣパ
ッケージと称す）を示す。（８１図は正面図。First, FIG. 1 shows a conventional integrated circuit package (hereinafter referred to as an IC package). (Figure 81 is a front view.

（ｂ）図は平面図、（Ｃ）図はＡ−Ａ断面図、（ｄ）図
はＢ−Ｂ断面図である、グランド内部配線はグランド外
部端子２から内部配線３．パッド部４になされ、ＩＣ’
チップｌとパッド部４でワイヤボンドされる。(b) is a plan view, (C) is a sectional view taken along A-A, and (d) is a sectional view taken along B-B. The ground internal wiring runs from the ground external terminal 2 to the internal wiring 3. IC'
Chip l and pad portion 4 are wire-bonded.

電源内部配線は電源外部端子５から内部配線６゜パッド
部７となされ、ＩＣチップｌとワイヤボンドされる。他
の入出力内部配線についても、例えば入出力信号外部端
子８．１１から内部配線９゜１２、パッド部１０．１３
を経て、ＩＣチッグエとワイヤボンドされる。電気的に
はグランド・電源・入出力信号の各配線によるインピー
ダンスがすべて低いことが望ましいがこのま＼の構造で
は配線の幅は制限され無理である。The power supply internal wiring is formed from the power supply external terminal 5 to the internal wiring 6° pad portion 7, and is wire-bonded to the IC chip 1. Regarding other input/output internal wiring, for example, from the input/output signal external terminal 8.11 to the internal wiring 9.12, and the pad portion 10.13.
After that, it is wire-bonded to the IC chip. Electrically, it is desirable that the impedance of the ground, power supply, and input/output signal wiring be all low, but this is not possible with the current structure because the wiring width is limited.

第２図が本発明の一実施例である。ＩＣパッケージの基
板が二層になっており、電源およびグランドの配線を一
層に、その他の入出力信号の配線を他の一層に配置した
構造である。（ａ）図が正面図。FIG. 2 shows an embodiment of the present invention. The IC package substrate has a two-layer structure, with power supply and ground wiring arranged on one layer, and other input/output signal wiring arranged on the other layer. (a) The figure is a front view.

（ｂ）図が平面図、（Ｃ）図がＡ−Ａ断面図で二層の上
の層の配置を、（ｄ）図がＢ−Ｂ断面図で下の層の配置
をみることができる。（ｅ）図はＣ−Ｃ断面図である。(b) is a plan view, (C) is an A-A cross-sectional view showing the arrangement of the upper layer of the two layers, and (d) is a B-B cross-sectional view showing the arrangement of the lower layer. . The figure (e) is a cross-sectional view taken along the line C-C.

（ｅ）図にみる如くパッケージ基板は二層にな）、各層
ごとに内部配線およびパッド部が設けられる。(e) As shown in the figure, the package substrate has two layers), and internal wiring and pad portions are provided for each layer.

上層についていうと、グランド外部端子２．電源外部端
子５はそれぞれ広い面積の内部配線３，６を経てパッド
部４ａ　、７ａに接続される。パッド部４ａ、７ａも広
い面積となってお夛、こ＼でＩＣチップ１とワイヤボン
ドがなされる。通常の電気回路においてはグランドおよ
び電源配線は入出力信号部と共通配線になるから、この
インピーダンスは極力小にする必要があるが、この構造
で充分その要求をみたすことができる。入出力信号の配
線は（ｅ）図にみるごとく下層に配設される。電源・グ
ランド配線分がないため、（ｄ）図のように幅広く余裕
をもって配設される。例えば入出力信号外部端子８．１
１は内部配線９，１２としてかなシ広い面積を占有し、
そのインピーダンスを低下することができる。Regarding the upper layer, the ground external terminal 2. The power supply external terminals 5 are connected to the pad portions 4a and 7a via internal wirings 3 and 6 having large areas, respectively. The pad portions 4a and 7a also have a large area, and are then wire-bonded to the IC chip 1. In a normal electric circuit, the ground and power wiring are shared with the input/output signal section, so this impedance needs to be minimized as much as possible, and this structure can fully meet this requirement. Wiring for input/output signals is arranged in the lower layer as shown in figure (e). Since there is no power supply/ground wiring, it is laid out with a wide margin as shown in figure (d). For example, input/output signal external terminal 8.1
1 occupies a large area as internal wiring 9, 12,
Its impedance can be lowered.

上述の実施例では接地・電源と入出力信号との二層にわ
けたが、電気的所要特性からこれと別の組合わせにする
こともできる。実施例は通常最も一般的に問題になる場
合の例である。また、構造は複雑になるがさらに必要に
応じ、二層以上にすることも考えられる。In the above embodiment, the layer is divided into two layers: ground/power source and input/output signal layer, but other combinations may be used depending on the required electrical characteristics. The examples are usually examples of the most commonly problematic cases. Further, although the structure becomes more complicated, it is also possible to use two or more layers as necessary.

以上説明したように、本発明によればＩＣパッケージの
基板を多層として、各層に外部端子に接続される内部配
線、パッド部を組みわけることによって、配線インピー
ダンスを低下させ、電気的に良好な集積回路を得ること
ができる。As explained above, according to the present invention, the substrate of the IC package is multilayered, and internal wiring and pad portions connected to external terminals are arranged in each layer, thereby reducing wiring impedance and achieving electrically good integration. You can get the circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の集積回路パッケージを示す図、第２図は
本発明の一実施例を示す図である。 ｌ・・・・・・集積回路チップ、２・・・・・・グラン
ド外部端子、５・・・・・・電源外部端子、８，１１・
・・・・・入出力信号外部端子、３，６，９，１２・・
印・内部配線、４゜７　、１０　、１１　、４　ａ　、
　７　ａ　＝パッド部、１４・・・・・・キャップ。 際　２　目 享２回FIG. 1 is a diagram showing a conventional integrated circuit package, and FIG. 2 is a diagram showing an embodiment of the present invention. l...Integrated circuit chip, 2...Ground external terminal, 5...Power supply external terminal, 8, 11.
...Input/output signal external terminals, 3, 6, 9, 12...
Mark/internal wiring, 4°7, 10, 11, 4a,
7 a = pad portion, 14... cap. 2nd time 2 times

Claims (1)

【特許請求の範囲】[Claims] 集積回路パッケージにおいて、多層の基板を設は外部端
子に接続される内部配線およびパッド部を前記各層の基
板に組みわけして配設したことを特徴とする集積回路パ
ッケージ。1. An integrated circuit package, characterized in that a multilayer substrate is provided, and internal wiring and pad portions connected to external terminals are arranged separately on each layer of the substrate.
JP3985183A 1983-03-10 1983-03-10 Package for integrated circuit Pending JPS59165440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3985183A JPS59165440A (en) 1983-03-10 1983-03-10 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3985183A JPS59165440A (en) 1983-03-10 1983-03-10 Package for integrated circuit

Publications (1)

Publication Number Publication Date
JPS59165440A true JPS59165440A (en) 1984-09-18

Family

ID=12564464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3985183A Pending JPS59165440A (en) 1983-03-10 1983-03-10 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS59165440A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0718450U (en) * 1993-09-01 1995-03-31 日本無線株式会社 Electronic device mounting board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0718450U (en) * 1993-09-01 1995-03-31 日本無線株式会社 Electronic device mounting board

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