JPS5898943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably reduce the pattern conversion difference from the space for isolating between elements and the size of the mask by containing the step of forming an element isolating groove vertical to a silicon crystal substrate. CONSTITUTION:A dioxidized silicon film 42 and a nitrided silicon film 43 are formed on a silicon substrate 41, and a photoresist 44 is formed thereon. With the resist 44 as an etching resistant mask a groove 45 is formed, impurity ions are implanted as a dioxidized silicon film 46 and a channel stopper 47 on the groove 45, a polycrystalline silicon 48 is then grown on the groove, and the groove is buried. Subsequently, with a nitrided silicon film 43' on the element region as an etching resistant mask the silicon 48 is etched and removed to the surface of the silicon substrate, and a dioxidized silicon film 49 is formed on the nitrided silicon film and the groove. A photoresist 50 which covers the entire element is removed to the boundary of the film 49. Subsequently, the film 49 is etched and removed to the surface of the substrate 41.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for separating system relationships in an integrated circuit in which a plurality of semiconductor elements are integrally formed.

Conventionally, methods for separating elements in integrated circuits include Ph junction separation and dielectric separation, but in either method, the area required for separation is fk/411, which is larger than that for integrated circuits, so it is necessary to reduce the area lost for separation. Many attempts have been made to do so.

FIG. 1 is a cross-sectional view of an example of a conventional element isolation layer. After a channel stopper region 17 is provided on a silicon substrate 11, and a thin silicon dioxide film 8112 and a silicon nitride film 13 are provided on the surface, thermal oxidation is performed to separate 8108 layers. Layer 18 is selectively formed. The end of the sio separation layer 18 formed by this method lifts the end of the silicon nitride film 13 and invades the element region in the shape of a bird's beak.

This intrusion increases the area required for separation, which has the disadvantage of lowering the integration density.

FIGS. 2A to 2C are rounded cross-sectional views illustrating an example of a conventional method for forming an element isolation layer.

First, as shown in FIG.
After selectively forming a silicon nitride film 23 on the silicon nitride film 23, a photoresist 24 is formed.

Next, as shown in FIG. 2(b), using the photoresist 24 as an etching-resistant mask, the silicon nitride film 23 and the silicon substrate 21 are etched using reactive sputter etching or the like to form a groove 25.

Next, as shown in FIG. 2 (CJ), thermal oxidation is performed using the silicon nitride film 23' covering the element region as an oxidation-resistant mask.
Silicon dioxide J[28 is formed in the groove portion 25 and the non-element region to form element isolation.

However, since device isolation using this method completely fills the trench with a thermal oxide film, the device isolation width is always twice the i-sk dimension, and the silicon dioxide film that grows with respect to the trench width is The drawback is that it is difficult to control the film thickness. For example, when a silicon dioxide film is formed thinly relative to the groove width, the silicon dioxide film formed in the groove does not completely fill the tile, leaving a groove of silicon dioxide film in the center of the tile. If an n-channel silicon gate MOB type transistor is formed by a normal manufacturing method while leaving the trench in the silicon dioxide film, if polysilicon is formed on the surface of the wafer in the round shape to form a polysilicon gate, the silicon dioxide film will Polysilicon fills the groove. It is difficult to remove the polysilicon buried in this groove using normal etching for polysilicon gate processing. If such polysilicon remains buried in the trench, leakage may easily occur between polysilicon lines running in parallel across the #I# section. On the other hand, if a thick silicon dioxide film is formed in the groove and the groove is completely filled with the silicon dioxide film, stress is applied to the silicon substrate around the groove due to the volumetric expansion of the silicon dioxide film O, resulting in defects and device failure. The leakage current between the two increases. For this reason, the silicon dioxide film formed in the groove needs to be formed with precision with respect to the groove width, but it is difficult to control this #1 width. This is because the groove width varies to some extent (due to photoresist patterning and the next etching process).

Further, even when the trench is completely filled with the silicon dioxide film, stress is inevitably applied to the silicon substrate as a result of the volume expansion of the silicon dioxide film formed at the bottom of the trench.

In particular, the stress at the bottom corner of the groove becomes large. Defects caused by such stress pose a major problem in device reliability.

FIGS. 3(a) to 3(G) are process diagrams for explaining another example of the conventional method for forming an element isolation layer.

First, as shown in FIG. 3<a+, a silicon densified silicon 32 tube is formed on a (100) plane silicon substrate 31 by a thermal oxidation method, and then KCVD (Cheml ca I
A silicon oxide film 33 is formed by a vapor deposition method.

Next, as shown in FIG. 3 (bl), after covering the element region with a photoresist 34, using the photoresist 34 as an etching-resistant mask, the silicon nitride G433 and the silicon dioxide film 32 are removed by etching to create an element isolation region. let

Next, as shown in FIG. 3(a), after removing the photoresist 34, the silicon dioxide film 32 and silicon nitride film covering the device region are etched with an anisotropic etchant of potassium hydroxide as an etching-resistant mask. 100) to form a V-shaped groove in the silicon substrate.

Next, as shown in FIG. 3 (dJ), thermal oxidation is performed using the silicon nitride film 34 as an oxidation-resistant mask to form a silicon dioxide film 36 on the V-shaped exposed surface of the silicon substrate.

Next, as shown in FIG. 3(e), polycrystalline silicon 38 is grown over the entire surface of the wafer by the CVD method to fill the holes.

Next, as shown in FIG. 3 (fl), polycrystalline silicon 38 is etched away to the surface of the silicon substrate using electrified silicon 1x33 as an etching-resistant mask.

Next, as shown in FIG. 3, a silicon dioxide film 39 is formed on the polycrystalline silicon by an invulnerability method using the silicon nitride film 33 as an oxidation-resistant mask.

However, in this conventional device isolation method, thermal oxidation is performed using the electrified silicon film as an oxidation-resistant mask because it is necessary to form a thick oxide film on the polysilicon buried in the ■-shaped trench. The disadvantage is that the film penetrates into the element region to a large extent, and this penetration must be accounted for in the mask dimensions. As described above, this poses a major problem in improving the integration density. As a conventional example, we have shown a V-shaped groove filled with polysilicon.
Similar device isolation methods using U-shaped grooves have the same drawbacks.

The present invention eliminates the above-mentioned drawbacks, makes the difference in pattern conversion from the space for isolation between elements and mask dimensions extremely small, and provides a flat and reliable inter-element structure suitable for high integration without stressing the silicon substrate. The method of manufacturing a semiconductor device of the present invention provides a method of manufacturing a semiconductor device in which a separation layer can be formed. , a step of forming a photoresist having a device region shape on the silicon nitride 1g film; and using the photoresist as an etching-resistant mask, the silicon dioxide film and the silicon nitride 3
a step of selectively removing the 1c film and further removing the silicon crystal substrate to form a groove; a step of forming a silicon dioxide film in the groove portion using the silicon nitride film as an oxidation-resistant mask; A step of implanting impurity ions as a channel stopper into the trench as an implantation mask, a step of growing polycrystalline silicon on the silicon nitride film and in the trench to fill the trench, and etching the silicon nitride film on the element region as an etching-resistant mask. a step of etching away the polycrystalline silicon to below the surface of the silicon crystal substrate; a step of forming a silicon dioxide film on the silicon nitride film and in the trench to fill the trench; and a step of covering the entire surface of the device region with photoresist. and a step of removing the photoresist to below the interface of the silicon dioxide film, and using the photoresist remaining in the groove and the silicon nitride film covering the element region as an etching-resistant mask, removing the silicon dioxide film to the surface of the silicon substrate. The method includes a step of removing by etching.

Next, embodiments of the present invention will be described using the drawings.

FIG. 4 ((roll) to (j)) are 1-root cross-sectional views for explaining one embodiment of the present invention.

First, as shown in FIG. 4(a)K, a silicon dioxide film 42 is formed on the surface of a P-type silicon substrate 41 by a thermal heating method, a silicon nitride film 43 is formed thereon, and then the nitride film 42 is formed on the surface of a P-type silicon substrate 41. A photoresist 44 having a device region shape is formed on the silicon film 43.

Next, as shown in FIG. 4 (bl), using the photoresist 44 as an etching-resistant mask, the silicon nitride film 43, silicon dioxide film 42, and silicon substrate 41 in the non-element region are etched to a depth of 1 μm or more. A groove 45 is formed.The etching method is, for example, when etching an electrified silicon film or silicon dioxide film, a gas containing CF is used, and when etching a silicon substrate, reactive sputtering using a gas containing CC1, F is used. is appropriate.

Next, as shown in FIG. 4(C), grooves 4 are carved by thermal oxidation.
A silicon dioxide X film 46 is formed on the surface of the groove 45, and then, using the silicon nitride film 43' covering the surface of the element region as a mask for ion implantation resistance, for example, borium is implanted into the bottom of the groove 45, which is a non-element region. A channel stopper region 47 is formed.

Next, as shown in FIG. 4(dl), polycrystalline silicon 48 is grown over the entire wafer by the CVD method to completely fill the trenches.

Next, as shown in FIG. 4 (6), silicon nitride 1!143
' and silicon dioxide #[46] are used as an etching-resistant mask, and the polycrystalline silicon 48 is removed by etching to below the surface of the silicon substrate. It is appropriate to stop the etching of polycrystalline silicon within 1 μm (the surface of the silicon substrate).

Next, a silicon dioxide film 49 is grown on the entire surface of the wafer by plasma CVD as shown in FIG. 4 (fl). The thickness of the silicon dioxide film is set so that the interface of the silicon dioxide film in the groove is near the surface of the silicon substrate.

Next, as shown in FIG. 4(1), a photoresist 50 is formed on the entire surface of the wafer.

Next, as shown in FIG. 4(h), 5° of photoresist is etched, and 50° of photoresist is etched only on the groove.
' leave. A suitable method for etching the photoresist is, for example, plasma etching using an enemy or reactive sputter etching.

Next, as shown in FIG. 4(1), a photoresist 50'
Then, using the electrified silicon film 43' as an etching-resistant mask, the silicon dioxide film on the element region is removed by etching down to the surface of the silicon substrate.

Next, as shown in FIG. 4N), the photoresist 5σ silicon nitride $43' and the silicon dioxide film are removed to complete the element isolation layer.

Next, a method for manufacturing an insulated gate field effect transistor to which the present invention is applied will be described.

FIGS. 5(1) to 5(C) are process cross-sectional views for explaining a method of manufacturing nine insulated gate field effect transistors to which the present invention is applied. It is assumed that an element isolation layer shown in FIG. 4(j) has already been formed on the semiconductor substrate to be used.

First, as shown in FIG. 5, a gate oxide film 51 is formed in the element region by thermal oxidation, and then a gate electrode 52 made of polysilicon is formed.

Next, as shown in FIG.
Source/drain regions 53 and 53' are formed.

Next, as shown in FIG. 5(C), silicon dioxide 154 is formed around the rug gate electrode by thermal oxidation, and a silicon dioxide deposit 55 is formed by CVD, and conductive holes are formed in this. Then, a conductor wiring 56 made of aluminum or the like is formed. As a result, an insulated gate field effect transistor to which the present invention is applied can be obtained. In the above application example 11n channel insulated gate field effect transistor of the present invention, element isolation of the complementary field effect transistor and the pibo two transistor of the present invention is obtained. What can be applied to I! Not even R5.

As explained in detail above, according to the present invention, the space for isolation between elements can be made small, and the difference in pattern conversion from mask dimensions can also be kept very small. Semiconductor devices suitable for high integration can be easily obtained.

[Brief explanation of drawings]

The first figure is a cross-sectional view of an example of a conventional element isolation layer, and FIG.
) to (C) 1-i: Process cross-sectional views for explaining an example of a conventional method for forming an element isolation layer, Figures 3(a) to 3) show other examples of a conventional method for forming an element isolation layer. Figures 4 ((roll) to (J) are process cross-sectional views for explaining one embodiment of the present invention, and Figures #!5 ((roll) to (C)
J is a rounded process sectional view illustrating a method of manufacturing an insulated gate field effect transistor to which the present invention is applied. 11.21.31.41...Silicon substrate, 1
2.32゜42...Silicon dioxide film, 23, 2
3', 33, 43, 43'...Electrified silicon film, 24.34.44...Photoresist, 25
．． 35.45...Groove, 36.46...
・Silicon dioxide film, 17.47...Channel stopper region, 18°28...S1 pseudo separation layer, 3
8, 38', 48, 48'...Polycrystalline silicon, 39.49.49'...Silicon dioxide film, 50.50'...Photoresist, 51...・
... Gate oxide film, 52 ... Gate electrode, 5
3.53'...source/drain region, 54.
... Silicon dioxide film, 55 ... Silicon dioxide film by CVD method, 56 ... Conductor wiring. Figure 5

Claims (1)

[Claims] a step of forming a silicon dioxide film on the surface of a silicon crystal substrate and forming an electrified silicon film thereon; a step of forming a photoresist having an element region shape on the electrified silicon Xg; a step of selectively removing the silicon dioxide film and the electrified silicon film and further removing the silicon crystal substrate to form a ceramic; a step of forming a silicon dioxide film in the groove portion using the electrified silicon film as an oxidation-resistant mask; a step of ion-implanting impurities into the groove as a channel stopper using a silicon film as an ion implantation-resistant mask; a step of growing polycrystalline silicon on the electrified silicon film and in the groove to fill the groove; A step of etching away the polycrystalline silicon to below the surface of the silicon crystal substrate using a silicon film as an etching-resistant mask, a step of forming a silicon dioxide film on the enhanced silicon film and in the groove to fill the trench, and a step of using photoresist to fill the groove. a step of covering the entire surface of the device; a step of removing the photoresist to below the interface with the silicon dioxide film; and a step of removing the photoresist remaining in the groove and the electrified silicon film covering the device region as an etching-resistant mask to remove the silicon dioxide. 1. A method for manufacturing a semiconductor device, comprising the step of etching a film down to the surface of a silicon substrate.