JPS587860A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To raise alpha-ray resistance intensity of a semiconductor memory device by forming a memory cell on a low impurity density semiconductor layer formed on a high impurity density substrate, forming a reverse conductive type high impurity density buried layer at least under the memory cell, and applying the prescribed voltage thereto. CONSTITUTION:A low impurity density thin P<-> type epitaxial layer 2 is grown on a high impurity density P<+> type substrate 1, and N channel MISFETQ1- Q4 for memory cells are formed. In this RAMIC, high density N<+> type diffused regions 8, 9 passing elevationally through the layer 2 are formed at both ends of memory arrays M-ARY1-M-ARY4, and an N<+> type buried layer 10 is formed only directly under the memory arrays continuously to the diffused layers. A positive power source voltage VCC is applied from the electrode 11 to the layer 10. In this manner, alpha-ray resistance intensity is raised, thereby performing a normal memory function.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, for example, from M (Met −
a1 engineering n5u14tor 88m1oonduotor
) type static RAM, dynamic RAMj/
(This is related to

Mf'r channel MIS field effect transistor (hereinafter referred to as
In the case of ft-RAM, the storage element (memory cell) is constructed using a high resistivity P-type to lower the junction capacitance and improve the switching speed and substrate bias effect. A silicon substrate may be used. However, when a memory cell is provided on a high resistivity substrate, the depletion layer tends to spread from the PM junction formed by the drain region of the M-81FIT to the substrate side, reducing the junction capacitance. A friend who turns out to be weak.

That is, when a@ emitted from uranium, thorium, etc. contained in the package of the RAM device 0 enters the substrate, electron-hole pairs are generated due to the energy of It easily diffuses into the drain region and lowers the drain potential.
C neutralizes the accumulated positive charge. This phenomenon is facilitated by the low impurity concentration of the substrate, which increases the lifetime of the electrons.

In this way, the storage function of the memory cell is inhibited and the output voltage characteristics during reading are adversely affected.As a countermeasure, high impurity IIp! It is conceivable to form an N-channel MIFIT in a thin P-type epitaxial layer with a low impurity concentration that is grown on the surface of a P-type silicon substrate. In this case, the effect of carrier Q due to αiIK can be somewhat reduced by restricting the extension of the depletion layer with an epitaxial layer and by shortening the carrier lifetime with a high-concentration substrate, but it is still possible to obtain sufficient α-ray resistance. This has not yet been achieved.

Therefore, it is an object of the present invention to provide a storage device with high radiation resistance that can maintain the memory retention function normally against radiation l/IjK such as α resistance.

In order to achieve all of these objectives, according to the present invention, in a semiconductor unit equipped with an epitaxial layer as described above, a buried layer of a high impurity concentration of the opposite conductivity type is provided at least under the memory element, and the buried layer is A predetermined voltage is applied to the

That is, one of the electron-hole pairs Q) is generated by the radiation m.
'Trap the F-V rear to the above buried layer I, CMXHP
At the same time as preventing the spread of ivy into the active area,
The other carrier is drawn to the epitaxial layer and the power supply side of the semiconductor substrate. As a result, even if carriers are generated by radiation, the memory retention function of the memory cell is not affected, and radiation resistance can be increased.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments in which the present invention is applied to an MIS type static RAM will be described in detail with reference to the drawings.

First, regarding FIG. 1, the static RA according to this embodiment
The layout pattern of the MIC will be explained.

This RAMIC may have a 4-mat system in which memory plays are divided into four parts within one IC chip (semiconductor chip incorporating a semiconductor integrated circuit device), for example.
94 memory plays M-RY, each consisting of a plurality of memory cells M-011fL.

M-MURY, , M-MURYs and M-MURY4 are arranged in the chip separately from each other.

M-MURY and M-MURY are written on the 10,000 side of the engineering C chip, and M-MURY and FU-MUFTY are written on the other side of -F:. A row decoder R-DOR for M-MUs RYI to M-MU RY4 is provided in the center of the C-chip sandwiched between the sections. Also, M-MuR
between Y, and R-DOR, and between M-RY, and R-DO
Between R and M-MU RYI to M-Itya's friend word driver `` '' + and WD @ are written. One end of M-MURYI to M-MURY4 is in contact with lIK, k
-MuRYl~M-MURY4's friend column switch O
-El w, % O-B Y, % C-day W, and 0-
8W4 is provided, and further adjacent to 0-8W, ~0-8W4, column decoders 0-DOR, 0-DOR, 0-DOR, and 0-DOR for M-MURY, ~M-MURY, −
DOR4 is provided.

Also, in contact with these decoders, M-MURYI~M-
MURY4’s friend sense amplifier” 1% 8 A1.
6M1 and 11A4 are arranged respectively. 8. Position lc#i close to M1 to B4, 7 dress signal M4 to M1.
address parameters for DBs-, and MUDBI
, are arranged. The data output buffer DOB is adjacent to the program DB, -s, and the data output buffer DOB is also adjacent to the ADBI, -s.
W signal person Kabatsu 7a Wl! -B, 0B (No. I1 entry type Kabatsufaro S-B and data person Kabatsufaro SB are arranged.Furthermore, along the periphery of one end of the IC chip, address signal application pads P-mu S and P-mu 6, Data signal extraction pad p-pout.

WT! A signal application pad P-Wl, ground potential connection pad P-GliD, 08 signal application pad P-08° data signal input pad P-D1n, address signal application pad P
-A, P-Mu's house and P-ginseng are arranged. Ten thousand,
In contact with the other end side of M-MU RY, to M-MU RY4, there is a data line reduction load circuit DLO,.

DLO Tomi, DI, 03 and DLO4 are arranged. The M8P]WIC that constitutes these load circuits has address signal tables 0""AI, MU1, address signals DBI for M1, and MUDBs adjacent to each other on the left and right. . Adjacent to this MDBskC, address signal application pads P-4, P-3, P-3, P-3 and P-
, power supply voltage voo supply pad P-VOO%, address signal application pad P-mu'11%, P-mu11%, F-mu■ and P-mu1 are arranged.

The memory cells constituting each memory array of this RM MIO have a structure as shown in FIGS. 2 and 3.

A low impurity 1lIFiILO thin hP- type epitaxial layer 2 is grown on a P+ type silicon substrate 1 with a high concentration of ions. Qas%
MI87ITQh';
6 is a drive transistor with Lmu memory retention function, and each polysilicon gate electrode G1, Gl is a Reiko 8FI.
Each of TQ1%q1 is connected to the type drain region 3.4 by a direct contact method. Gate electrode GI
, Gl are further extended and connected to a power source at a voltage v0° via a high resistance polysilicon portion (load resistance R1s Rr ) not doped with impurities and a low resistance polysilicon arrangement t. M engineering 8FMTQ3 % Qs K common N+ya source region 5 is aluminum AfJiG M
DK includes 1iI ground type ◇ Also, transformer gate and lk; EsMX 81FMT Qa,
Qa u, the word l of horisilicon! W (common gate electrode), a C-type drain region 4.3 common to the F TQ1% Qs, and an H+-type source region 6.7 connected to the aluminum data IID% D, respectively. There is.

As shown equivalently in FIG. 5, this memory cell has a pair of inverter circuits consisting of a polysilicon load resistor R1, an MIS type drive transistor Qm connected in series with an R, and these inverter circuits By cross-coupling the human outputs, a seven-lip flop is constructed as an information storage means. In addition, each inverter circuit KFi
, M-engineer 8FICTQ wealth for transmission gate,
Ql is connected. One terminal of load resistor R1, R@ has polysilicon wiring! Voltage V through lt. 0 is applied, and each source terminal Fi is grounded. Then, the output of the first inverter is input from the second inverter M to the gate terminal of FITq3, and the output of the second inverter is input to the gate terminal of MI81FIITQx of the first inverter. . The cutting edge of the first inverter is from M'
I'll send the data via NTQat to the 1st and 2nd interface.
Data via O output tj M X B F I T Q 4! l1IDK added. In other words, the transmission gate q1%Qa is used as an address means for controlling the information transmission line between the flip-flop and the complementary data line pair DD.
[Will be turned off by the applied address signal.]

The characteristic configuration of the RA work O according to this implementation IIK is as follows:
High-concentration N+ type diffusion regions 8.9 are formed in both 11 portions of each of the memory arrays M-MU RY1 to M-MU RY4 (see FIG. 1), vertically penetrating the epitaxial layer 2, and these diffusion regions N only immediately below each memory array consecutively to
``!II! The formation field of the inclusion layer 10 is lost 1: IiS
Ru. This buried layer 10 is located in the relationship between the epitaxial layer 2 and the substrate 1, and serves to separate them from each other, and also plays an extremely important role for carriers caused by %AlHK. That is, as shown in an enlarged view of the main part in FIG. 4, a positive power supply voltage V is applied to the buried layer 10 from the aluminum electrode 11 through the N type region 8. 0, while applying a negative power supply voltage vBB to the epitaxial layer 2 and substrate IK, even if α rays 12 are incident and electron-hole pairs are generated, especially in the epitaxial layer 2. , the electrons are attracted by the positive electric field of the buried layer 10 and
The trap will make you vomit. As a result, the electrons are prevented from diffusing into the drain region 4, and the drain potential is stably maintained, allowing the memory cell to perform its normal storage function. In addition, holes are collected into the epitaxial layer 2 and the substrate ill, which are at a negative potential.

In this manner, the a-tolerance strength of the memory cell can be reliably improved by virtue of the fact that the buried layer can effectively trap carriers due to the a-tolerance. In addition, this a resistance strength is
It is expected that it will be on the same level as the 0M0III type memory cell, which can trap electrons to the substrate side using the potential difference between the well and the substrate by providing BiTt, and is thought to have lower α-ray resistance than the 0M0a type memory. It is possible to thoroughly read the great gospel.

Furthermore, due to the presence of the P-type epitaxial layer 2, the junction capacitance of the PN junction in the N-type active region of the M-871T can be appropriately reduced.In addition, the above-mentioned buried layer 10T is not formed in the peripheral circuit element part. It is also important to note that this is not the case (see Figure 3). That is, for example, row decoder R-DOR
Since the above-mentioned buried layer 10 does not exist in the M process 5FITT:1 that constitutes 't-, an abnormal voltage is applied to one of the N+ diffusion regions 13 and 14 (drain region) which becomes the source or drain region. In this case, even if a current B flows from the drain region due to the avalanche effect, the current flows K in the vertical direction (deep field direction) of the B/fi wafer. Therefore, the increase in power supply voltage VBB due to BK (below the channel) can be further suppressed to a minimum, and the drain potential can be suppressed from decreasing and the withstand voltage of 7 can be sufficiently maintained. CtL
On the other hand, if the above-mentioned buried layer IO is present in the decoder section, B flows only in the lateral direction due to the ti of the epitaxial layer 2, so the voltage drop due to ■BB is There is a fear that this will cause a phenomenon in which the drain potential decreases more and more, leading to destruction of K. Note that this phenomenon occurs in memory cells with a small amount of current and is likely to occur in the peripheral circuit element section, but the structure of this embodiment effectively prevents the increase in voltage vBB due to H in the peripheral circuit element section. It's broken. In addition, when the peripheral circuit section is configured as described above, the peripheral circuit section itself has a large load capacity and a large current supply capability, so its α-resistance is large and the memory cell V is protected. W
The embedded layer IO is not necessary but necessary.

Next, the method for manufacturing the structure shown in FIG. 3 will be described in detail with reference to FIG. 6.

First, as shown in FIG. 6A, a mask 15i made of 5i03 is formed by 0VD (chemical vapor deposition) on the entire surface of a P-type silicon substrate l, and this is subjected to known photoetching to form the buried layer lO. A portion corresponding to the N+ type diffusion region 16 is removed and arsenic or phosphorus is thermally diffused from there.
Form into 1.

Then, after removing the mask 15t by etching, the 6th B
As shown in the figure, a single crystal silicon layer 2 is deposited on the entire surface by OVD.
′ is epitaxially grown. At this time, the impurity in the M type diffusion region 16 is post-diffused to form an N+ type buried layer lO between the epitaxial layer 2 and the substrate l.

Next, as shown in FIG. 6C, a field 810n film 18t for element isolation is grown by a known selective oxidation technique using the silicon nitride film 17 as a mask.

After removing the mask 17 and the underlying 51o1 film 19i by etching, the gate oxide film 20 is grown by thermal oxidation in a mono-oxidizing atmosphere as shown in FIG. 6D.
Otregis) 21 in a predetermined pattern and gate oxidation! Etch a part of s20.

Next, as shown in FIG. 6z, arsenic or phosphorus is thermally diffused from the removed portion of the gate oxide film 20 into the epitaxial layer 2 on both sides of the memory array region. N+ type diffusion regions 8 and 9 are formed passing through the upper and lower parts of r and reaching the buried layer lOK, respectively. At this time, although not shown, the memory array area and peripheral circuit area may be covered with an appropriate mask (for example, photoresist), or the diffusion area 8 may be covered with a suitable mask (for example, photoresist).
．． After the -H gate oxide film is removed after forming 9, a new gate oxide film may be formed again.

Next, as shown in FIG. 6F, the polysilicon film Gt is made to have a length of 1 kg over the entire surface by GVD and subjected to a known phosphorus treatment, and then patterned by a known photoetching process to form each polysilicon film Gt that will become a gate, a pole, or a wiring. Gt, Gi, 22 are formed respectively.

Next, as shown in FIG. 6G, the surface of each polysilicon film is thermally oxidized to form a thin layer 810. A film 23 is formed, and then the regions of the load resistors R, , R, mentioned above are temporarily covered with a photoresist, and then the entire surface is irradiated with an ion beam 24 of arsenic or phosphorus. As a result, each polysilicon film and field S
Complete ion implantation into the epitaxial layer 2 using a gate oxidation fi120'kJ as an iOtgk mask, and N type region 3.4.5.13 as a source or drain region.
．． 14 respectively.

Next, as shown in FIG. 6H, a phosphosilicate glass film 25 is deposited and exploded on the entire surface by C'VD, and then the glass film 25 and the underlying layer are sequentially etched by 10 mm by known photoetching to form each contact hole 26. and,
Aluminum is coated with N on the entire surface using, for example, vacuum evaporation technology, and patterned using known photoetching to form a third layer.
As shown in the figure, the Al-I arrangement 111 is formed with GNDt. Although not shown, a final passivation film and the like are further applied to complete the static RAM construction 0.

Although the present invention has been illustrated above, the embodiments described above can be modified based on the technical idea of the present invention.

For example, the above-mentioned buried layer 10 may be formed over the entire IC, or may be formed only at necessary locations as described above. Alternatively, the conductivity type of each semiconductor region described above may be converted to the opposite conductivity type. The structure of the memory cell described above can be varied in various ways. However, the present invention can also be applied to dynamic RAM (including one-transistor type), etc.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a plan view schematically showing the layout of a static RAM;
FIG. 2 is an enlarged plan view showing the main part of the memory array section.
FIG. 3 is a sectional view taken along the line X-X1ij in FIG. 2, and FIG. 4 is a! 3 is an enlarged cross-sectional view of the main part of FIG. 3 to explain the situation at the time of l-injection, FIG. 5 is an equivalent circuit diagram of a memory cell, and FIGS. 6A to 6A.
FIG. 6H is a cross-sectional view showing the entire manufacturing process of the structure shown in FIG. is α-12
2ri polysilicon wiring, Q, + and QI are MI for driving
Japanese yg'r, Qs and Q4Fi transmission gate bar work 8IPKT, Q, H row decoder M work 81F
ET%R, and Rm#-1t polysilicon load resistance, D
and D are aluminum data line, GNDFi aluminum ground line, and w#i polysilicon word line. 305

Claims (1)

[Claims] 1. A semiconductor layer of a first conductive lid is formed with a low impurity concentration on a semiconductor substrate of a first conductivity type with a high impurity concentration.A semiconductor layer is provided with a memory element portion and a peripheral circuit element portion in this semiconductor layer. In the storage device, a buried layer of a second conductivity type with a high impurity concentration is formed between the semiconductor substrate and the semiconductor layer at least under the storage element, and the buried layer has a second conductivity type buried layer that has a high impurity concentration between the semiconductor substrate and the semiconductor layer. A semiconductor memory device characterized in that the semiconductor memory device is configured to apply a voltage having a polarity opposite to that of the layer.