JPS5875250A - Digital information processor - Google Patents

Abstract

PURPOSE:To improve arithmetic processing efficiency by switching arithmetic register groups when a subroutine call is made. CONSTITUTION:An arithmetic logical device 6 consists of an arithmetic logical device (ALU) 9, arithmetic register groups 10-13 for temporarily storing an intermediate arithmetic result by said ALU9, the 1st and 2nd multiplexers 14 and 15 for switching data sources to the ALU9, and a buffer 16 for transfer control over output from the ALU9. When a subroutine call instruction is latched in an instruction register 3, a prescribed arithmetic register group among said groups 10-13 is selected by a register switching means 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technique for switching arithmetic registers in a digital information processing device such as an electronic computer that is equipped with an arithmetic register group consisting of a plurality of arithmetic registers.

Generally, a digital information processing device such as an electronic computer is equipped with an arithmetic register for temporarily storing information on intermediate results of arithmetic operations or their address information. The intermediate results of the calculation stored in this calculation register are no longer needed once the series of calculations has finished, but if there is an instruction that transfers control to another program area during the calculation, such as a subroutine call, If left as is, the stored contents of the calculation register up to that point will be erased by the processing of another program area based on the subroutine call, so the stored contents of this calculation register should be temporarily saved to the main memory, and then the contents of the calculation register will be erased by the processing of another program area based on the subroutine call. When control returns from another program area based on the program, it is necessary to load information on the intermediate result of the operation into the operation register again. For example, the most widely used method for saving arithmetic registers is to use an instruction to save the contents of the arithmetic registers that need to be saved to a sufficient space in the main memory before making a subroutine call. After writing to the PC and executing the program based on the subroutine, when returning from the subroutine and returning to the original processing, the contents of the arithmetic register written to the main memory as described above are written to the main memory based on the arithmetic instruction. A method was adopted in which the data was read from the memory and written to the arithmetic register again.

However, in conventional electronic computers etc. that adopt this type of saving method, saving of arithmetic registers must be taken into account when creating a program, which has the disadvantage of complicating the program and increasing the effort required to create the program. Since the saving is done by software before a subroutine call, there is a disadvantage that the time required for a subroutine call is long and the efficiency of arithmetic processing is lowered.

The present invention has been made based on the above circumstances.When a subroutine call is made, the arithmetic register group is switched to the next one, and when a return to the original processing is performed, the original arithmetic register group is used. By making it possible to switch between groups and use them, and taking into account the saving of arithmetic registers, programs can be created quickly, and the effort required to create programs can be reduced.
It is an object of the present invention to provide a digital information processing device that can improve calculation processing efficiency.

The apparatus of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an electronic computer as an embodiment of the apparatus of the present invention, and FIG. 2 is a block diagram showing an embodiment of register switching means. In Figure 1, numeral 1 is a command register into which macro commands, which are assembly language instructions, are loaded.The control unit includes a 2H program counter, program memory, controller, clock pulse oscillator, etc., and sequentially executes the necessary instructions. This instruction is latched every clock cycle from the control unit 2.

In addition, between the two data buses DBI and I) B2, there is a buffer 4 for data transfer with some external equipment, and a main H
1i storage device 5 and an arithmetic device 6 are provided. This main memory device @5 is composed of a main memory 7 that stores data from the data bus DBI, and a first buffer 8 that controls transfer of output from the main memory 7.

Further, the arithmetic unit @6 includes an arithmetic logic unit (hereinafter referred to as ALU) 9 and an arithmetic register unit, for example, a plurality of arithmetic register groups for temporarily storing intermediate results of arithmetic operations by the ALU 9. 1st to 4th operation register group 10
13, and a first mapper 16 that switches the data source to the ALU 9. Further, a hardware controller 17 is provided which decodes the contents latched in the instruction register 3 and controls hardware such as the main memory #5 and the arithmetic unit 6. Note that control signal path lines from this hardware controller 17 to each piece of hardware are not shown. Further, register switching means 18 is provided for selecting a predetermined arithmetic register group from the first to fourth arithmetic register groups 10 to 13 when a subroutine call instruction is latched in the instruction register 6.

Each of the arithmetic register groups 10 to 13 includes a plurality of arithmetic registers, and in this embodiment, the arithmetic registers in each of the arithmetic register groups 10 to 16 are to be switched at once. By selecting a predetermined arithmetic register group by the register switching means 18, all the arithmetic registers (including C) are switched all at once.

t7' (the command register 1 and the control section 2)
A control device 26 is composed of the instruction register 6 and the hardware controller 17.

Here, an example of this register switching means 18 will be explained in detail based on FIG. 2. A decoder 19 is connected to the instruction register 6, and when a subroutine call instruction is output to the decoder 19, an active signal '@S1 is output to the first AND gate 20, and the program called from the subroutine is When a return command is output to return control to the second AND gate 21, the active signal S2 is output to the second AND gate 21, and both AND gates 20 and 21 receive the clock pulse from the control section 2. It is configured to be inputted and ANDed with the active signals S+ and S2. A counter 22 is provided which receives the outputs of both AND gates 20 and 21 as input, and counts up when there is an output from the first AND gate 20.
When there is an output of 1, a down count is performed. Control signals corresponding to the up-count and down-count are input to the first to fourth arithmetic register groups 10 to 16, so that a predetermined arithmetic register group is selected. ~The memories of the fourth arithmetic register group 10 to 16 are given address numbers sequentially incremented from the first arithmetic register group 10, and a predetermined address number is assigned based on the control signal from the counter 22. The specified arithmetic register group is selected. In particular, assuming that the memory of each arithmetic register group 10 to 13 can be read and written in one machine cycle of the computer, the time required to switch the arithmetic register group is The operation of the 0-order electronic 11n machine configured in this manner will be explained, in which it is possible to extremely shorten h1. This electron H
In the E machine, the command register 1 is macro-controlled, and the control unit 2 sequentially sends the necessary instructions to the instruction register 6, and when they are latched at every clock pulse cycle of the control unit 2, the instructions are transferred to the instruction register 3. Depending on the contents of the above No. 1-Dware Controller 17. Various processes will be performed via the main memory device [5, arithmetic unit 6, etc.]. Therefore, in particular, the operation register group is saved when a subroutine call instruction (hereinafter also simply referred to as a call instruction) is latched in the instruction register 3, and the return instruction (hereinafter also simply referred to as a return instruction) that returns control from this subroutine to the calling program. ) is latched, and the recovery action will be explained. First, it is assumed that the first arithmetic register group 10 is used based on the first reading program and no processing is performed. At this time, when the call instruction is latched in the instruction register 3, this call instruction is input to the decoder 19, and an active signal S+ is output to the first analogue controller 20, and the clock signal from the control section 2 is output. A logical product with the pulse is taken, and an active signal is output to the first AND gate 20 and the counter 22. In this counter 22, the address number of the first arithmetic register group 10 is transferred to the second arithmetic register group 1.
A control signal corresponding to the up-counted address number is output to the valley operation register group 10 to 13, and the operation register group of the address number corresponding to this control signal, that is, the second
The performance register group 11 will be selected. By selecting the second arithmetic register group 11 in this way, the second arithmetic register group 11 is used in the subroutine, and the first arithmetic register group 10 V
The contents of the stored arithmetic information will not be erased but will be saved. This saving is not done by software as in the past, but by hardware by the register switching means 18 that operates based on the call instruction 1c, so the effort required for program creation can be reduced, and moreover, it is possible to It is possible to shorten the time required for the first step, and to improve the efficiency of subsequent arithmetic processing. After executing the subroutine, if a return instruction is latched in the instruction register 3, the decoder 19 sends the function 1! to the second AND gate 21. I
I 1g S2 is outputted and logically logically ANDed with the clock pulse - [an active signal is outputted from this second AND gate 21 to the counter 22. And this counter 2
2, the address number of the second arithmetic register group 11 is counted down as the address number of the first arithmetic register group 1D, and a control signal corresponding to this down-counted address number is sent to each arithmetic register group 10 to 16.
The arithmetic register it of the address number corresponding to this control signal, that is, the first arithmetic register group 10, is selected. By selecting the first arithmetic register group 10 again in this way, the first arithmetic register group 10 is recovered, and processing based on the first called program is continued using the arithmetic information stored therein. It will be abducted.

Note that the above-mentioned embodiment is just an example, and it goes without saying that the valley member can be replaced with another member having the same function. For example, in the above embodiment, the arithmetic register section Q is configured from the first to fourth arithmetic register groups. It is possible to increase the number of It is also possible to configure a digital information processing device by adding a group of arithmetic registers that are not switched by a conventional call or return.

aυ ...Counter, 23...Control device.

As is clear from the above description, in the digital information processing device of the present invention, when a subroutine call is made, the arithmetic register group can be switched to the next one and used, and a return can be made to the original processing. At times, it is possible to switch to the original arithmetic register group and use it, and as a result, it is possible to create a program without considering the saving of the memory contents of the static register, which in turn reduces the labor required to create a program and improves VC calculation efficiency. It has excellent effects such as being able to improve the

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an electronic computer as an embodiment of the device W of the present invention, and FIG. 2 is a block diagram showing an embodiment of register switching means. 10...First operation register group, 11...Second
arithmetic register group, 12...sixth arithmetic register group, 13... fourth arithmetic register group, 18...
Register 1. Switching means, 19.. Decoder, 20.. First AND gate, 21.-
・Second AND gate, 22 (1 no

Claims (1)

[Claims] In a digital information processing device that processes digital information by performing arithmetic operations using multiple arithmetic registers based on instructions from a control device, a subroutine call instruction from the previous control device causes the arithmetic registers to be used. A register switching means is provided that not only switches to another arithmetic register but also switches to and restores the original arithmetic register by a return instruction from a subroutine, and automatically saves and restores the arithmetic register that was used before the subroutine call instruction. A digital information processing device characterized by: