JPS5842267A - Data storage device and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data storage device, and particularly to a data storage device using semiconductor integrated circuit technology.

Such devices currently available on the market have a planar integrated circuit, each part of which performs two separate functions: data storage and access to the data storage portion of this circuit. However, each transistor or other active element in a planar integrated circuit can only store one bit of data.
Although high-density packaging has been achieved, the amount of data that can be stored on an integrated circuit is actually extremely limited.

An object of the present invention is to provide a data storage device using semiconductor integrated circuit technology that overcomes this problem.

In accordance with the present invention, a data storage device includes a planar integrated circuit formed on a surface of a body of electron storage material, the storage material comprising a plurality of spaced apart rows of spaced discrete electrical charges. Provide storage locations, each column extending in a direction perpendicular to the plane of the integrated circuit, and the integrated circuit has access to these charge storage locations.

Preferably, the integrated circuit means has a control means on the side of said body remote from the integrated circuit, whereby, by control of the integrated circuit, a storage location proximate to said control means in a selected one of said columns is controlled. Charge can be injected into the integrated circuit, whereby the charge of a selected column is transferred in the direction towards the integrated circuit to the respective next adjacent storage location in that column.

In such a device, the storage locations of each column of storage material typically correspond to each element of the integrated circuit to which charge in an adjacent storage location of the storage locations of the corresponding column is transferred by operation of said control means. are doing.

In one particular embodiment of the invention, the body of storage material is comprised of a semiconductor material, and each storage location is comprised of a material with a relatively low dielectric constant compared to the material separating the storage locations.

In one such implementation, each storage location is comprised of silicon and the material separating each storage location is comprised of silicon oxide. This may be doped with a suitable impurity to increase charge mobility.

In such devices, the charge injection is an avalanche
Breakdown mechanisms suitably take place, and charge transfer between storage locations takes place suitably by tunneling and transport mechanisms.

This transport mechanism may be assisted by photons if necessary.

In such devices, the control means are adjacent to the respective end of each row of storage locations. It is desirable to have a -0 junction. Therefore, charge injection is performed by applying a high reverse bias Y to the corresponding p-n junction,
Charge transfer is effected by applying a suitable potential between the electrode of the corresponding p-n junction and the integrated circuit substrate.

One data storage device according to the present invention will be described below by way of example with reference to the accompanying drawings.

Referring to FIG. 1Y, the device is formed on a silicon substrate 1. As shown in FIG. On one of its main surfaces, this substrate supports a body of electron storage material in the form of a layer 5 of silicon oxide, in which islands 5 of silicon are formed. island 5
are arranged in rows of a rectangular matrix extending perpendicular to the storage material-substrate interface 7, each row being shown in the drawing as containing four islands, but usually there are many, e.g. Equal to the number of bits contained in a byte stored on the device.

The six islands constitute charge storage sites within layer 3, as will be explained in more detail below.

Referring now also to FIG. 2, in the substrate 1 adjacent the interface 7 there are a number of spacings t in the form of tape strips. A ten region 11 is formed, which extends at right angles to the ten region. This provides each pn junction adjacent to the end island of the islands 5 in each row. For each junction, the ten region 9 is closer to layer 3.

On the side of layer 30 remote from the substrate, a monocrystalline silicon layer 13 is provided, in which an integrated circuit is formed.

As will be explained in more detail below, this integrated circuit operates in conjunction with regions 9 and 11 to inject charge into islands 5 of any selected row of islands adjacent to substrate 1, Each charge on an island in a row is transferred to the next adjacent island in that row in a direction toward the integrated circuit. The islands in each column thus function as independent n-pit storage elements of the shift register type accessed by the integrated circuit, where n is the number of islands in a column.

- Details of this integrated circuit are not shown in the drawings, as this integrated circuit can be manufactured in any desired suitable form using known integrated circuit technology. However, this integrated circuit requires that each column of islands contain one element, for example a transistor v, into which charge is transferred from the end island of the corresponding column.

Charge injection is operationally performed by causing an avalanche breakdown of the p-0 junction corresponding to the island CD array where data is to be stored. Typically, this data is binary data, with "1" and "0" each represented by the presence or absence of charge accumulated on one island.

The substrate of an integrated circuit is usually grounded, in which case the required p-
The breakdown of the n-junction corresponds to a positive potential, for example 5. A relatively high negative potential, for example -15V, is applied to the + strip 11. ten area strip 9
This is done properly by applying .

Transferring the charge v in the direction towards the integrated circuit from one island 5 of one column to the next is carried out by the corresponding p + region 9VC.
, which is done by applying a negative potential, correspondingly.

Accordingly, the negative and positive voltages are not required in the area 11.

Transferring charge from the end islands in a column to the corresponding integrated circuit element is done in a similar manner.

The mechanism for transfer from one island to another, or to an integrated circuit, is to first Fowler-Nordheim tunneling of electrons from the island into the conductive band of the oxide, and then through the oxide 7 This is done by transferring it to the next island or integrated circuit.

To avoid charge build-up in one column, the transport time through the oxide is greater than the time for the majority of charges on an island to exit an island and tunnel into the oxide; It also corresponds to a voltage pulse of the form shown in FIG. 3 for carrying out the transfer. Apply to ten areas. The relatively high amplitude, relatively short tip 15 of this pulse injects charge into the oxide, and the low amplitude, long remaining portion 17 of this pulse provides the necessary charge transfer to the next island. , the possibility that charges will exit from the next island due to the tunnel effect is not dangerous until the second transfer pulse is applied.

Note that with reference to FIGS. 1 and 2, [in the particular device described above, it is possible to access individual columns and inject charge, but it is not possible to simultaneously access all columns corresponding to one ten area. It is necessary to transfer charge to row 5. However, in other arrangements according to the invention, integrated circuits and corresponding control means may be provided to access each column separately and to perform both charge injection and transfer.

A modification of the device described above with respect to FIGS. 1 and 2 is such that an integrated circuit illuminates six islands and provides nine tunneling effects with the aid of photons. However, the light used has an energy smaller than the forbidden band width of silicon and must be avoided to avoid affecting the integrated circuit. Area 9
In order to eliminate the unnecessary breakdown caused by the light irradiation due to the p-n junction between *11″ limit.

Located on one side of each column. It may be limited to -1 junction.

Alternatively, to improve the charge mobility in silicon oxide and increase the charge transfer rate, a high concentration of silicon or other impurities is introduced into the oxide, i.e., by ion implantation to provide an impurity band. The forbidden band width may be made smaller.

A suitable method of manufacturing the apparatus shown in FIGS. 1 and 2 will now be illustrated with reference to FIGS. 4-6.

First, in one surface of the silicon substrate 1, a + region 9 and a region 9 are formed. A region 11 is formed using any conventionally known impurity diffusion or implantation technique.

Referring to FIG. 4, next, ten areas 9 and. Alternating layers 19 and 21Y of silicon and silicon oxide are formed on the substrate over region 11. This is done by epitaxially growing silicon and oxide layers alternately or by epitaxially growing a silicon layer and
This silicon layer Y may be partially oxidized, the silicon layer may be further grown and partially oxidized, and this process may be repeated.

Referring now to Figures 5 and 6 (Figure 6 is
FIG. 3 is a plan view of the illustrated structure; ), then inject monoxide into the structure of the layer (St/810. , the assembly is heated to oxidize all of the monoxide-implanted silicon.The remaining portions 25 of silicon layer 19 are then separated by silicon oxide as needed to form a series of nine silicon islands.

Finally, a monocrystalline silicon layer is formed on the exposed surface of this layer structure, for example by recrystallization of the deposited polycrystalline silicon layer, and the monocrystalline silicon layer is formed using known techniques. form integrated circuits.

It should be noted that, although in the embodiments of the invention described above by way of example, the body of the storage material is made of silicon, this need not necessarily be the case. Therefore, the body of accumulated material is
It may be any material capable of storing charge in discrete storage locations therein and transferring charge from one storage location to another.

For example, a multilayer organic material that can be manufactured into a multilayer structure by the Langmuir-Prodgett method and has the property of accumulating and transferring charge between each layer by a mechanism similar to that described above. It has the potential to be suitably used as a storage material in devices according to the method.

In summary, a data storage device has a Brainer integrated circuit formed on a surface of a body of electron storage material;
The material provides spaced discrete rows of spaced discrete charge storage locations, each row extending in a direction perpendicular to the plane of the integrated circuit, and the integrated circuit provides access to these storage locations. It is something to do.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view schematically showing a part of the device according to the present invention, Fig. 2 is a diagram showing a portion taken by line - H in Fig. 1, and Fig. 3 is a voltage applied to the device in the operating state. Figures 4, 5, and 6 are diagrams showing the waveforms of each stage in the manufacture of this device. 1... Substrate 3... First part, Main body 5... Charge storage place 7... Surface 9.11... Control means 1S... Second part, Planar integrated circuit 19. ...Silicon layer 21...Silicon oxide layer 2S...Lattice pattern procedural amendment C spontaneous) September-7, 1981 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1 Name of the invention Data storage device and its manufacturing method 3 , Relationship to the amended person's case ゛ Name of patent applicant: The General Electric Company. P, L, C. , agent postal code 100

Claims (1)

Claims: A data storage device comprising a first portion for storing data and a second portion for accessing the stored data, the first portion comprising a body of charge storage material; The second portion is formed on a surface of the body of charge storage material and includes a nine-grain integrated circuit, the second portion being formed on a surface of the body of charge storage material and providing a plurality of spaced apart discrete rows of spaced apart charge storage locations. , wherein each column extends in a direction perpendicular to the plane of the integrated circuit. 2. The apparatus of claim 1, wherein said integrated circuit means is associated with control means on a side of said body remote from said integrated circuit, whereby selection of said columns is controlled by said integrated circuit. A charge can be injected into a storage location adjacent to said control means in a selected column, whereby the charge in a selected column is transferred to the next adjacent storage location in that column in the direction towards said integrated circuit. A data storage device with t% characteristics. S, IrI In the apparatus according to claim 2. Each column of storage locations in the storage material corresponds to each element of the integrated circuit to which charges in adjacent storage locations of the corresponding column of storage locations are transferred by operation of the control means. A small data storage device. 1@Claims 2 and 9 provide a device according to claim 3, wherein the body of storage material is made of a semiconductor material, and each storage location is relatively free of material compared to the material it separates from the storage location. A data storage device characterized by being made of a material with a low dielectric constant. (5) In the device according to claim 4, the storage location is made of 19:2y, and the material separating the storage location is enriched silicon, and 9:2y is doped with an impurity that increases charge mobility. A data storage device characterized in that it is made of common-sense silicon. 6. The device according to claim 5, characterized in that charge injection is performed by an avalanche breakdown mechanism, and charge transfer between storage locations is performed by a tunnel effect and a transport mechanism. data storage device. 7. Apparatus according to claim 6, wherein the control means is located adjacent to the appropriate end of each row of storage locations.
A data storage device comprising a junction. 8. a first portion for storing data and a second portion for accessing the stored data, the first portion comprising a body of charge storage material and the second portion comprising a body of charge storage material; including a planar integrated circuit formed in the plane of the body, the storage material providing a plurality of spaced discrete rows of spaced discrete charge storage locations, each row perpendicular to the plane of the integrated circuit; In a method of manufacturing a data storage device extending in the direction, the body of storage material is formed by forming alternating layers of silicon and silicon oxide on a substrate, so formed that the storage material of each column of the nine-layer structure is introducing oxygen into the portion between the regions where the locations are provided and heating the layer structure to oxidize the silicon portion of the layer structure into which the oxygen has been introduced;
A method for manufacturing a data storage device, characterized in that the data storage device is manufactured by: