JPS5839050A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5839050A
JPS5839050A JP56137431A JP13743181A JPS5839050A JP S5839050 A JPS5839050 A JP S5839050A JP 56137431 A JP56137431 A JP 56137431A JP 13743181 A JP13743181 A JP 13743181A JP S5839050 A JPS5839050 A JP S5839050A
Authority
JP
Japan
Prior art keywords
circuit
redundancy
integrated circuit
reliability
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56137431A
Other languages
Japanese (ja)
Other versions
JPS6211739B2 (en
Inventor
Masahiro Ouchi
大内 雅弘
Yoshinari Kitamura
北村 嘉成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56137431A priority Critical patent/JPS5839050A/en
Publication of JPS5839050A publication Critical patent/JPS5839050A/en
Publication of JPS6211739B2 publication Critical patent/JPS6211739B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/006Identification

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To enable to grasp the reliability of an integrated circuit by providing a simple selecting circuit and a decoder in the circuit, thereby discriminating the redundancy of a redundancy circuit from its exterior. CONSTITUTION:A redundancy circuit is checked by providing a circuit for examining how much the redundancy is retained on the same integrated circuit, thereby examining the redundancy and grasping the reliability of the chip. A circuit for examining the redundancy is composed of a simple decoder and a gate circuit. For example, the circuit has signal processors a1, a2, a3, b1, b2, b3,... majority decision circuits A1, A2, A3,... and decoder B, and these circuits are formed on the same silicon chip.

Description

【発明の詳細な説明】 本発明は集積回路に関するものである。[Detailed description of the invention] TECHNICAL FIELD This invention relates to integrated circuits.

従来、高倍1IliIcのシステムを実現する場合、2
つの方法が考えらnてきた。l)は、システムを構成す
る部品の信頼度を高めるものであり、他の1)?1.V
スTムの1部に故障が生じることをあらかじめ予想し、
冗長性を持った回路構成にし、1部に故障が起きても、
外部からは、故障と見なせない様にするものである。
Conventionally, when realizing a high magnification 1IliIc system, 2
I have thought of two methods. 1) increases the reliability of the parts that make up the system, and the other 1)? 1. V
Anticipate in advance that a part of the system will break down,
The circuit configuration has redundancy, so even if one part fails,
This is to prevent it from being seen as a failure from the outside.

冗長性を持った回路構成の代表的なものは第1図に示し
た多数決の原理を利用したものでおる。
A typical redundant circuit configuration utilizes the principle of majority voting shown in FIG.

第1図において@  811部g tagは同一回路で
あり。
In FIG. 1, @ 811 part g tag is the same circuit.

Alからの同一出力信号が入力さn% al*a2*a
、からの出力信号が、A2の多数決判定回路にに入力さ
n、多数決がとらn、単一の出方がA2から次段のbl
t bl t bsの回路に入力され、同様にして多数
決により単一の出力が得らnる。この様な回路構成にし
た場合、a@ tE12 ta畠のどnか1つが故障し
ても正し−い信号が次段の回路に送らnる。
The same output signal from Al is input n% al*a2*a
, the output signal from A2 is input to the majority decision circuit of A2.
The signal is input to the circuit t bl t bs, and a single output is similarly obtained by majority vote. With such a circuit configuration, even if one of the a@tE12ta is out of order, a correct signal will be sent to the next stage circuit.

しかし、  al eaz sagのどnか1つが故障
していても外部からは、システムは正常に動作している
ように見えるが、システムの信頼性は、al−a2as
がすべて正常に動作している場合に比べて大幅に低下す
る。al*IigeaBがプリント基板単位のシステム
の様な時は、a1駿a諺DaBを各々周期的にチェック
することによりシステムの信頼性を一定に保つことはで
きる。
However, even if one of the al-eaz sag is out of order, the system appears to be operating normally from the outside, but the reliability of the system is
significantly lower than if everything was working properly. When al*IigeaB is a system based on printed circuit boards, the reliability of the system can be kept constant by periodically checking each a1 and every DaB.

しかし、システム全体が一個のシリコン基板上に構成さ
nるような大規模集積回路で冗長度を持った回路構成に
しても、外部からその冗長度が判定できない様では、チ
ップの信頼度を判定できないことになり、結局システム
の信頼度t−判定する仁とは難しくなる。
However, even if the entire system is configured with redundancy in a large-scale integrated circuit such as one built on a single silicon substrate, if the degree of redundancy cannot be determined from the outside, it is difficult to judge the reliability of the chip. As a result, it becomes difficult to judge the reliability of the system.

本発明は、外部から集積回路の冗長度がどの程度残さn
ているかを判定する回路を同−牛導体基板上に設け、こ
の判定回路により集積回路の冗長度t−調べ信頼性の高
い装置を作るための集積回路を提供するものである。
The present invention examines how much redundancy remains in an integrated circuit from the outside.
A circuit is provided on the same conductive substrate, and the redundancy level t of the integrated circuit is checked using this judgment circuit to provide an integrated circuit for producing a highly reliable device.

本発明は、従来は、冗長回路が集積回路内部に設けらn
ていてもその冗長度が外部がら把握できなかったものを
同−集積回路上に冗長度がどの程度残さnているかを調
べるための回路を設けることにより、冗長回路をチェッ
クし、冗長度を調べらnるようにし、チップの信頼度を
把握で造るようにした。tた。冗長度t−調べるための
回路は。
In the present invention, conventionally, a redundant circuit is provided inside an integrated circuit.
By installing a circuit to check how much redundancy remains on the same integrated circuit, it is possible to check the redundancy and investigate the redundancy. The reliability of the chip was determined based on the reliability of the chip. It was. The circuit for checking redundancy t is:

簡単なデコーダとゲート回路で構成することができる。It can be configured with a simple decoder and gate circuit.

第2図、第3図に本発明の実施例を示す。Embodiments of the present invention are shown in FIGS. 2 and 3.

第2図は、信号処理回路(al sag sag)*(
blt  。
Figure 2 shows the signal processing circuit (al sag sag)*(
blt.

bll)m)”’多数決回路A、 、A、 、A、・・
・、およびデコーダBから成り立っており、cnらの回
路は同一のシリコンチップ上に構成さjしている。(a
l*aHtlkB)t(b、vJeb@)・・・の信号
処理回路は各々8EL1(i=1〜3)がHレベルの時
正常な動作をするものとし、iた8EL、がLレベルの
時は。
bll)m)"'Majority circuit A, ,A, ,A,...
. . , and decoder B, and the circuits of cn et al. are constructed on the same silicon chip. (a
It is assumed that the signal processing circuits l*aHtlkB)t(b,vJeb@)... each operate normally when 8EL1 (i=1 to 3) are at H level, and when i and 8EL are at L level. teeth.

各々の出力はHレベル又はLレベルに固定さnる。Each output is fixed at H level or L level.

また、CKがHレベルになると、8EL1はすべてHレ
ベルとなり、通常の動作を行ない、OKがLレベルの時
、ADH、AD2に入力さnた2進化信号により、10
進化信号に変換さnた5ELiのいずnか1つが選択さ
n、今、8)、Ll  が選択さn九時は、信号の流r
tはAI −a 1 →A 2−e l) 。
Also, when CK goes to H level, all 8EL1 goes to H level and performs normal operation, and when OK goes to L level, 10
If any one of 5ELi is selected n, now 8), and Ll is selected n9, the signal flow r is converted into an evolutionary signal.
t is AI-a 1 →A 2-e l).

A3となり% (al 警b11・・・)の回路チェッ
クが行なえる。
It becomes A3 and a circuit check of % (al warning b11...) can be performed.

餓3図の例は、各信号処理回路を単独に選択できるセレ
クタを同一シリコンチップ上に設け、各信号処理回路単
独のチェックを可能にしたものである。
In the example shown in Figure 3, a selector that can select each signal processing circuit independently is provided on the same silicon chip, making it possible to check each signal processing circuit alone.

第3図は、各々の信号処理ブロック(atb#・・・)
に単独に第2図で用いたセレクタを設け(B1゜B2.
・・・)こnらセレクタを選択するセレクタCを設けた
が、信号処理回路、多数決回路と共に同一シリコンチッ
プ上に構成されたものである。セレクタCからのセレク
ト信号線は、信号処理回路のブロック数が必要になり、
こnらの信号は、AL)1−Al)iに入力さnた2進
化信号tデコードして、10進にさnたも(D(81〜
1i)t−使用する。さらに5l−8iの信号線は、B
l−、Biなるセレクタのスレクト信号となり、各信号
処理ブロック(aMsebMs=−・)?選択する。マ
タ。
Figure 3 shows each signal processing block (atb#...)
The selector used in FIG. 2 is provided independently at (B1°B2.
(...) A selector C for selecting a selector is provided, but it is constructed on the same silicon chip along with a signal processing circuit and a majority decision circuit. The select signal line from selector C requires the number of blocks of the signal processing circuit,
These signals are input to AL)1-Al)i and then decoded into a binary coded signal t and converted into decimal (D(81~
1i) t-use. Furthermore, the signal line of 5l-8i is B
It becomes the select signal of the selector l-, Bi, and each signal processing block (aMsebMs=-・)? select. Mata.

各信号処理ブロックの内での回路の選択は、第2図に示
したと同様な信号ADDI*ADD2 GK により行
う、第3v!Aの場合も、第2図と同様にCK端子をH
レベルにすることにより、チップは正常の動作状態にな
る。
The selection of the circuit within each signal processing block is performed by the signal ADDI*ADD2 GK similar to that shown in FIG. In the case of A, the CK terminal is set to H as in Figure 2.
level, the chip will be in a normal operating state.

第4図に信号処理ブロックの構成の例を示す。FIG. 4 shows an example of the configuration of the signal processing block.

#!4図でs aHe au * allが同一の構造
をもつ信号処理回路であり、各々8E−L i (i=
1〜3)がLレベルの時正常の動作を行ない、Hレベル
の時、その出力はハイインピーダンス状態となり。
#! In Figure 4, s aHe au * all are signal processing circuits with the same structure, and each 8E-L i (i=
1 to 3) operate normally when they are at L level, and when they are at H level, their outputs are in a high impedance state.

この時*  Ii  (t”=t〜3)に入力さnた信
号は。
At this time, the signal input to *Ii (t''=t~3) is.

Gi(1−1〜3)のトライステート出力を持つゲ−)
1−通して0i(1−1〜3)に出力さnる。
A game with a tri-state output of Gi (1-1 to 3)
1- and output to 0i (1-1 to 3).

また、第4図において11.I、 、I、の入力信号!
Iは、複数本であっても前述と同様の動作を行なうこと
ができる。
Also, in FIG. 4, 11. Input signal of I, ,I,!
Even if there are a plurality of Is, the same operation as described above can be performed.

以上述べた第3図、第4図又はg2図の回路構成とする
ことにより任意の信号処理回路を外部から単独に選択す
ることができ、任意の部分の回路チェックができること
になる。
By adopting the circuit configuration as shown in FIG. 3, FIG. 4, or FIG.

本発明は1以上述べた簡単なセレクト回路、デコーダ(
ロ)路t−集積回路内部に設けることにより。
The present invention is based on one or more of the simple select circuits and decoders (
b) By providing the circuit inside the integrated circuit.

外部から冗長回路の冗長度を判定でき、築積回路の信頼
度を把握できる効果かめる。
The degree of redundancy of redundant circuits can be determined from the outside, and the reliability of built-in circuits can be determined.

【図面の簡単な説明】[Brief explanation of drawings]

第1(2)は3対lの多数決回路を示す図hMz図は1
本発明の実施例のl)を示す図、第3図は本発明の一実
施例を示す図、第4図は第3図のa又はbを詳しく説明
する図である。 lユII、、I、・・・・・・前段からの同一信号s 
 ”11 ’a□j t alll・旧・・同一の信号
処理回路。
The first (2) is a diagram showing a 3-to-l majority circuit.hMz diagram is 1
FIG. 3 is a diagram showing one embodiment of the present invention, and FIG. 4 is a diagram explaining in detail a or b of FIG. 3. lUII,,I,...Identical signal s from the previous stage
``11 'a□j t all・Old...Same signal processing circuit.

Claims (3)

【特許請求の範囲】[Claims] (1)  1個の半導体基板に、所要の回路の構成素子
の数に冗長度を持たせて該所要の回路を必要最小限の素
子数よ°り多い菓子で構成する集積回路において、冗長
度がどの程度残さnているかを外部から判定できる手段
を設けたことを特徴としfc集積回路。
(1) In an integrated circuit in which redundancy is provided to the number of constituent elements of a required circuit on one semiconductor substrate, and the required circuit is configured with more elements than the minimum number of elements, the redundancy An FC integrated circuit characterized in that it is provided with a means for determining from the outside how much n remains.
(2)上記外部端子を選択することにより冗長回路の信
頼度を+U足できる回路を該半導体基板上に構成したこ
とを特徴とする特許請求の範囲(1)項延記載の集積回
路。
(2) The integrated circuit as recited in claim (1), characterized in that a circuit that can increase the reliability of the redundant circuit by +U by selecting the external terminal is constructed on the semiconductor substrate.
(3)2進−10進デコーダを該半導体基板上に構成し
、冗長回路の信頼度t−!!sJ定できる機能を有する
ことを特徴とする特許請求の範囲(2)に記載の集積回
路。
(3) A binary-decimal decoder is constructed on the semiconductor substrate, and the reliability of the redundant circuit is t-! ! The integrated circuit according to claim (2), characterized in that it has a function of determining sJ.
JP56137431A 1981-09-01 1981-09-01 Integrated circuit Granted JPS5839050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56137431A JPS5839050A (en) 1981-09-01 1981-09-01 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56137431A JPS5839050A (en) 1981-09-01 1981-09-01 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS5839050A true JPS5839050A (en) 1983-03-07
JPS6211739B2 JPS6211739B2 (en) 1987-03-14

Family

ID=15198459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56137431A Granted JPS5839050A (en) 1981-09-01 1981-09-01 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5839050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150439A (en) * 1985-12-24 1987-07-04 Nec Corp High reliable computer system
US4994976A (en) * 1988-02-17 1991-02-19 Mitsubishi Jukogyo Kabushiki Kaisha Film thickness controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830338A (en) * 1971-08-17 1973-04-21
JPS5276842A (en) * 1975-12-22 1977-06-28 Nippon Telegr & Teleph Corp <Ntt> Memory elements
JPS5570998A (en) * 1978-11-20 1980-05-28 Nippon Telegr & Teleph Corp <Ntt> Block switching system for memory unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830338A (en) * 1971-08-17 1973-04-21
JPS5276842A (en) * 1975-12-22 1977-06-28 Nippon Telegr & Teleph Corp <Ntt> Memory elements
JPS5570998A (en) * 1978-11-20 1980-05-28 Nippon Telegr & Teleph Corp <Ntt> Block switching system for memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150439A (en) * 1985-12-24 1987-07-04 Nec Corp High reliable computer system
US4994976A (en) * 1988-02-17 1991-02-19 Mitsubishi Jukogyo Kabushiki Kaisha Film thickness controller

Also Published As

Publication number Publication date
JPS6211739B2 (en) 1987-03-14

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