JPS5837926A - Manufacture of substrate for semiconductor element - Google Patents
Manufacture of substrate for semiconductor elementInfo
- Publication number
- JPS5837926A JPS5837926A JP13676581A JP13676581A JPS5837926A JP S5837926 A JPS5837926 A JP S5837926A JP 13676581 A JP13676581 A JP 13676581A JP 13676581 A JP13676581 A JP 13676581A JP S5837926 A JPS5837926 A JP S5837926A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- quartz
- oxygen
- substrates
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 230000007547 defect Effects 0.000 abstract description 16
- 239000010453 quartz Substances 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000007789 gas Substances 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000007800 oxidant agent Substances 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 241001237726 Yoma Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
この発明状半導体素子用基板の製造方法にかかり、特に
シリコン半導体素子の製造に用いるシリコン基板の不純
物による欠陥を除去する製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a substrate for a semiconductor device, and particularly relates to a method of manufacturing a silicon substrate used for manufacturing a silicon semiconductor device to remove defects caused by impurities.
一般に引上法（チョクツルス中法）によって育成された
シリコン単結晶体は、この引上けに用いられるシリコン
多結晶体を溶融するるつぼが石英であるため、通常１０
１７〜ＩＱＩＩ原子／ｃｄ程度のｌＩ累不純物が含まれ
ている。そこで、このようなシリコン単結晶体より切夕
出して作製されるシリコン基板を比較的高温、例えば１
０５０℃で熱処理を施すと酸素の析出によると考えられ
ている析出−およびそれによって派生する転位ループや
積層欠陥を生じ、素子のａｔ造およびその電気的特性上
悪影響をおよぼすことが知られている。ところが最近、
酸素不純物を多く含んだシリコン基板を熱処理すること
によりシリコン基板の表面近傍、すなわち数十趨の深さ
までにある余剰酸素不純物をシリコン基板外へアクトデ
ィ７ユージヨンによｐ＃去し、この基板の厚さの中央部
ＯみＫｌｌ素不純智の析出物ある一社それに起因する欠
陥を作り、この欠陥により素子製造中に発生して種々の
欠陥のもとＫなる不純物を吸収させるメツタ効果（Ｌａ
ｔｒｌｎｓｉ・Ｇ＠ｔｔ＠ｒ１ｍｇ ）を利用すること
が試みられている。これは不活性の雰囲気で熱処理を施
し酸素不純物を基板外ヘアクトデイ７：Ｌ−ズさせる（
のであるが、処理温度を選んでも効果が乏しく、基板の
表面近傍領域に余剰な酸素不純物が残存しており、これ
が素子製造中に発生する欠陥の直接の原因になっている
ので実用上の効果は認められない。In general, silicon single crystals grown by the pulling method (Chocturus medium method) usually have a
It contains lI cumulative impurities of about 17 to IQII atoms/cd. Therefore, a silicon substrate made by cutting out a silicon single crystal like this is heated to a relatively high temperature, for example, 1.
It is known that heat treatment at 050°C causes precipitation, which is thought to be due to oxygen precipitation, and the resulting dislocation loops and stacking faults, which adversely affect the element structure and its electrical properties. . However, recently,
By heat-treating a silicon substrate containing a large amount of oxygen impurities, the excess oxygen impurities near the surface of the silicon substrate, that is, up to several tens of depths, are removed from the silicon substrate by an active process, and the thickness of this substrate is reduced. A precipitate of Kll element impurity in the central part of the sensor creates a defect caused by it, and this defect absorbs the impurity K, which occurs during device manufacturing and causes various defects.
Attempts have been made to utilize trlnsi・G@tt@r1mg). This is heat-treated in an inert atmosphere to remove oxygen impurities from the substrate.
However, no matter what treatment temperature is selected, the effect is poor, and excess oxygen impurities remain in the region near the surface of the substrate, which is a direct cause of defects that occur during device manufacturing, so it is not practical. It is not allowed.
この発明は上記従来の方法の欠点を改良するもので、牛
導体素子を形成するにあたり、２ｘ１０ｔａ原子／ａｘ
”以下のａｌｌ素を含有させたシリコン基板を用意し、
これに非酸化性の減圧雰囲気中で１０００ ”〜１２０
０℃の加熱を施すことを特徴とする。This invention improves the drawbacks of the conventional method described above, and in forming a cow conductor element, 2x10ta atoms/ax
``Prepare a silicon substrate containing the following all elements,
1000" to 120" in a non-oxidizing reduced pressure atmosphere.
It is characterized by heating at 0°C.
以下にこの発明を１実施例につき詳細に説明する。シリ
コン基板の製造には例えば第１図に示すような引上装置
による。図において、（１）は多結晶シリコンを入れ溶
融する石英るつほで緩速回転される。（２）は多結晶シ
リコンを溶融する丸めの加熱体、（３）は引上軸で上下
軸と石英るり埋と逆回シの緩速回転運動とをする、また
、（４）は多結晶シリコンの溶融体の表面に接するよう
に置かれ中央に単結晶シリコンの引上げを可能にする孔
を有する石英板である。前記るつは（１）および石英板
（４）の石英は高温で単結晶シリコン体の）中に２Ｘ１
０１ｎ原子／♂以下の酸素を供給させる。引上げによっ
て形成された棒状の単結晶シリコン体を切断して作った
シリコンウェハ（以降ウェハと略称） （６’） 、
（６’）・・・を第２図に示す加熱装置の気密耐熱容器
（７）内に互いに平行かつ離間させて配置し、この容器
をとりまくように配置し九加熱体（８）にて加熱する。The invention will be explained in detail below with reference to one embodiment. For manufacturing silicon substrates, a lifting device as shown in FIG. 1 is used, for example. In the figure, (1) is rotated at a slow speed in a quartz crucible containing polycrystalline silicon and melting it. (2) is a rounded heating element that melts polycrystalline silicon, (3) is a pulling shaft that performs slow rotational motion in the vertical axis, quartz burying and reverse rotation, and (4) is a polycrystalline silicon It is a quartz plate that is placed in contact with the surface of a silicon melt and has a hole in the center that allows single-crystal silicon to be pulled up. The quartz of the melt (1) and the quartz plate (4) are 2X1 in a single crystal silicon body at high temperature.
Oxygen of 01n atoms/male or less is supplied. Silicon wafer (hereinafter abbreviated as wafer) made by cutting a rod-shaped single crystal silicon body formed by pulling (6'),
(6')... are arranged in parallel and apart from each other in an airtight heat-resistant container (7) of the heating device shown in Fig. 2, arranged so as to surround this container, and heated with nine heating elements (8). do.
容器に紘排気口（９ａ）と、たとえばアルゴンのような
不活性気体を導入するためのガス導入口（９ｋ）が設け
られている。処理条件は温度間８１０００’〜１２００
℃にで、 １Ｇ””〜１Ｇ−マトールまた社非酸化Ｉｌ
！囲気の１〜２Ｇ）−ルでよい０これらの処理条件は上
記単結晶シリコン中に含有される酸素の含有量と組み合
わせて嬉３図ないしｊ１８図にウェハの左半部に本発明
による場合、右半部に従来の処理による場合を夫々置化
後の欠陥分布を対比させて示したもので、表面状態を写
真にもとづいて描い友もので。The container is provided with a gas outlet (9a) and a gas inlet (9k) for introducing an inert gas such as argon. Processing conditions are temperature range 81000'~1200'
At ℃, 1G"" ~ 1G-matol or non-oxidized Il
! These processing conditions, in combination with the oxygen content contained in the single-crystal silicon, result in the formation of the left half of the wafer according to the present invention, as shown in Figures 3 to 18. The right half shows a comparison of the defect distribution after conventional treatment and after treatment, and the surface condition is illustrated based on the photograph.
ある・■中打点を施し先部分は表面欠陥のある曇り（ｃ
ｌ・ｗ＋ｄｙ ）状態を示している。また、クエへの酸
素含有状態、加熱処理の条件等によって発生する表面欠
陥Ｏ状態との関係を上記与真にもとづく図面と対応させ
て次Ｏ表に示す。加熱処理条件は、この発明の１実施例
の（４）ではウェハを清浄化したのち、４ Ｘ １０”
−”）−ル、１０５０℃にて１８時間加熱を施し再び清
浄化し、スチーム中にて１１００℃、９０分間加熱し酸
化させるものであり、別の１実施例の（Ａ′）ではウエ
ノ・を清浄化したのち、Ｎｔ雰囲気中、１０５０℃にて
１８時間加熱を施し再び清浄化しスチーム中にて１１０
０℃、 ９０分間加熱し酸化させるものである。これに
対しくＢ）は、従来の加熱処理であって、ウエノ・を清
浄化したのちスチーム中にて１１００℃、９０分間加熱
し酸化させるものである。Yes/■ Medium dots are applied, and the tip part is cloudy with surface defects (c
l・w+dy) state. In addition, the relationship between the surface defect O state caused by the oxygen content of the quench, heat treatment conditions, etc. is shown in the following table in correspondence with the drawings based on the above-mentioned Yoma. In (4) of one embodiment of the present invention, the heat treatment conditions are 4 x 10" after cleaning the wafer.
In another example (A'), Ueno was heated at 1050°C for 18 hours, cleaned again, and heated in steam at 1100°C for 90 minutes to oxidize it. After cleaning, heating at 1050°C for 18 hours in Nt atmosphere, cleaning again, and heating at 110°C in steam.
It is oxidized by heating at 0°C for 90 minutes. On the other hand, B) is a conventional heat treatment in which Ueno® is cleaned and then heated in steam at 1100° C. for 90 minutes to oxidize it.
なお、ウェハの試料の別（ａ） 、 （ｂ）ｅ （ｅ）
は表にも示したように（ａ）は酸素濃度０．７ Ｘ １
０”原子／ｃｌＩｓ１炭素濃度１．４Ｘ１０’テ原子／
ｉ、（ｂ）は酸素濃度０．９Ｘ１０”原子／ｃｍ”、炭
素洟度１．Ｉ Ｘ １０”原子／ ｅｘ”、（ｃ）は酸
素浸度１．４×１０′８原子／α３、炭素濃度６Ｘ１０
”原子／♂に夫々調装されたものである。In addition, the types of wafer samples (a), (b)e (e)
As shown in the table, (a) has an oxygen concentration of 0.7 x 1
0" atom/clIs1 carbon concentration 1.4X10'te atom/
i, (b) is an oxygen concentration of 0.9 x 10"atoms/cm" and a carbon purity of 1. I
``They are each arranged into an atom/♂.
（以十余白）
次の第９因には熱地理後の酸素不純物による微小欠陥分
布を示し、横軸はウエノ１端部からの距離で３０１１１
がウエノ・の中心である。また、（＆）、（ｂ）、（Ｃ
）は前記のウェハ中の酸素の濃度に基づく分類によって
いる。第１Ｏ図および第１１図にはウェハ（ｂ）の断面
における微小欠陥分布を示し、第１Ｏ図は加熱処理を減
圧で施し酸化表面に欠陥のない領域、第１１図は酸化表
面に欠陥のある領域を断面写真に基づいて描い九もので
ある。必中ＸＹ＃′ｉ基板の表面であり、第１０図に示
すものはアウトディフュージョンによって槍く表層の酸
素が除かれ、これより若干深い部分ではウェハの厚さ方
向の中心部の＃ＲＸによるＩＱ効果によりｘ／ ｙ／面
まで無欠陥となっているのが明瞭に認められる。(10 blank spaces) The following 9th factor shows the micro defect distribution due to oxygen impurities after thermogeography, and the horizontal axis is the distance from the end of Ueno 1, which is 30111.
is the center of Ueno. Also, (&), (b), (C
) is classified based on the concentration of oxygen in the wafer. Figures 1O and 11 show the distribution of minute defects in the cross section of the wafer (b). Figure 1O shows the area where the oxidized surface has no defects after heat treatment under reduced pressure, and Figure 11 shows the area where the oxidized surface has defects. The area is drawn based on cross-sectional photographs. This is the surface of the XY #'i substrate, and what is shown in Figure 10 is where oxygen on the surface layer is removed by outdiffusion, and in a slightly deeper part, there is an IQ effect due to #RX in the center of the wafer thickness. It can be clearly seen that there are no defects up to the x/y/plane.
上に述べたようにこの発明によれば再現性の良い無欠陥
領域の制御が達成できるので、半導体素子の電気的特性
が良好に得られる顕著な利点がある。また、この発明は
実施が簡単である上に用いる装置もはは従来のものでよ
いなどの利点もある。As described above, according to the present invention, it is possible to control the defect-free area with good reproducibility, so there is a significant advantage that good electrical characteristics of the semiconductor element can be obtained. Further, the present invention has the advantage that it is easy to implement and that conventional equipment may be used.
第１色はｌ実施例に用いられる単結晶引上育成装置の断
面図、第２図は１実施例に用いられる加熱装置の断面図
、第３図ないし第８−はいずれも夫々が１実施例の効果
を説明するためのウェア・の正面図、第９図はウェハの
微小欠陥分布を示す線図、第１０図および第１１図はい
ずれもウェハの表層部の微小欠陥を示す断面図である。
１ 石英るつぼ
４ 石英板
５ 単結晶シリコン
６．６′・・ シリコン基板
９ａ 排気口
９ｂ ガス導入口
代理人 弁理士 井 上 −男The first color is a cross-sectional view of the single crystal pulling growth apparatus used in Example 1, FIG. Figure 9 is a front view of the wafer to explain the effect of the example, Figure 9 is a line diagram showing the distribution of minute defects on the wafer, and Figures 10 and 11 are cross-sectional views showing minute defects on the surface layer of the wafer. be. 1 Quartz crucible 4 Quartz plate 5 Single crystal silicon 6.6'... Silicon substrate 9a Exhaust port 9b Gas inlet agent Patent attorney Inoue - Male
Claims (1)
以下の酸素を含有させたシリコン基板を用意し、これに
非酸化性の減圧雰囲気中にて１０００ ’〜１２００℃
の加熱を施すことを特徴とする半導体素子用基板の製造
方法。#)9,2X10” atoms/- to form a semiconductor device
A silicon substrate containing the following oxygen is prepared, and heated to 1000' to 1200°C in a non-oxidizing reduced pressure atmosphere.
1. A method of manufacturing a substrate for a semiconductor device, comprising heating the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13676581A JPS5837926A (en) | 1981-08-31 | 1981-08-31 | Manufacture of substrate for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13676581A JPS5837926A (en) | 1981-08-31 | 1981-08-31 | Manufacture of substrate for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5837926A true JPS5837926A (en) | 1983-03-05 |
Family
ID=15182979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13676581A Pending JPS5837926A (en) | 1981-08-31 | 1981-08-31 | Manufacture of substrate for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837926A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094722A (en) * | 1983-08-16 | 1985-05-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Silicon wafer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068052A (en) * | 1973-10-17 | 1975-06-07 | ||
| JPS5680139A (en) * | 1979-12-05 | 1981-07-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
-
1981
- 1981-08-31 JP JP13676581A patent/JPS5837926A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068052A (en) * | 1973-10-17 | 1975-06-07 | ||
| JPS5680139A (en) * | 1979-12-05 | 1981-07-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094722A (en) * | 1983-08-16 | 1985-05-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Silicon wafer |
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