JPS5827671B2 - Charge pumping memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge pumping memory cell having an MO8FET structure that injects charges into a floating substrate and utilizes the substrate bias effect thereof.

As shown in FIG. 1, a conventional charge pumping type memory cell has an SO8 structure in which an island-shaped silicon layer is formed on a sapphire substrate and a MOS FET is formed in the silicon layer.

In this figure, 10 is a sapphire substrate, 12 is a P-type silicon layer (floating substrate) formed in the form of an island on the substrate, 14 is a gate oxide film formed on the silicon layer, and 16 is a polycrystalline layer formed on top of it. Silicon gate electrodes 18 and 20 are N+ type source and drain regions formed on the floating silicon substrate 12, and these 12 to 20 constitute an N-channel silicon gate MOS FET.

In this device, a positive voltage is applied to the gate 16 to form an N inversion layer, that is, a channel, in the lower substrate portion of the gate oxide film 14, and a voltage is applied between the source and drains 18 and 20 to cause current to flow, causing a sudden increase in the voltage. When the positive voltage is reduced to zero, the channel naturally disappears and the current is cut off, but at this time the charges, in this case electrons, flowing through the channel are injected into the substrate 12.

Electrons injected into the substrate 12 due to this charge pump phenomenon recombine with holes and disappear;
The number of inner holes decreases, the P-type impurity concentration in the substrate 12 decreases (in this device, a relatively high substrate concentration of 1016 atoms/d or more is used), and the depletion layer at the source and drain 18°20 junctions expands. However, the potential of the substrate 12 decreases to the negative side.

When the substrate becomes negative, the threshold voltage vt of this MOSFET
h is driven to the enhancement side.

Therefore, when we look at the current that flows when a voltage is applied between the source and drain, we see that when charge pumping is performed (assuming that "1" is written), and when it is not performed (assuming that "0" is written, ), the drain current becomes smaller, and it is possible to determine whether the memory content is "1" or "0" based on the magnitude of this current.

Use avalanche breakdown to erase memory contents.

That is, reading is performed by applying approximately +5V to the drain 20 (writing is approximately +9V), but for erasing, this is increased to approximately +16V to cause avalanche breakdown near the drain.

As a result, electron-hole pairs are generated, the electrons are absorbed by the drain at positive potential, and the holes are injected into the substrate 12, returning the negatively charged substrate 12 to zero potential.

When excessive holes are injected into the substrate, the substrate becomes at a positive potential, which forward biases the PN junction formed between the substrate and the source, and the holes flow out to the source at zero potential.

Therefore, there is no excessive hole injection into the substrate.

The details of this charge pumping memory element are disclosed in Japanese Patent Laid-Open No. 54
-5635, etc.

By the way, as shown in FIG. 2, the minimum value of the planar size of the charge pumping memory of the SO8-MO5FET structure mentioned above is that the width of the gate part G1 source S1 drain D is the minimum line width F, and the length is also If it is IF, it is necessary to set the minimum line width F between adjacent elements, so including this, the required area becomes 4FX2F=8F2.

Needless to say, it is desired that the memory cell be as small as possible in order to realize a large capacity memory.

Furthermore, since the SO8 structure has many crystal defects and a large leakage current, the injected charges are quickly dissipated, and therefore refreshing must be repeated at short intervals.

The present invention aims to improve these points by eliminating the SO8 structure, reducing leakage current by using a bulk silicon semiconductor substrate, and realizing a minimum cell area of 4F2 by using a buried source type charger. The present invention provides a pumping type memory cell.

Hereinafter, the present invention will be explained in detail along with the manufacturing process shown in FIG.

In FIG. 3a, 30 is an N-type silicon semiconductor substrate, and 32 is an N-type layer formed by epitaxial growth on the substrate or by diffusion of impurities (this may be a P-type layer, but in this case, of course, the source described later is used). , the conductivity types of the drain, etc. are all reversed), and 34 is a field oxide film for isolation.

A gate oxide film is formed on the substrate by thermal oxidation, a polycrystalline silicon layer is deposited by the CVD method, and this is patterned to form a gate oxide film 40 having a gate electrode 38° as shown in FIG.

As shown in the figure, the gate electrode 38 and gate oxide film 40 are
The field oxide film is biased to one side of the active region defined around the periphery, and the other side serves as a window W to expose the substrate.

Next, P-type impurities are first diffused deeply through this window W, and then N-type impurities are diffused shallowly to form a P-type layer (floating substrate) 42 and an N+-type layer (drain region) as shown in FIG. Make 44.

Thereafter, an insulating film 46 such as silicon dioxide is formed around the gate electrode 38, and then aluminum is deposited and patterned to form a bit line 48.

The word line is formed by an extension of the gate electrode 38.

The layer 32 serving as the source region is in conductive contact with the substrate 30, and this substrate 30 serves as the common source wiring.

If we consider this charge pumping memory cell as a planar pattern as shown in Figure 2, the minimum width may be 2F, and the length remains unchanged and is also 2F, so the cell area is 2FX.
2 F=4 F2.

In addition, the channel is formed by a P-type layer 42 facing the gate electrode 46.
Because it can be made into sections, it can be made extremely short.

In addition, the semiconductor layer used is of good quality because it is made by introducing impurities of a desired concentration or conductivity type into a silicon epitaxial growth layer stacked on a silicon substrate or into the silicon substrate itself, and it has a high leakage current like an SO8 element. There are no drawbacks as a dog.

The operation is similar to that shown in FIG.
A channel is formed in 2, a current is passed through a path between the drain region 44, the channel, and the source region (layer 32), and this is abruptly interrupted to inject charges into 42.

Since this layer 42 is completely insulated from its surroundings by a PN junction or the like formed between layers 44 and 32, this charge injection changes the potential and produces a bank gate effect.

For reading, it is sufficient to detect the difference in drain current due to this back gate effect.

Note that the P region 42 is small as shown in the figure, and therefore the amount of charge injected is small, but if the potential of the layer 42 changes, a bank gate effect will appear, so unlike a one-transistor, one-capacitor cell, etc., the amount of charge will affect the operation. There's nothing to do.

As described above, according to the present invention, the minimum area per cell of a charge pumping type memory can be reduced to 4F2, which is extremely advantageous in achieving high integration of large capacity storage devices. Since it has a silicon bulk structure rather than an SO8 structure, it has advantages such as low leakage current.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing an example of a charge pumping memory with a 508-MO8FET structure, Figure 2 is an explanatory diagram of the area occupied by the same charge pumping memory, and Figures 3a and 3c are cross-sectional views showing the manufacturing process of the device of the present invention. In the figure, 30 is an N-type silicon semiconductor substrate (common source region), 32 is an N-type silicon layer, 38 is a polycrystalline silicon gate, 40 is a gate oxide film, and 42 is a P-type layer (floating substrate region). , 44 is an N+ type layer (drain region).

Claims (1)

[Claims] 1. A gate insulating film is left on a semiconductor layer of one conductivity type whose circumferential side is insulated, a gate insulating film is attached, and a gate electrode connected to a word line is attached on top of the gate insulating film, and an impurity is diffused into the semiconductor layer through the window. A channel is formed extending from the window side to a drain region of the same conductivity type and connected to the bit line, below the drain region, and below the gate electrode portion on the drain region side, and charge is injected into the channel. A charge pumping type memory cell characterized in that floating substrate regions of opposite conductivity type are sequentially formed to provide a bank gate effect.