JPS58207653A - Master wafer for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive to improve the economic property by enabling the arbitrary selection of basic blocks included in a master chip, by making variable the scribing position of the master wafer before forming the master chip. CONSTITUTION:A hundred basic blocks 2 are built in on a piece of semiconductor wafer 1, which basic blocks 2 are composed by arranging and integrate a plurality of several kinds of circuit elements consisting of a plurality of elements. The chip A is scribed at the position of a real lines 3 and constituted of four basic blocks 2, and the chip B is scribed at the position of dot lines 4 and constituted of twenty five basic blocks 2. In other words, twenty five master chips can be obtained from a piece of wafer 1 in the case of the chip A, while four from the same wafer in the case of the chip B. Therefore, when the circuit scale of the basic block 2 is 200 gates, the chip A becomes 800 gates, and the chip B 5K gates; and the increase and decrease of the circuit scale is enabled by the unit of 200 gates only by changing the scribing position of the wafer 1 by means of the same wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to mask slicing semiconductor integrated circuit technology, and more specifically to a mask for semiconductor integrated circuits that improves the wafer structure before forming mask chips. Regarding wafers.

[Technical background of the invention and its problems]

The mask slicing method is a process in which a large number of basic cells (element circuits) consisting of multiple elements are fabricated on a semiconductor wafer in advance.
It attempts to obtain a desired circuit operation by changing contact holes, metal wiring, etc., and its feature is that it can relatively easily respond to requests for circuits with new functions. That is, since the semiconductor chip created through the steps up to the step of forming the metal wiring is substantially common to all functional circuits, it is possible to shorten the development period and reduce the manufacturing cost. Moreover, it has attracted particular attention in recent years and has led to the release of many products because it enables high-mix, low-volume production, which has been considered difficult in the past.

By the way, most of the mask slicing method products that have been reported so far are of the dart array type, and many types of mask chips such as 1.5 dart, 3 dart, 6 dart, etc. are prepared, and the necessary Masks and
A common method is to use chips selectively. For this reason,
For example, if the required circuit scale is 4-dart, it would be best to use a 6-dart mask chip. Therefore, the second gate is left unused, which increases the chip size relative to the circuit scale, which is uneconomical.

'Also,] K Da-to, 2 K
Preparing in advance a wide variety of mask chips such as 3K ri'-to, 4K ri'-to, 4-dirt, etc. is also not economically desirable.

[Purpose of the invention]

An object of the present invention is to enable the selection of the minimum number of basic blocks (consisting of a plurality of element circuits arranged) included in a mask chip according to the desired circuit scale, thereby improving economic efficiency. It is an object of the present invention to provide a mask wafer for semiconductor integrated circuits that can be used to measure .

[Summary of the invention]

The gist of the present invention is to make it possible to arbitrarily select the basic blocks included in the mask chip by varying the scribe position of the mask wafer before forming the mask chip.

That is, in a mask wafer for a semiconductor integrated circuit, the present invention arranges a plurality of basic blocks formed by arranging and integrating several types of element circuits on a semiconductor wafer, and scribing between each block. A wiring area is formed and the scribe position can be varied depending on the required circuit scale.

〔Effect of the invention〕

According to the present invention, the number of basic blocks included in one mask chip can be arbitrarily selected by varying the scribe order 1k, so that the basic blocks included in the mask chip can be adjusted to a desired circuit scale. Depending on the situation, the amount can be reduced to the necessary minimum and economical efficiency can be improved.

[Embodiments of the invention]

FIG. 1 is a plan view showing the basic structure of a mask wafer for a semiconductor integrated circuit according to an embodiment of the present invention. 1 semiconductor wae/100 pieces on 1 (10 rows x 1 () column)
Basic block 2 is built in. These basic blocks 2 are formed by arranging and integrating several types of circuit elements each consisting of a plurality of elements. Chip A is scribed at the position indicated by the solid line 3 in the figure and is constructed using four basic blocks 2, and chip B is scribed at the position indicated by the broken line 4 in the figure and constructed using 25 basic blocks 2.

Sunawa'chi, in case of chip A, 2 from H1 wavepano
In the case of chip 7'B, four mask chips can be obtained from one wafer. Therefore, if the circuit scale of basic block 2 is 2 (10 darts), chip A
is 800 darts, and chip B is 5 to 9 darts. Using the same wafer 1, only changing the scribe position,
The circuit scale can be increased or decreased in units of 200 dyads.

FIG. 2 shows an enlarged plan view of the chip A in an example where four basic blocks 2 are used to construct one mask chip. The basic block 2 is divided into an element circuit array part) 1 and a peripheral circuit part 12.
A wiring region 13 between the blocks is formed in a portion where four basic blocks 2 are adjacent to each other (shaded portion in the figure). The non-adjacent portions of the peripheral circuit portion 12 are still used as the entire peripheral circuit portion, and the gendering pads 14 are formed at the same time as the metal wiring is formed.

Thus, according to this embodiment, mask chips having, for example, 4 or 25 basic blocks 2 can be easily obtained from one type of mask wafer by changing the scribe position. Therefore, depending on the circuit size! - It is possible to manufacture a wide variety of LSIs with desired functions by performing tuning.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the bonding/? Wood does not necessarily need to be placed around the chip, but can be placed at any position. Furthermore, the present invention is not limited to dart arrays, and can be applied to various mask-sliced LSIs.

Furthermore, it is a matter of literature that the scribe position is not limited to the position shown in the embodiments, but may be determined as appropriate depending on the required circuit integrity.

Figure 1 is a plan view showing the basic structure of a mask wafer for semiconductor integrated circuits according to an embodiment of the present invention, and Figure 2 shows the main part of the above embodiment. FIG. 2 is an enlarged plan view of a master chip consisting of four basic blocks obtained by scribing an example wafer.

DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Basic block, node... Element circuit arrangement part, 12... Peripheral circuit part, 13
... Wiring area, 14... Bonding -re y
Do.

Claims (1)

[Claims] A plurality of basic blocks formed by arranging a plurality of element circuits each consisting of a plurality of elements are arranged on a semiconductor wafer, and a wiring area is formed between each block, and the semiconductor wafer is selected in the wiring area. scribed,
A mask wafer for semiconductor integrated circuits, characterized in that the scribe position can be varied according to the required circuit scale.