JPS58202573A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58202573A JPS58202573A JP57086012A JP8601282A JPS58202573A JP S58202573 A JPS58202573 A JP S58202573A JP 57086012 A JP57086012 A JP 57086012A JP 8601282 A JP8601282 A JP 8601282A JP S58202573 A JPS58202573 A JP S58202573A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- electrode
- impurity diffusion
- input pad
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 48
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000005611 electricity Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体集積回路装置の構造に係り、特に半導体
集積回路装置の静電耐量を増す構造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor integrated circuit device, and more particularly to a structure that increases the electrostatic withstand capacity of a semiconductor integrated circuit device.
（ｂ） 技術の背景
ＭＯＳ ＬＳＩ等のＭＯ８型半導体集積回路（Ｉ Ｃ）
の入力端子は、通常ＭＯＢ）ランジスタのゲート電極に
接続されているが、咳ゲート電極は極めて絶縁抵抗の高
い酸化膜等によ如絶縁されているので、衣服、プラスチ
ック容器、その他ＬＳＩの保存、取扱い中に発生する静
電気によって高い電圧が加わ如易い。この場合ゲート電
極と半導体基板間に形成されているゲート酸化膜が数１
００（Ａ）程度の薄い膜であるために、数１０ （Ｖ）
程度の低い電圧で絶縁破壊を起しＭＯＳ）ランジスタの
機能が失われる。(b) Technology background MO8 type semiconductor integrated circuit (IC) such as MOS LSI
The input terminal of the MOB is usually connected to the gate electrode of the transistor, but since the gate electrode is insulated with an oxide film with extremely high insulation resistance, it should not be used for storage of clothes, plastic containers, or other LSIs. High voltage can easily be applied due to static electricity generated during handling. In this case, the gate oxide film formed between the gate electrode and the semiconductor substrate is
Since it is a thin film of about 00 (A), it is several tens (V)
Dielectric breakdown occurs at a very low voltage, and the function of the MOS transistor is lost.
そのためＭＯ８Ｌ８Ｉに於ては、静電気やその他の誤っ
て加えられる過電圧から特に容量の小さい入力ＭＯ８）
ランジスタを保護するために入力保護回路が配設される
。Therefore, in MO8L8I, the input MO8, which has a particularly small capacity, is protected against static electricity and other accidentally applied overvoltages.
An input protection circuit is provided to protect the transistor.
（ｃ） 従来技術と問題点
入力保護回路に必要な特性は、ＬＳＩの正常な動作範囲
に於ては電流を流さず、異常電圧に対してはゲートの破
壊電圧よシも充分低い電圧で電流を流して入力回路をク
ランプし、更にサージ電圧に対して速やかに応答するこ
とである。(c) Prior art and problems The characteristics necessary for an input protection circuit are that no current flows within the normal operating range of the LSI, and in the case of an abnormal voltage, the current flows at a voltage that is sufficiently low compared to the breakdown voltage of the gate. The purpose of this is to clamp the input circuit by applying current to the input circuit, and to quickly respond to surge voltage.
これらの条件を満たすものとして従来から用いられてい
る回路は、例えばｎチャネルＭＯ８に於ては第１図に示
すように、入力端子と入力ＭＯＳトランジスタＴＨのゲ
ート電極０間にｐｎ接合ダイオード（Ｄｉ）や直列抵抗
Ｒが挿入された構造を有してお多基板Ｓに対して負電圧
が入力端子に加わった時にはｐｎ接合ダイオード（Ｄｉ
）の順方向特性によってこれをクランプし、正電圧が加
わった時にはダイオードＤＩの回復可能なブレークダウ
ンによってこれをクランプし、更に直列抵抗の分圧効果
を利用してそのクランプ効果を更に向上せしめる機能を
有してなっていた。A conventionally used circuit that satisfies these conditions is, for example, in an n-channel MO8, as shown in FIG. 1, a pn junction diode (Di ) and a series resistor R are inserted, and when a negative voltage is applied to the input terminal of the multi-board S, a pn junction diode (Di
), and when a positive voltage is applied, it is clamped by the recoverable breakdown of the diode DI, and the clamping effect is further improved by using the voltage dividing effect of the series resistor. It had become.
第２図は上記従来の入力保護回路の構造を示したもので
、同図に於ける（イ）はその透視平面図、（ロ）はその
Ａ −Ａ’矢視断面図である。FIG. 2 shows the structure of the conventional input protection circuit, in which (a) is a perspective plan view thereof, and (b) is a sectional view taken along the line A-A'.
即ち従来の入力保護回路に於て、入力ＭＯ８）ランジス
タＴＲのゲー）を極Ｇは、例えばｐ型半導体基板１に形
成したｎ十型拡散領域２の一端部に、電極コンタクト窓
３ａおよび３ｃと上層配線りを介して接続され、入力端
子即ち入力パッド電極５は電極コンタクト窓３ｂを介し
てｎ十型拡散領域２の他端部に接続されてなっていた。That is, in the conventional input protection circuit, the input MO8) gate of the transistor TR is connected to the electrode contact windows 3a and 3c at one end of the n+ type diffusion region 2 formed in the p-type semiconductor substrate 1, for example. The input terminal or input pad electrode 5 was connected to the other end of the n+ type diffusion region 2 via the electrode contact window 3b.
なお第２図（イ）Ｋ於ては、絶縁膜を省略して図示して
あシ、又第２図（イ）に於て６及び７はｎ中型ドレイン
領域、第２図（ロ）に於て８はフィールド酸化膜、９は
シん珪酸ガラス（Ｐ Ｓ Ｇ）絶縁膜を示す。Note that in FIG. 2(a) K, the insulating film is omitted, and in FIG. 2(a), 6 and 7 are n medium-sized drain regions, and in FIG. 2(b), 8 is a field oxide film, and 9 is a shinsilicate glass (PSG) insulating film.
そして骸構造に於ては、ｎ十型拡散領第２とｐ型半導体
基板１の接合部に前記クランプ用のｐｎ接合ダイオード
（ＤＩ）が形成され、更にｎ十型拡散領域２が前記分圧
効果を有する直列抵抗および接合容量を構成する。In the skeleton structure, the clamping pn junction diode (DI) is formed at the junction between the second n0 type diffusion region and the p type semiconductor substrate 1, and the n0 type diffusion region 2 is further connected to the partial voltage constitute a series resistance and junction capacitance that has an effect.
このような従来構造に於ては、ｎ十型拡散領域２が微小
であり、入カバ′ツド電極５及び入力ＭＯＳトランジス
タＴＨのゲート電極Ｇと販ｎ十拡散領域２との接続が電
極コンタクト窓３ｍ、３ｂ、３ｏを介してなされる。そ
のため人力パット電極５に静電気等の高電圧が印加され
た際に、前記コンタクト窓部に電界が集中するので接続
破壊や接合破壊を起し、回路が切断される場合がある。In such a conventional structure, the n0 type diffusion region 2 is minute and the connection between the input covered electrode 5 and the gate electrode G of the input MOS transistor TH and the solder n0 type diffusion region 2 is through the electrode contact window. It is done via 3m, 3b, 3o. Therefore, when a high voltage such as static electricity is applied to the manual pad electrode 5, the electric field concentrates on the contact window, causing connection breakdown or junction breakdown, and the circuit may be disconnected.
（ｄ） 発明の目的
３一
本発明の目的は、上記入力トランジスタ保護用の直列抵
抗及びクランプ・ダイオードとなる第１の不純物拡散領
域と入力パッド電極の間に１、所望の接合容量を有し、
且つ多数の電極コンタクト部を有する第２の不純物拡散
領域を並列に接続することによし、前記第１の不純物拡
散領域と入力パッド電極の接続部に高パワーのサージ電
圧が短時間に印加されるのを防止せしめることにより、
上記問題点を除去することにある。(d) Object of the Invention 3. An object of the present invention is to provide a method of forming a transistor having a desired junction capacitance between the input pad electrode and the first impurity diffusion region that serves as the series resistor and clamp diode for protecting the input transistor. ,
In addition, by connecting the second impurity diffusion regions having a large number of electrode contact portions in parallel, a high power surge voltage is applied to the connection portion between the first impurity diffusion region and the input pad electrode in a short time. By preventing
The purpose is to eliminate the above problems.
（ｅ） 発明の構成
即ち本発明は、入力トランジスタに第１の不純物拡散領
域の一端部が接続され、該第１の不純物拡散領域の他端
部に人力パット電極が接続される半導体集積回路装置に
於て、入力パッド電極の近傍に前記第１の不純物拡散領
域と同導電型の第２の不純物拡散領域を設け、該第２の
不純物拡散領域を、該第２の不純物拡散領域上の絶縁膜
に設けた複数の電極コンタクト窓を介して該第２の不純
物拡散領域に前記入力バッド電極を接続してなることを
特徴とする。(e) Structure of the invention, that is, the present invention provides a semiconductor integrated circuit device in which one end of a first impurity diffusion region is connected to an input transistor, and a manual pad electrode is connected to the other end of the first impurity diffusion region. A second impurity diffusion region of the same conductivity type as the first impurity diffusion region is provided near the input pad electrode, and the second impurity diffusion region is connected to an insulating layer on the second impurity diffusion region. The input pad electrode is connected to the second impurity diffusion region through a plurality of electrode contact windows provided in the film.
４−
（ｆ） 発明の実施例
以下本発明を一実施例について、第３図に示す透視平面
図（イ）及びそのＡ −Ａ’矢視断面図（ロ）を用いて
詳細に説明する。4-(f) Embodiment of the Invention Hereinafter, one embodiment of the present invention will be described in detail using a perspective plan view (A) and a sectional view taken along the line A-A' (B) shown in FIG.
なお透視平面、図（イ）に於ては、下層の絶縁膜及びカ
バー絶縁膜は省略されている。Note that in the perspective plane, the lower insulating film and the cover insulating film are omitted.
本発明の構造に於ては、例えば第３図（イ）及び（ロ）
に示すように、フィールド酸化膜１１の上部領域に下層
ＰＳＧ絶縁膜１２を介してアルミニウム（ＡＺ）等から
なる入力バッド電極１３が配設される。この人力パッド
電極１３はその延出部１３′の端部に於て、下層ＰＳＧ
絶縁膜１２の電極コンタクト窓１４ａを介してｐ型シリ
コン（ｓｉ）基板１５面に形成された第１のＮ＋型拡散
領域１６の一端部に接続される。なお該第１のＮ十型拡
散領域１６は入力ＭＯＳトランジスタＴＲの保瞳抵抵及
びクランプやダイオードの機能を有しており、従って別
の一端部は下層ＰＳＧ絶縁膜１２の電極コンタクト窓１
４ｂ、１４ｃ及び上層配線りを介して入力トランジスタ
ＴＨのゲート電極Ｇに接続される。In the structure of the present invention, for example, Fig. 3 (a) and (b)
As shown in FIG. 2, an input pad electrode 13 made of aluminum (AZ) or the like is provided in the upper region of the field oxide film 11 with a lower PSG insulating film 12 interposed therebetween. This human power pad electrode 13 is connected to the lower PSG at the end of its extending portion 13'.
It is connected to one end of a first N+ type diffusion region 16 formed on the surface of a p-type silicon (si) substrate 15 through an electrode contact window 14a of the insulating film 12. Note that the first N-type diffusion region 16 has the functions of a pupil-keeping resistor, a clamp, and a diode for the input MOS transistor TR, and therefore, another end thereof is connected to the electrode contact window 1 of the lower PSG insulating film 12.
It is connected to the gate electrode G of the input transistor TH via 4b, 14c and upper layer wiring.
そして入力パッド電極１３近傍周辺部のｐ型Ｓ１基板１
５面に、該入力パッド電極１３を囲むように第２のＮ中
型拡散領域１７が配設されている。Then, the p-type S1 substrate 1 in the vicinity of the input pad electrode 13
A second N medium-sized diffusion region 17 is provided on the fifth surface so as to surround the input pad electrode 13.
そして該第２のＮ＋型拡散領域−１７は前記入カッくッ
ド電極１３と第１のＮ＋型拡散領域１６の間、即ち入力
パッド電極延出部１３′から入力バッド電極１３と並列
に入力バッド電極１３を囲む状態に延出された環状電極
１８によって、第２のＮ＋型拡散領域１７上の下層ＰＳ
Ｇ絶縁膜１２に形成した多数個の電極コンタクト窓１４
ｄ〜１４ｍを介して、入力パッド電極１３に接続されて
なっている０上記構造に於ては、入力パッド電極１３に
印加された静電気等の瞬時的高電圧は入力パッド電極１
３に接続している環状電極１８を経て、多数個の電極コ
ンタクト窓１４ｄ〜１４ｇに分散されこれら電極窓１４
ｄ〜１４ｇを介して第２のＮ中型拡散領域１７とｐ型Ｓ
ｔ基板１５間に形成される接合容量に一時的に蓄積され
、該容量と第１のＮ生型拡散領域１６の抵抗とで構成さ
れる遅延特性に沿って徐々にクランプ・ダイオード（Ｄ
ｌ）を経て放出されるので、入力ＭＯ８）ランジスタＴ
ＲのゲートＧ保護機能を持つ第１のＮ生型拡散領域１６
と入力パッド電極１３を接続するコンタクト窓１４＆部
、及び第１のＮ生型拡散領域１６とゲート電極Ｇを接続
するコンタクト窓１４ｂ及び１４ａ部に高電圧が短時間
に集中印加されることがなくなる０上記実施例に於ては
、第２のＮ中型拡散領域１７を入力パッド電極１３を囲
む環状に形成したが、該第２ＯＮ＋型拡散領斌は上記環
状に限らない。The second N+ type diffusion region -17 is input between the input cup electrode 13 and the first N+ type diffusion region 16, that is, from the input pad electrode extension portion 13' in parallel with the input pad electrode 13. The lower layer PS on the second N+ type diffusion region 17 is
A large number of electrode contact windows 14 formed in the G insulating film 12
In the above structure, instantaneous high voltage such as static electricity applied to the input pad electrode 13 is connected to the input pad electrode 13 through the input pad electrode 14m.
These electrode windows 14 are distributed over a large number of electrode contact windows 14d to 14g through an annular electrode 18 connected to
d to 14g to the second N medium diffusion region 17 and the p-type S
The clamp diode (D
l), so the input MO8) transistor T
First N-type diffusion region 16 with R gate G protection function
High voltage is no longer intensively applied in a short period of time to the contact window 14& section connecting the input pad electrode 13 and the contact window 14b and 14a section connecting the first N-type diffusion region 16 and the gate electrode G. 0 In the above embodiment, the second N medium type diffusion region 17 was formed in a ring shape surrounding the input pad electrode 13, but the second ON+ type diffusion region is not limited to the above ring shape.
即ち一部が欠けた不完全環状でも良く、又入カッくッド
電極の近傍に１箇所又は数箇所に分けて形成してもよい
。そしてその容量はいずれの場合も、該ＩＣの動作速度
を考慮して適切な値に選ばねばならない。That is, it may have an incomplete annular shape with a portion missing, or it may be formed in one place or in several places in the vicinity of the injected cup electrode. In any case, the capacitance must be selected at an appropriate value in consideration of the operating speed of the IC.
なお上記実施例の構造を形成する際に、通常のＭＯ８Ｉ
Ｃを形成する工程以外に別な工程が追加され製造工程が
複雑化することはない。Note that when forming the structure of the above example, ordinary MO8I
The manufacturing process is not complicated by adding another process other than the process of forming C.
即ち第３図に於けるＭＯＳトランジスタＴＲのＮ中型ソ
ース領域１９．Ｎ中型ドレイン領域２０゜第１のＮ中型
拡散領域１・、６．及び本発明の第２のＮ＋＝７−
型拡散領域１７は選択酸化法によって形成したフィール
ド酸化膜１１をマスクにして選択イオン注入によ９同時
に形成でき、又下層ＰＳＧ絶縁膜１２の各電極窓１４ａ
〜１４ｇの形成も同時になされる○そして又入力パッド
電極１３．同延出部１３′及び本発明の環状電極１８は
同一電極材料層から同時にパターンニングされる。（図
中２１はカバー絶縁膜）
（Ｘ） 発明の詳細
な説明したように本発明の構造に於ては、入力パッド電
極に印加された静電気等の高電圧は、入力パッド電極と
入力トランジスタの保護抵抗及びクランプ・ダイオード
となる第１の不純物拡散領域の間に配置された第２の不
純物拡散領域に、多数の電極コンタクト窓を介して分散
供給され、該第２の不純物拡散領域のｐｎ接合容量に一
時的に蓄積される。従って前記第１の不純物拡散領域と
入力パット電極の接続部及び入力トランジスタのゲート
電極との接続部に急激に高電圧が印加されることがなく
なり、これら接続部の破壊が防止８−
されるので、ＩＣの静電耐量は増加する。That is, the N medium-sized source region 19 of the MOS transistor TR in FIG. N medium-sized drain region 20° first N medium-sized diffusion region 1., 6. The second N+=7- type diffusion region 17 of the present invention can be formed simultaneously by selective ion implantation using the field oxide film 11 formed by the selective oxidation method as a mask. 14a
~14g is also formed at the same time○ and also input pad electrode 13. The extension 13' and the annular electrode 18 of the present invention are simultaneously patterned from the same layer of electrode material. (21 in the figure is a cover insulating film) (X) As described in detail, in the structure of the present invention, high voltage such as static electricity applied to the input pad electrode is transferred between the input pad electrode and the input transistor. A second impurity diffusion region disposed between the first impurity diffusion regions serving as a protection resistor and a clamp diode is supplied in a distributed manner through a number of electrode contact windows, and the pn junction of the second impurity diffusion region is distributed. Temporarily stored in capacity. Therefore, a high voltage is not suddenly applied to the connection between the first impurity diffusion region and the input pad electrode and the gate electrode of the input transistor, and destruction of these connection areas is prevented. , the electrostatic capacity of the IC increases.
又本発明の構造に於ては、入力パッド電極はフィールド
酸化膜の上部領域に設けられるので、ワイヤ会ボンディ
ングに対する耐性も極めて大きい。Also, in the structure of the present invention, since the input pad electrode is provided in the upper region of the field oxide film, resistance to wire bonding is also extremely high.
なお本発明の構造はいずれの導電型にも適用することが
でき、更に出力パッド電極側に適用することもできる。Note that the structure of the present invention can be applied to any conductivity type, and can also be applied to the output pad electrode side.
第１図は従来の入力保護回路図、第２図は従来の入力保
護回路の透視平面図（イ）及びＡ −Ａ’矢視断面図（
ロ）で、第３図は本発明の入力保護回路の透視平面図（
イ）及びＡ −Ａ’矢視断面図（ロ）である。
図に於て、１１はフィールド酸化膜、１２は下層りん珪
酸ガラス絶縁膜、１３は入力パッド電極。
１３′は入力パッド電極延出部、１４ａ〜１４Ｂは電極
コンタクト窓、１５はｐ型シリコン基板、１６は第１の
Ｎ中型拡散領域、１７は第２のＮ中型拡散領域、１Ｂは
環状電極、１９はＮ生型ソース領域。
２０はＮ中型ドレイン領域、Ｔｎは入力ＭＯ８）ランジ
スタ、Ｇはゲート電極、Ｌは上層配線を示す。
第 １ ス
見 ２ 閃
％ ３ 図Fig. 1 is a diagram of a conventional input protection circuit, and Fig. 2 is a perspective plan view (A) and a sectional view taken along arrows A-A' of the conventional input protection circuit (A).
b), and Fig. 3 is a perspective plan view of the input protection circuit of the present invention (
1) and a sectional view taken along the line A-A' (b). In the figure, 11 is a field oxide film, 12 is a lower phosphosilicate glass insulating film, and 13 is an input pad electrode. 13' is an input pad electrode extension, 14a to 14B are electrode contact windows, 15 is a p-type silicon substrate, 16 is a first N medium-sized diffusion region, 17 is a second N medium-sized diffusion region, 1B is an annular electrode, 19 is an N-type source region. 20 is an N medium-sized drain region, Tn is an input MO8) transistor, G is a gate electrode, and L is an upper layer wiring. 1st Scene 2 Flash% 3 Figure
Claims (1)
続され、該第１の不純物拡散領域の他端部に入力パッド
電極が接続される構造に於て、入力パッド電極の近傍に
前記第１の不純物拡散領域と同導電型の第２の不純物拡
散領域を設け、該第２の不純物拡散領域上の絶縁膜に設
けた複数の電極コンタクト窓を介して該第２の不純物拡
散領域に前記入力パッド電極を接続してなることを特徴
とする半導体集積回路装置。In a structure in which one end of the first impurity diffusion region is connected to the input transistor and an input pad electrode is connected to the other end of the first impurity diffusion region, the first impurity diffusion region is connected near the input pad electrode. A second impurity diffusion region of the same conductivity type as the impurity diffusion region is provided, and the input pad is connected to the second impurity diffusion region via a plurality of electrode contact windows provided in an insulating film over the second impurity diffusion region. A semiconductor integrated circuit device characterized by connecting electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57086012A JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57086012A JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58202573A true JPS58202573A (en) | 1983-11-25 |
| JPS6355871B2 JPS6355871B2 (en) | 1988-11-04 |
Family
ID=13874765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57086012A Granted JPS58202573A (en) | 1982-05-21 | 1982-05-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58202573A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263260A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Semiconductor device |
| US4806999A (en) * | 1985-09-30 | 1989-02-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Area efficient input protection |
| US4821089A (en) * | 1985-10-15 | 1989-04-11 | American Telephone And Telegraph Company, At&T Laboratories | Protection of IGFET integrated circuits from electrostatic discharge |
-
1982
- 1982-05-21 JP JP57086012A patent/JPS58202573A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263260A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Semiconductor device |
| US4806999A (en) * | 1985-09-30 | 1989-02-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Area efficient input protection |
| US4821089A (en) * | 1985-10-15 | 1989-04-11 | American Telephone And Telegraph Company, At&T Laboratories | Protection of IGFET integrated circuits from electrostatic discharge |
| JPH0828426B2 (en) * | 1985-10-15 | 1996-03-21 | エイ・ティ・アンド・ティ・コーポレーション | Protection of IGFET integrated circuits from electrostatic discharge |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6355871B2 (en) | 1988-11-04 |
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