JPS58190064A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS58190064A JPS58190064A JP57071232A JP7123282A JPS58190064A JP S58190064 A JPS58190064 A JP S58190064A JP 57071232 A JP57071232 A JP 57071232A JP 7123282 A JP7123282 A JP 7123282A JP S58190064 A JPS58190064 A JP S58190064A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- junction
- light
- source
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 101100081489 Drosophila melanogaster Obp83a gene Proteins 0.000 description 1
- 230000002421 anti-septic effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＥＰＲＯＭオンチップＬＳＩに係り、特にＰ−
Ｎ接合への光の入射によるリーク特性を改善するのに好
適なＬＳＩの形成法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an EPROM on-chip LSI, and in particular to a P-ROM on-chip LSI.
The present invention relates to a method of forming an LSI suitable for improving leakage characteristics due to light incident on an N junction.
ＭＯＳ Ｆ Ｅ’ｒｆｌゲートのオフ状態のインピーダ
ンスが高いことから、第１図に示すような、配線上の容
量をメモリ素子とする回路が従来からよく使用されてい
る。しかし、紫外線等で消去できるメモリ（以下ＥＰＲ
ＯＭ）を内蔵するＬＳＩチップにおいてＵ、Ｔ、ＳＩ衣
表面外光にさらされるために、ＭＯＳＦＥＴの拡散層と
基板との間の接合部で多量のり−クＮＲを発生する。こ
のため、メモリ素子として十分な記憶保持特性を得るこ
とができない欠点があった。Since the impedance of the MOS F E'rfl gate in the off state is high, a circuit as shown in FIG. 1 in which a capacitor on a wiring is used as a memory element has been commonly used. However, memory that can be erased by ultraviolet rays (hereinafter referred to as EPR)
In an LSI chip incorporating a MOSFET, a large amount of glue NR is generated at the junction between the MOSFET diffusion layer and the substrate because the surfaces of the U, T, and SI layers are exposed to external light. For this reason, there was a drawback that sufficient memory retention characteristics could not be obtained as a memory element.
通常のＬＳＩのパッケージは光を完全に遮へいする構造
になっており、光の入射による特性の悪化になかった。A typical LSI package has a structure that completely blocks light, so its characteristics do not deteriorate due to the incidence of light.
ＥＰＲＯＭオンチップＬＳＩにおいては、ＥＰＲＯＭの
データ消去は紫外線でおこなうため、パッケージ上部は
透明物質でおおわれており、特性悪化を防止するために
はチップを部分的に光から遮へいする必要がある。In EPROM on-chip LSIs, since data in the EPROM is erased using ultraviolet light, the upper part of the package is covered with a transparent material, and it is necessary to partially shield the chip from light in order to prevent deterioration of characteristics.
本発明の目的はＭＯＳ Ｆ ＥＴの拡散層領域への光の
入射を防止し、Ｐ−Ｎ接合のリーク特性を改善すること
にある。An object of the present invention is to prevent light from entering the diffusion layer region of a MOS FET and to improve the leakage characteristics of the PN junction.
このため、本発明では、情報記憶用に用いるＭＯＳ Ｆ
ＥＴの拡散層の上部に金属電極を設けた。Therefore, in the present invention, MOS F used for information storage
A metal electrode was provided on top of the ET diffusion layer.
通常のＬＳＩのパッケージは光ｋＲ全に遮へいする構造
になっており、光入射による特性の悪化は問題とはなら
な〃・つた。ＥＰｒｔＯＭオンチップＬ Ｓ Ｉにおい
ては光によるデータ消去の必要性上パッケージ上部が透
明物質でおおわれており、特性悪化を防止する九めにＴ
、ＳＩテップを部分的に光から遮へいするようにした。A normal LSI package has a structure that shields all of the light kR, so deterioration of characteristics due to light incidence is not a problem. In EPrtOM on-chip LSI, the upper part of the package is covered with a transparent material because it is necessary to erase data with light, and the ninth layer of T is used to prevent deterioration of characteristics.
, the SI tip was partially shielded from light.
以下、本発明の実施例をＥ Ｐ ＴＬ ＯＭ （Ｅ ｒ
ａｓａｂｌｅｐｒｏｇｒａｍａｂｌｅ ＲＯＭ ）オ
ンチップ半導体集積回路において実施した場合について
述べる。Hereinafter, embodiments of the present invention will be described as E P TL OM (E r
(asable programmable ROM) A case where it is implemented in an on-chip semiconductor integrated circuit will be described.
ＥＦＲＯＭオンチップ半導体集積回路は、ＢＦＲＯＭに
記憶されているデータを光によって消去するため、透明
パッケージに実装されている。The EFROM on-chip semiconductor integrated circuit is mounted in a transparent package in order to erase data stored in the BFROM using light.
第１図に本実施例で述べるＭＯＳＦＥＴで構成したライ
ンメモリ（配線容量などにデータを記憶保持するメモリ
１０回路図を示す。ＭＯ８ＦＥＴＩの入力電極３から入
力されたデータはｌがオンしている期間に１のソース拡
散ｌ−４、インバータ２の入力ゲート５、および４〜５
間の配線容ｌの総和６に伝搬され、１がオフするとデー
タげ６に記憶保持される。しかし４と基板から成るＰ−
Ｎ接合７に透明パッケージを介して光が入射すると光エ
ネルギーにより７のリーク電流（Ｐ−Ｎ接合の逆方向飽
和′電流）が増加し、６に蓄えられた電荷は徐々に失な
われることになる。Figure 1 shows a circuit diagram of a line memory (memory 10 that stores and holds data in wiring capacitors, etc.) configured with MOSFETs described in this embodiment.Data input from the input electrode 3 of MO8FETI is transmitted during the period when l is on. 1 source diffusion l-4, input gate 5 of inverter 2, and 4-5
It is propagated to the sum 6 of the wiring capacitance 1 between them, and when 1 is turned off, it is stored and held in the data column 6. However, P− consisting of 4 and the substrate
When light enters N junction 7 through the transparent package, the leakage current of 7 (reverse saturation current of P-N junction) increases due to the light energy, and the charge stored in 6 is gradually lost. Become.
実施例１
第２図は第１図の回路において本発明を実施した例のＭ
ＯＳ Ｆ’ Ｅ Ｔの縦構造を示したものである。Example 1 FIG. 2 shows an example of M in which the present invention is implemented in the circuit shown in FIG. 1.
This shows the vertical structure of OS F'ET.
ドレイン拡散層８、ゲート９、ソース拡散層１０から成
るＭＯ８Ｆ’ＥＴ（第１図の１）の入力電極Ａｔ（アル
ミニウム）１１から入力されたデータは１０、インバー
タのゲート酸化膜２０から成る入力ゲート１２（第１図
の５）および１０〜１２間の配線１３の容量に記憶保持
される。本発明では電荷を記憶保持するためにを与して
いる拡散層１０の上部に、配線のＡｔ１１と同時に形成
したＡ４１５を電源などの固定した電位に接続して配置
することにより、透明パッケージ１４を透過して入射し
た光は透明な保珈膜１９を通過したのち、Ａｔ層１５の
表面で反射するため、１０と基板１６から成るＰ−Ｎ接
合（第１図の７）への光の入射を防ぎ、１０−１６の接
合でのリーク電流の増加を防止することができる。The data input from the input electrode At (aluminum) 11 of the MO8F'ET (1 in Figure 1) consisting of the drain diffusion layer 8, gate 9, and source diffusion layer 10 is input to the input gate 10 consisting of the gate oxide film 20 of the inverter. 12 (5 in FIG. 1) and the capacitance of the wiring 13 between 10 and 12. In the present invention, the transparent package 14 is formed by connecting A415, which was formed at the same time as the wiring At11, to a fixed potential such as a power source, on the top of the diffusion layer 10, which serves to store and hold charges. The transmitted and incident light passes through the transparent antiseptic film 19 and is then reflected on the surface of the At layer 15, so that the light enters the P-N junction (7 in FIG. 1) consisting of the At layer 10 and the substrate 16. can be prevented, and an increase in leakage current at the 10-16 junction can be prevented.
本実施例によれば、リーク悟性の悪化を防ぐとともに、
拡散層１０の容ｈａげ１５に対する容量も伺加され、記
憶保持するだめの総容量が増えることになり、さらに記
憶悟性を改善する効果がおる。According to this embodiment, while preventing deterioration of leak sensitivity,
The capacitance of the diffusion layer 10 for the capacitance 15 is also increased, increasing the total memory storage capacity, which has the effect of further improving memory comprehension.
実施例２
第３図は実施例１において、拡散層１０の上部に形成す
るＡ／＝１５を１０自身に結合して１０と同電位にした
場合の縦構造を示す。光に対する効果は実施例１と同様
であるが、拡散層１０の容量は１５を形成しても増加し
ない。従って記憶保持するだめの容−１は増加せず、高
速動作を必要とする場合に効果がある。Embodiment 2 FIG. 3 shows a vertical structure in Embodiment 1 when A/=15 formed above the diffusion layer 10 is coupled to 10 itself to have the same potential as 10. Although the effect on light is similar to that in Example 1, the capacitance of the diffusion layer 10 does not increase even if the diffusion layer 15 is formed. Therefore, the memory storage capacity -1 does not increase, which is effective when high-speed operation is required.
以上の二実１ｍ例ＨＮチャンネルＭＯ８について示シた
が、Ｐチャンネル間０８およびそれらを組合わせた回路
についても同様の効果がある。Although the above example of two 1m HN channel MO8 has been shown, the same effect can be obtained for the P channel inter-channel 08 and a circuit combining them.
上記実施例はラインメモリを構成する場合について示し
たが、他に微小を流を扱かうアナログ回路等の接合面か
らのリーク電流の防止方法とじても有効である。Although the above embodiment has been described for the case of configuring a line memory, it is also effective as a method for preventing leakage current from the junction surface of analog circuits that handle minute currents.
本発明によれば、Ｐ−Ｎ接合への光の入射を遮断できる
ので、光によるＰ−Ｎ接合の逆方向飽和電流の増加を防
止する効果がある。According to the present invention, since it is possible to block light from entering the P-N junction, there is an effect of preventing an increase in the reverse saturation current of the P-N junction due to light.
光の遮断面となるアルミ層１５は従来のＭＯ８ＦＥＴ形
成における配線用のアルミ層１１の形成と同時に行なう
ことができ、プロセスの増加を必要としない。またアル
ミ層１５は拡散層１０に重なる形に形成するために、Ｌ
ＳＩ形成上、面積の増加等の問題は生じない。The aluminum layer 15 serving as a light blocking surface can be formed simultaneously with the formation of the wiring aluminum layer 11 in the conventional MO8FET formation, and no increase in the number of processes is required. In addition, in order to form the aluminum layer 15 so as to overlap the diffusion layer 10, L
In forming the SI, problems such as an increase in area do not occur.
【図面の簡単な説明】
第１図は配線容量を記憶素子として用いるメモリ（ライ
ン・メモリ）の回路図である。
第２図はＡｔを固定電位にした場合の第１図の回路のＭ
Ｏ８Ｆ’ＥＴ縦構造である。
第３図はＡｔを拡散層に結合した場合の第１図の回路の
ＭＯＳ Ｆ’ ＥＴ縦構造である。
１・・・入力ＭＯ８ＦＥＴ、２・・・インバータ、３・
・・入力電極、４・・・ソース電極、５・・・入力ゲー
ト、６・・・配線容量、７・・・Ｐ−Ｎ接合、８・・・
ドレイン拡散層、９・・・ゲート電極、１０・・・ソー
ス拡散層、ｌ】・・・入力Ａｔ１！極、１２・・・イン
バータの入力ゲート、１３・・・入力ＭＯＳ Ｆ ＦＡ
Ｔとインバータ間の配線、１４・・・透明パッケージ、
１５・・・光遮へい用Ａｔ１１６・・・基板、１７・・
・酸化膜、１８・・・透明絶縁膜、第 ２ 図
克
６
■ ３ 図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a memory (line memory) that uses wiring capacitors as storage elements. Figure 2 shows the M of the circuit in Figure 1 when At is set to a fixed potential.
O8F'ET vertical structure. FIG. 3 shows the MOS F'ET vertical structure of the circuit of FIG. 1 when At is coupled to the diffusion layer. 1... Input MO8FET, 2... Inverter, 3...
... Input electrode, 4... Source electrode, 5... Input gate, 6... Wiring capacitance, 7... P-N junction, 8...
Drain diffusion layer, 9... Gate electrode, 10... Source diffusion layer, l]... Input At1! Pole, 12... Inverter input gate, 13... Input MOS F FA
Wiring between T and inverter, 14...transparent package,
15... At116... substrate for light shielding, 17...
・Oxide film, 18...Transparent insulating film, Figure 2, Figure 6 ■ 3
Claims (1)
）層を形成し、光の入射を防止したことを特徴とする半
導体集積回路。 ２、Ｐ−Ｎ接合上に電位を固定したＡｔ層を形成し、光
の入射を防止したことを特徴とする第１項の半導体集積
回路。 ３、Ｐ−Ｎ接合上にソース筐たはドレインとなる拡散層
に接続したＡｔ層を形成し、光の入射を防止したことを
特徴とする第１項の半導体集積回路。[Claims] 1. A semiconductor integrated circuit characterized in that an Al (aluminum) layer is formed on an element (such as a MOSFET) to prevent light from entering. 2. The semiconductor integrated circuit according to item 1, characterized in that an At layer with a fixed potential is formed on the PN junction to prevent light from entering. 3. The semiconductor integrated circuit according to item 1, characterized in that an At layer connected to a source casing or a diffusion layer serving as a drain is formed on the PN junction to prevent light from entering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57071232A JPS58190064A (en) | 1982-04-30 | 1982-04-30 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57071232A JPS58190064A (en) | 1982-04-30 | 1982-04-30 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58190064A true JPS58190064A (en) | 1983-11-05 |
Family
ID=13454732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57071232A Pending JPS58190064A (en) | 1982-04-30 | 1982-04-30 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58190064A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0764985A2 (en) | 1995-09-22 | 1997-03-26 | Hughes Aircraft Company | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US5866933A (en) * | 1992-07-31 | 1999-02-02 | Hughes Electronics Corporation | Integrated circuit security system and method with implanted interconnections |
| US5973375A (en) * | 1997-06-06 | 1999-10-26 | Hughes Electronics Corporation | Camouflaged circuit structure with step implants |
| US6667245B2 (en) | 1999-11-10 | 2003-12-23 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
| US6740942B2 (en) | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
| US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
-
1982
- 1982-04-30 JP JP57071232A patent/JPS58190064A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5866933A (en) * | 1992-07-31 | 1999-02-02 | Hughes Electronics Corporation | Integrated circuit security system and method with implanted interconnections |
| US6294816B1 (en) | 1992-07-31 | 2001-09-25 | Hughes Electronics Corporation | Secure integrated circuit |
| US6613661B1 (en) | 1992-07-31 | 2003-09-02 | Hughes Electronics Corporation | Process for fabricating secure integrated circuit |
| EP0764985A2 (en) | 1995-09-22 | 1997-03-26 | Hughes Aircraft Company | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US5783846A (en) * | 1995-09-22 | 1998-07-21 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US5930663A (en) * | 1995-09-22 | 1999-07-27 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US6064110A (en) * | 1995-09-22 | 2000-05-16 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US5973375A (en) * | 1997-06-06 | 1999-10-26 | Hughes Electronics Corporation | Camouflaged circuit structure with step implants |
| US6667245B2 (en) | 1999-11-10 | 2003-12-23 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
| US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
| US6740942B2 (en) | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
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