JPS5817638A - Bump forming device - Google Patents

Bump forming device

Info

Publication number
JPS5817638A
JPS5817638A JP11508481A JP11508481A JPS5817638A JP S5817638 A JPS5817638 A JP S5817638A JP 11508481 A JP11508481 A JP 11508481A JP 11508481 A JP11508481 A JP 11508481A JP S5817638 A JPS5817638 A JP S5817638A
Authority
JP
Japan
Prior art keywords
wafer
electrode
current
bump forming
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11508481A
Other languages
Japanese (ja)
Other versions
JPS6325709B2 (en
Inventor
Kazuhisa Nakamoto
中元 和久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11508481A priority Critical patent/JPS5817638A/en
Publication of JPS5817638A publication Critical patent/JPS5817638A/en
Publication of JPS6325709B2 publication Critical patent/JPS6325709B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the number of obtained lots of excellent products by removing a current concentrated at the periphery of a wafer by an auxiliary electrode, equalizing the current distribution to the wafer and plating it. CONSTITUTION:A water 2 is inserted into the inside of an auxiliary electrode 5, and is secured to the holding surface of an electrode 3. The electrode 3 for setting the wafer 2 and an electrode plate 4 including plating solution are contacted oppositely. A current is flowed between the electrodes, 3, 5 and the plate 4 while rubbing between the electrode 3 and the plate 4, and a bump is grown on the bump forming surface of the main surface of the wafer 2. Then, since the current (designated by an arrow) at the periphery of the wafer 2 is also flowed through the electrode 5, the current is not concentrated at the bump forming portion at the periphery of the wafer 2, but flows uniformly over the entire bump forming parts of the wafer 2. As a result, the size of the bumps can be equalized.

Description

【発明の詳細な説明】 本発明はバンプ形成装置、主として半導体素子のパンダ
電極形成装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bump forming apparatus, mainly to a panda electrode forming apparatus for semiconductor devices.

従来、たとえば第1図に示すような、シリコンダイオー
ド7のAIIバンプ(バング電極)lの形成に当っては
、第2因に示すようにウェーハ(半導体薄板)it電極
に固定し、メッキ液な含んだ電極板4と対向させて電流
な流し、ウェー/S2と電極板4をたがいにこすり合せ
ながらウェーハ2の主面にバングな成長させる方法で行
なっている。しかしこの方法では、第3図に示すようK
Conventionally, when forming the AII bump (bang electrode) l of a silicon diode 7, as shown in FIG. The wafer 2 is grown in bangs on the main surface of the wafer 2 while a current is applied to the electrode plate 4 facing the wafer 2 and the wafer S2 and the electrode plate 4 are rubbed together. However, with this method, as shown in Figure 3,
.

ウェーハ周辺部でメッキ電流(矢印で示す。)の集中が
起き、ウェーハ周辺のバングが中心部にくらべ大キ<な
り、不良になってしまうという欠点があった。
There was a drawback that the plating current (indicated by the arrow) was concentrated at the periphery of the wafer, and the bangs around the wafer were larger than those at the center, resulting in defects.

したがって1本発明の目的は、ウェーハ全面に大きさの
均一なバングな形成することのできるバンプ形成装置を
提供することにある。
Therefore, one object of the present invention is to provide a bump forming apparatus that can form bumps of uniform size over the entire surface of a wafer.

上記の目的を達成するために1本発明は不良バンプ発生
の原因であるつ1−ハ周辺部へのメッキ電流の集中を防
止するために、ウェーハ乞支持する電極とは別にウェー
ハな取り囲むように補助電極51jI:配設し、ウェー
ハ周辺部に集中する電流を補助電極で取り除きウェー・
・への電流分布を均一にし℃メッキを行なうものであっ
て、以下実施例χより本発明な説明する。
In order to achieve the above objects, the present invention provides a method to prevent plating current from concentrating on the periphery of the wafer, which is a cause of the occurrence of defective bumps. Auxiliary electrode 51jI: Provided to remove current concentrated around the wafer with the auxiliary electrode.
The present invention will be explained below with reference to Example χ.

第454(s本発明の一実施例によるバンプ形成装置の
要部な示す断面図、第5図は同じくバンプ形成状態を示
す一部を断面とした説明図である。
454(s) A sectional view showing a main part of a bump forming apparatus according to an embodiment of the present invention. FIG.

第4図に示すように、このバング形成装置は、ウェーハ
2の直径よりもわずかに大きな円板状のガイド6Y!f
る。ガイド6の上面中央には支軸8が取り付けられ、ガ
イドゝ6はこの支軸8で支えられる。また、ガイド6の
下面中央には窪みが設けられ、この窪み部分には平板状
の電極3が埋め込まnている。電[j3の下面、すなわ
ち露出面はウェーハ2の保持面となり、かつガイド面と
同一面となっている。また、ガイド6の外周にはリング
状の補助電極5が嵌合されている。この補助電極5は前
記電極3の保持面よりも突出し、ウェーハ2を電極3に
密着保持した状態でウエーノ・2の下面(主面)である
露出面(バング形成面)と同一面となるように構成され
ている。ここで、電極3と補助電極51kl:固定する
ガイド6は電極3と補助電極5の絶縁なとるために絶縁
性なもっていることがメッキ電流の均一化な図る上で必
要である。
As shown in FIG. 4, this bang forming apparatus has a disk-shaped guide 6Y! which is slightly larger than the diameter of the wafer 2! f
Ru. A support shaft 8 is attached to the center of the upper surface of the guide 6, and the guide 6 is supported by this support shaft 8. Further, a depression is provided in the center of the lower surface of the guide 6, and a flat electrode 3 is embedded in this depression. The lower surface of the electric conductor [j3, that is, the exposed surface, serves as a holding surface for the wafer 2, and is flush with the guide surface. Further, a ring-shaped auxiliary electrode 5 is fitted on the outer periphery of the guide 6. The auxiliary electrode 5 protrudes beyond the holding surface of the electrode 3 and is flush with the exposed surface (bang forming surface) which is the lower surface (main surface) of the wafer 2 when the wafer 2 is held tightly against the electrode 3. It is composed of Here, the electrode 3 and the auxiliary electrode 51kl: The fixed guide 6 is required to have an insulating property in order to insulate the electrode 3 and the auxiliary electrode 5 in order to make the plating current uniform.

また、ガイド6に対面し工メッキ液な含んだ電極板4が
配設されている。
Further, an electrode plate 4 containing a plating solution is disposed facing the guide 6.

このような装置にあっては、ウェーハ2を補助電極5の
内側に入れるとと4に、@Jij、3の保持面に固定す
る。そして、上記のウェーハ2をセットした電極3と、
メッキ液を含んだ電極板4を対向接触させ、だがいくこ
すり合せながら、電極3゜補助電極5と電極板4間に電
流を流しウェーハ2の主面であるバンプ形成面にバング
を成長させる。
In such an apparatus, the wafer 2 is placed inside the auxiliary electrode 5 and fixed to the holding surface of the groove 4 and @Jij, 3. Then, the electrode 3 on which the above wafer 2 is set,
Electrode plates 4 containing a plating solution are placed in opposing contact with each other, and while being rubbed together, a current is passed between the electrode 3°, the auxiliary electrode 5 and the electrode plate 4 to grow a bang on the bump forming surface which is the main surface of the wafer 2.

すると、第5図に示すように、ウェーハ2の周辺部の電
流(電流は矢印で示す。)は補助電極5にも流れること
から、ウェーハ2の周辺部のバング形成部に集中するこ
とはなくなり、ウェーハ2の全域の各バンプ形成部に均
一に電流が流れる。この結果、バンプの大きさが均一と
なる。
Then, as shown in FIG. 5, the current at the periphery of the wafer 2 (the current is indicated by an arrow) also flows to the auxiliary electrode 5, so that it is no longer concentrated at the bang forming area at the periphery of the wafer 2. , current flows uniformly to each bump forming portion over the entire area of the wafer 2. As a result, the size of the bumps becomes uniform.

なお、本発明は前記実施例に限定されない。すなわち、
補助電極はリング状でなくともよく、不連続構造のもの
でもよい。また、バンプはバンプ電極に限定されない。
Note that the present invention is not limited to the above embodiments. That is,
The auxiliary electrode does not have to be ring-shaped and may have a discontinuous structure. Further, the bump is not limited to a bump electrode.

以上説明した如く、本発明によれば、ウェーハ全面に均
一なバンプが得られることから、良品ペレット取得数が
向上する。この結果、製品のコスト低減が図れる。
As explained above, according to the present invention, uniform bumps can be obtained over the entire surface of the wafer, thereby increasing the number of good pellets obtained. As a result, the cost of the product can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、バンプの説明図、第2図は、バンプメッキ法
の説明図、第3図は、不良バング発生原因図、第4図は
、本発明の概要を示す要部の断面図、第5図は同じく本
発明の実施例における電流の流れる状態を示す説明図で
ある。 l・・・バング、2・・・ウェーハ、3・・・電極、4
・・・電極板、5・・・補助電極、6・・・ガイド、7
・・・ダイオード、8・・・支軸。 第  1  図 第  2  図 第  3  図
Fig. 1 is an explanatory diagram of a bump, Fig. 2 is an explanatory diagram of a bump plating method, Fig. 3 is an illustration of causes of defective bangs, and Fig. 4 is a sectional view of main parts showing an outline of the present invention. FIG. 5 is an explanatory diagram showing the state of current flow in the embodiment of the present invention. l... Bang, 2... Wafer, 3... Electrode, 4
...Electrode plate, 5...Auxiliary electrode, 6...Guide, 7
...Diode, 8...Spindle. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、電極の保持面に被メッキ物を保持するとともに、メ
ッキ液な含んだ電極板に被メッキ物の露出する主面な接
触させて電圧な電極と電極間に印加し、被メツキ物主面
に電解メッキによってバングな形成する装置において、
前記被メッキ物を取り囲む突出した補助電極を配設して
おくことt%像とするバング形成装置。
1. While holding the object to be plated on the holding surface of the electrode, bring the exposed main surface of the object to be plated into contact with the electrode plate containing the plating solution, and apply a voltage between the electrodes to remove the main surface of the object to be plated. In the device that forms bangs by electrolytic plating,
A bang forming apparatus in which a protruding auxiliary electrode surrounding the object to be plated is provided.
JP11508481A 1981-07-24 1981-07-24 Bump forming device Granted JPS5817638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11508481A JPS5817638A (en) 1981-07-24 1981-07-24 Bump forming device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11508481A JPS5817638A (en) 1981-07-24 1981-07-24 Bump forming device

Publications (2)

Publication Number Publication Date
JPS5817638A true JPS5817638A (en) 1983-02-01
JPS6325709B2 JPS6325709B2 (en) 1988-05-26

Family

ID=14653788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11508481A Granted JPS5817638A (en) 1981-07-24 1981-07-24 Bump forming device

Country Status (1)

Country Link
JP (1) JPS5817638A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6025149U (en) * 1983-07-27 1985-02-20 関西日本電気株式会社 Bump electrode formation wafer
JPS636860A (en) * 1986-06-27 1988-01-12 Oki Electric Ind Co Ltd Formation of solder bump for flip chip
JPH01156566A (en) * 1987-12-07 1989-06-20 Pellerin Milnor Corp Machine and method for treating liquid absorbing fabric
DE19803490C2 (en) * 1997-04-28 2003-04-24 Mitsubishi Electric Corp separating

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6025149U (en) * 1983-07-27 1985-02-20 関西日本電気株式会社 Bump electrode formation wafer
JPS642443Y2 (en) * 1983-07-27 1989-01-20
JPS636860A (en) * 1986-06-27 1988-01-12 Oki Electric Ind Co Ltd Formation of solder bump for flip chip
JPH0580141B2 (en) * 1986-06-27 1993-11-08 Oki Electric Ind Co Ltd
JPH01156566A (en) * 1987-12-07 1989-06-20 Pellerin Milnor Corp Machine and method for treating liquid absorbing fabric
JPH0351828B2 (en) * 1987-12-07 1991-08-08 Pellerin Corp Milnor
DE19803490C2 (en) * 1997-04-28 2003-04-24 Mitsubishi Electric Corp separating

Also Published As

Publication number Publication date
JPS6325709B2 (en) 1988-05-26

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