JPS58171842A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS58171842A JPS58171842A JP57054288A JP5428882A JPS58171842A JP S58171842 A JPS58171842 A JP S58171842A JP 57054288 A JP57054288 A JP 57054288A JP 5428882 A JP5428882 A JP 5428882A JP S58171842 A JPS58171842 A JP S58171842A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- voltage
- input clock
- clock frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、機能回路ブロックへ供給される動作電圧をシ
ステムの動作速度に応じて可変設定する動作電圧変換回
路を有する回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit device having an operating voltage conversion circuit that variably sets the operating voltage supplied to a functional circuit block in accordance with the operating speed of a system.
近年、低消費電力を目的として相補型MO8集積回路を
使ったシステムが多く用いられるようになってきた。一
般に、相補型MO8集積回路の動作速度は動作電流に比
例し、また、この動作電流は動作電圧に比例する。従っ
て、低消費電力にするためには、動作速度が使用目的を
達成する範囲内で、動作電圧を可能な限り低くすること
が望まれる。In recent years, systems using complementary MO8 integrated circuits have come into widespread use for the purpose of low power consumption. Generally, the operating speed of a complementary MO8 integrated circuit is proportional to the operating current, which in turn is proportional to the operating voltage. Therefore, in order to reduce power consumption, it is desirable to lower the operating voltage as much as possible within the range where the operating speed achieves the intended use.
ところで、マイクロコンピュータ等の汎用に使用される
集積回路では、仕様で明記された電源電圧の範囲内で仕
様を満足する高速動作を確保するように、内部機能回路
ブロックを設計する。このため、従来は低速動作の場合
でも、高速動作可能な動作電圧で内部機能回路ブロック
を動作させており、無駄な電力消費もともなっていた。Incidentally, in integrated circuits used for general purposes such as microcomputers, internal functional circuit blocks are designed to ensure high-speed operation that satisfies the specifications within the power supply voltage range specified in the specifications. For this reason, conventionally, even in the case of low-speed operation, internal functional circuit blocks have been operated at an operating voltage that allows high-speed operation, resulting in wasteful power consumption.
本発明は上記欠点にかんがみなされたもので、単一の電
源電圧に対し、入力クロック周波数検出回路、定電圧電
源回路及び電源選択回路の各部により、入力クロック周
波数に応じて機能回路ブロックの動作電圧を適宜選択し
て最適な値に設定し得る集積回路装置を提供せんとする
ものである。The present invention has been made in view of the above-mentioned drawbacks, and the present invention has been made in consideration of the above-mentioned drawbacks. It is an object of the present invention to provide an integrated circuit device that can appropriately select and set the optimum value.
以下、本発明の構成を実施例を用いて説明する。Hereinafter, the configuration of the present invention will be explained using examples.
第1図は本発明の実施例に係る集積回路装置の基本ブロ
ック図である。本構成は入力クロック周波数検出回路部
1、定電圧電源回路部2、電源選択回路部3、スイッチ
群4及び機能回路ブロック5から構成される。前記入力
クロック周波数検出回路部1は、入力クロックCLII
Iにより、クロック周波数のディジタル情報Q1〜Qn
を出力する。FIG. 1 is a basic block diagram of an integrated circuit device according to an embodiment of the present invention. This configuration includes an input clock frequency detection circuit section 1, a constant voltage power supply circuit section 2, a power supply selection circuit section 3, a switch group 4, and a functional circuit block 5. The input clock frequency detection circuit section 1 has an input clock CLII.
By I, digital information Q1 to Qn of clock frequency
Output.
定電圧電源回路部2は、外部電源人力VDDより低電圧
のm個の固定電圧v1〜’Irnを発生させる。電源選
択回路部3は、クロック周波数のディジタル情報Q1〜
Qnよシ、電源選択出力81〜amを出力する。スイッ
チ群4は、電源選択出力81〜Smにより、定電圧群v
1〜Vmから1つの電圧Vt+nsを選択し、この電圧
VDINを機能回路ブロック6に供給する。同図中、s
’、es%機能ブロック6に対応する別の各機能ブロッ
クであり、a/ 、3/Fならびに4′、4′もそれら
に対応する各電源選択回路部ならびにスイッチ群である
。The constant voltage power supply circuit section 2 generates m fixed voltages v1 to 'Irn that are lower voltages than the external power supply VDD. The power supply selection circuit section 3 receives digital information Q1 about clock frequencies.
Qn outputs power supply selection outputs 81 to am. The switch group 4 is connected to the constant voltage group v by the power source selection outputs 81 to Sm.
One voltage Vt+ns is selected from 1 to Vm and this voltage VDIN is supplied to the functional circuit block 6. In the same figure, s
', es% are other functional blocks corresponding to the functional block 6, and a/, 3/F, and 4', 4' are also corresponding power supply selection circuit units and switch groups.
以下、この構成と機能の詳細を各ブロック単位に分解し
て説明する。簡単化のため機能回路ブロックが1つの場
合を考え説明する。The details of this configuration and function will be explained below by breaking it down into each block. For simplicity, the explanation will be based on a case where there is only one functional circuit block.
第2図に入力クロック周波数検出回路部10回路構成を
示す。この回路は、容量Cと抵抗Rとの間にアナログス
イッチ6をはさむOR直列回路、アナログスイッチ6を
、オン、オフするD形フリップフロップ7、ゲートパル
スを形成する波形整形回路8、入力クロックをゲートす
るアンドゲート9、周波数検出周期を決める1段カウン
タ1o、ゲートされた入力クロックを計数する3段カウ
ンタ11、カウント結果を保持するn段うッチ12、ゲ
ートパルスを反転するインバータ13から構成される。FIG. 2 shows the circuit configuration of the input clock frequency detection circuit section 10. This circuit consists of an OR series circuit that sandwiches an analog switch 6 between a capacitor C and a resistor R, a D-type flip-flop 7 that turns on and off the analog switch 6, a waveform shaping circuit 8 that forms gate pulses, and an input clock. Consists of an AND gate 9 that performs gating, a one-stage counter 1o that determines the frequency detection period, a three-stage counter 11 that counts the gated input clock, an n-stage switch 12 that holds the count result, and an inverter 13 that inverts the gate pulse. be done.
D入力に外部から供給される電源Vanを接続した前記
り形フリップ70ツブ7に、外部人力クロックOL l
yr が入力されると、そのQ出力がH”となる。、7
これによシ、外部から供給される電源に接続されたOR
直列回路のOR間のアナログスイッチ6がオンされる。An external human clock OL l is connected to the flip type flip 70 knob 7 to which the power supply Van supplied from the outside is connected to the D input.
When yr is input, its Q output becomes H''.,7
This allows the OR
The analog switch 6 between the ORs of the series circuit is turned on.
すると抵抗Hの両端には、初期値を外部電源電圧VDD
とするOR0時定数を持った指数関数的減衰信号が発生
する。この信号をインバータを複数個接続した波形整形
回路8によりパルス波に波形整形し、入力クロックOL
x* ヲカウントする期間Tをもつゲートパルスとする
。第3図(a)にOR直列回路の出力、同(b)に波形
整形回路8の出力を示す。ゲートパルス幅τは、外部電
源電圧VDD 、容量C9抵抗R,インバータの入力し
きい値電圧Vs+wにょシ決まる。関係式を下に示す。Then, the initial value is set to the external power supply voltage VDD at both ends of the resistor H.
An exponentially decaying signal with an OR0 time constant is generated. This signal is shaped into a pulse wave by a waveform shaping circuit 8 that connects a plurality of inverters, and the input clock OL
Let x* be a gate pulse with a period T to be counted. FIG. 3(a) shows the output of the OR series circuit, and FIG. 3(b) shows the output of the waveform shaping circuit 8. The gate pulse width τ is determined by the external power supply voltage VDD, the capacitor C9 resistor R, and the input threshold voltage Vs+w of the inverter. The relational expression is shown below.
V+sw = VDD 6!p(−cFl )・ T
VDn
・・τY=扛T「
パルス幅Tの前記ゲートパルスにより、入力クロックO
Lxwをアンドゲート9でゲートし、3段カウンタ11
に入力し、入力クロック周波数に比例したカウンタ出力
Q1〜Qnを得る。そして、終段のカウンタ出力Qnが
′H″になると、そのコンブリメント出力Qnをアンド
ゲート9に入力し、クロック入力を禁止する。3段カウ
ンタ11の出力Q1〜Qnをn段うッチ回路12で、ゲ
ートパルスの立ち下がりエツジに同期して記憶する。以
上の動作を入力クロック0Lxxで動作する1段カウン
タ1o(n>n)の出力信号Qeを、それぞれOR間の
アナログスイッチ6をオン、オフするD形フリップフロ
ップ7および3段カウンタ11の各リセット入力端子に
加えて周期To (ただし、To = tOX2’ 、
to :入力クロック周期)で繰シ返す。V+sw=VDD 6! p(-cFl)・T
VDn...τY=T' The gate pulse with pulse width T causes the input clock O
Gate Lxw with AND gate 9, 3-stage counter 11
to obtain counter outputs Q1 to Qn proportional to the input clock frequency. When the final stage counter output Qn becomes 'H', the concomitant output Qn is input to the AND gate 9 and clock input is inhibited. 12, it is stored in synchronization with the falling edge of the gate pulse.The above operation is performed by turning on the analog switch 6 between the respective ORs of the output signal Qe of the one-stage counter 1o (n>n) that operates with the input clock 0Lxx. , in addition to each reset input terminal of the D-type flip-flop 7 and the three-stage counter 11 to be turned off, the period To (however, To = tOX2',
to: input clock period).
第4図に定電圧電源回路部20回路構成例を示す。m個
のIC/XC/X型中ンネルMOSインバータで、それ
らの各MO8)ランジスタTrの入力端子14をグラン
ドレベルにし、第1段の電源は外部入力電源VIIDに
接続し、第2段以降の各段の電源はそれぞれ各前段の出
力と接続した構成とする。これにより、1段目のvlに
は、V1=VDI1
2段目以−降には、基板バイアス効果の影響が小さい場
合、
Vi#Vnn−isVy (L=1.2.・−、rn
−1)Vテ:Kln−チャンネルMOSトランジスタT
rのしきい値電圧
の電圧が得られる。こうして前記機能回路ブロック5.
5’、5’の各電源ラインには、最高動作周波数時はV
DDとし、動作周波数が低くなるにつれて、電圧値を順
次に下げて供給する。電源選択回路部3はMOS・アナ
ログスイッチの組合せで構成し、定電圧電源回路部2か
らの各出力電圧と各機能回路ブロック5.5’、5’と
を接続するアナログスイッチの内から、入力クロック周
波数検出回路のカウンタ出力Q1〜Qnにより論理ゲー
トで、動作電圧を1つ選択して、その動作電圧を供給し
得る上記アナログスイッチをオンとし、他は全てオフと
する構成とする。FIG. 4 shows an example of the circuit configuration of the constant voltage power supply circuit section 20. m IC/XC/X type medium channel MOS inverters, the input terminal 14 of each MO8) transistor Tr is set to ground level, the first stage power supply is connected to the external input power supply VIID, and the second stage and subsequent stages The power supply of each stage is connected to the output of each previous stage. As a result, in the first stage vl, V1=VDI1, and in the second and subsequent stages, when the influence of the substrate bias effect is small, Vi#Vnn-isVy (L=1.2.-, rn
-1) Vte: Kln-channel MOS transistor T
A voltage of the threshold voltage of r is obtained. In this way, the functional circuit block 5.
Each power supply line 5' and 5' has V at the maximum operating frequency.
DD, and as the operating frequency becomes lower, the voltage value is sequentially lowered and supplied. The power supply selection circuit section 3 is composed of a combination of MOS/analog switches, and selects an input from among the analog switches that connect each output voltage from the constant voltage power supply circuit section 2 and each functional circuit block 5.5', 5'. The configuration is such that a logic gate selects one operating voltage based on the counter outputs Q1 to Qn of the clock frequency detection circuit, turns on the analog switch capable of supplying that operating voltage, and turns off all others.
第6図に本発明について、その一系統を示す詳細な回路
図である。入力クロック周波数検出回路部1は、アンド
ゲート9でゲートされた入力クロックを7段カウンタ1
1で最大64個カウントし、Q1〜Q7を出力し、7段
ラッチ回路12で記憶する。また、10段カウンタ10
によシ、入力クロックを210個カウントするごとに、
この動作を繰り返す。定電圧電源回路部2は、K/に型
n−チャネルMOSインバータ2個により、1段目の電
源にVDD、1段目の出力にVtID−Vy、2段目の
出力にVDD−2V丁の各電圧を得る。電源選択回路部
3とスイッチ群4は、4人カッアゲート16.2人カッ
アゲート16、アナログスイッチ81,82゜S3の3
個で構成し、入力クロックカウント数が0〜7個で動作
電圧をvnn−2vyに選択し、8〜63個テVDD−
VT、64個テvDDヲ選択スル。第6図は第6図図示
回路の動作タイミングチャートであり、各入力クロック
数Nにおける入力クロック周波数検出回路部1の出力Q
sQ5*Q6sQ’H電源選択回路部3の出力S1,8
2.Ss、及びその時に選択される機能回路ブロック6
への動作電圧を表す。ここで、入力クロック数を入力ク
ロック周波数に置きかえるためゲートパルス幅Tを20
μ1llecにとれば機能回路ブロックの最適動作電圧
はそれぞれ4001H1未満ではV3=VDD−2Vt
。FIG. 6 is a detailed circuit diagram showing one system of the present invention. The input clock frequency detection circuit section 1 converts the input clock gated by the AND gate 9 into a 7-stage counter 1.
1 counts up to 64 pieces, outputs Q1 to Q7, and stores them in the 7-stage latch circuit 12. In addition, a 10-stage counter 10
By the way, every time we count 210 input clocks,
Repeat this action. The constant voltage power supply circuit section 2 uses two K/type n-channel MOS inverters to supply VDD to the first stage power supply, VtID-Vy to the first stage output, and VDD-2Vt to the second stage output. Obtain each voltage. The power supply selection circuit section 3 and the switch group 4 include a 4-person cutter gate 16, a 2-person cutter gate 16, and 3 analog switches 81 and 82°S3.
The input clock count number is 0 to 7, the operating voltage is selected to vnn-2vy, and the input clock count is 0 to 7.
VT, select 64 te vDD. FIG. 6 is an operation timing chart of the circuit shown in FIG.
sQ5*Q6sQ'H Output S1, 8 of power supply selection circuit section 3
2. Ss and the functional circuit block 6 selected at that time
represents the operating voltage. Here, in order to replace the number of input clocks with the input clock frequency, the gate pulse width T is set to 20
If we take μ1llec, the optimal operating voltage of each functional circuit block is V3=VDD-2Vt below 4001H1.
.
400 KHz以上3.2MHz未満でV2 =VD1
1−Vt 。V2 = VD1 at 400 KHz or more and less than 3.2 MHz
1-Vt.
3.2MHz以上テv1=vDDトナル。3.2MHz or higher tev1 = vDD tonal.
以上のように本発明は、入力クロック周波数を検知する
ことにより、機能ブロック回路の動作速度を知り、機能
回路ブロックの動作電圧を、たとえば低速動作時は低電
圧にと、各動作速度にあわせて、それぞれ最適な動作電
圧に設定することができるのて、集積回路装置の低消費
電力イヒに大きな効果をもへらす。 5.、−
尚、以上の説明i:相補!MO5集積回路に好適な回路
例4につい、て行なったが一般の半導体集積回路に′℃
ても適用可能であることはもちろんである。 。As described above, the present invention detects the input clock frequency to know the operating speed of the functional block circuit, and adjusts the operating voltage of the functional circuit block to a low voltage during low-speed operation, for example, according to each operating speed. , each can be set to the optimum operating voltage, which has a great effect on reducing the power consumption of the integrated circuit device. 5. , - Furthermore, the above explanation i: Complementary! Regarding circuit example 4 suitable for MO5 integrated circuit, we conducted a circuit example 4 which is suitable for MO5 integrated circuit.
Of course, it is also applicable to any .
第1図は、本発明に係る集積回路装置のブロック図、第
2図は入力クロック検出回路図、第3図は入力クロック
検出回路で、ゲートパルス形成過程における各部出力を
示す図で、同図(&)はCR直列回路出力波形図、同図
(b)は波形整形インバータある。
1・・・・・・入力クロック周波数検出回路部、2・・
・・・・定電圧電源回路部% 3 e 3’ + 3”
・・・・・・電源選択回路部、4.4’、4“・・・・
・・スイッチ群 6 、5/ 、 5//・・・・・・
機能回路ブロック、6・・・・・・アナログスイッチ、
7・・・・・・D型フリップフロップ、8・・・・・・
波形整形回路%9・・・・・・アンドゲート、10.1
1・・・・・・カウンタ、12・・・・・・ラッチ、1
3・・・・・・インバータ、CL工・・・・・・外部人
力クロック、V1.V2・・・・・・Vm・・・・・・
定電圧電源回路出力、Ql、Q2・・・・・・Qn・・
・・・・入カク。2□ff1i!i*Ifl[IM[]
、S 1 、 S 2−’−11,−Sm 0.−・・
・電源選択回路出力。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図
第3図
(αl (bJ
第4図
@5図FIG. 1 is a block diagram of an integrated circuit device according to the present invention, FIG. 2 is a diagram of an input clock detection circuit, and FIG. 3 is a diagram of an input clock detection circuit, showing the output of each part in the gate pulse forming process. (&) is a CR series circuit output waveform diagram, and the figure (b) is a waveform shaping inverter. 1... Input clock frequency detection circuit section, 2...
... Constant voltage power supply circuit section % 3 e 3' + 3"
...Power selection circuit section, 4.4', 4"...
...Switch group 6, 5/, 5//...
Functional circuit block, 6...analog switch,
7...D type flip-flop, 8...
Waveform shaping circuit %9...And gate, 10.1
1...Counter, 12...Latch, 1
3... Inverter, CL engineer... External manual clock, V1. V2...Vm...
Constant voltage power supply circuit output, Ql, Q2...Qn...
...Enter. 2□ff1i! i*Ifl[IM[]
, S 1 , S 2-'-11, -Sm 0. −・・
・Power supply selection circuit output. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 (αl (bJ Figure 4 @ Figure 5
Claims (2)
波数検出回路と、2種類以上の定電圧を発生する定電圧
電源回路と、前記周波数検出回路の出力に応じて前記定
電圧電源回路出力を適宜選択して所定電圧を機能回路に
供給する電源選択回路とを有することを特徴とする集積
回路装置0(1) A frequency detection circuit that detects a clock frequency input from the outside, a constant voltage power supply circuit that generates two or more types of constant voltages, and an output of the constant voltage power supply circuit as appropriate according to the output of the frequency detection circuit. An integrated circuit device 0 characterized in that it has a power supply selection circuit that selects and supplies a predetermined voltage to a functional circuit.
ウンタにより外部クロックを計数し、順次カウンタ出力
を得ることを特徴とする特許請求の範囲第1項記載の集
積回路装置。(2) The integrated circuit device according to claim 1, wherein the frequency detection circuit has a multi-stage counter, the counter counts an external clock, and sequentially obtains a counter output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57054288A JPS58171842A (en) | 1982-03-31 | 1982-03-31 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57054288A JPS58171842A (en) | 1982-03-31 | 1982-03-31 | Integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58171842A true JPS58171842A (en) | 1983-10-08 |
Family
ID=12966372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57054288A Pending JPS58171842A (en) | 1982-03-31 | 1982-03-31 | Integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58171842A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62232155A (en) * | 1986-04-01 | 1987-10-12 | Toshiba Corp | Semiconductor integrate circuit device |
JPH01164060A (en) * | 1987-12-21 | 1989-06-28 | Hitachi Ltd | Semiconductor device |
JPH03241403A (en) * | 1990-02-20 | 1991-10-28 | Canon Inc | Electronic equipment |
FR2690768A1 (en) * | 1992-04-30 | 1993-11-05 | Innovatron Sa | Data exchange between smart card and reader with adaptive voltage supply - uses low voltage on card with capability to accept higher voltage supply from reader if it is available |
EP0675425A3 (en) * | 1989-06-30 | 1995-11-29 | Fujitsu Personal Syst Inc | A method for reducing power consumed by a computer. |
US5889429A (en) * | 1996-01-22 | 1999-03-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and semiconductor integrated circuit device |
US5903513A (en) * | 1997-03-26 | 1999-05-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device with clock frequency invariant voltage step-down circuit |
EP1008923A1 (en) * | 1996-09-25 | 2000-06-14 | Matsushita Electric Industrial Co., Ltd. | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characterictics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input/output characteristics of frequency-volt |
WO2003036722A1 (en) * | 2001-10-26 | 2003-05-01 | Fujitsu Limited | Semiconductor integrated circuit device, electronic device having the circuit device packaged therein, and power consumption reducing method |
WO2005125012A1 (en) * | 2004-06-15 | 2005-12-29 | Koninklijke Philips Electronics N.V. | Adaptive control of power supply for integrated circuits |
US7149184B2 (en) | 2001-01-26 | 2006-12-12 | Fujitsu Limited | Transmission rate monitoring apparatus and method |
US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
US10020799B2 (en) | 2016-05-09 | 2018-07-10 | Renesas Electronics Corporation | Semiconductor integrated circuit |
-
1982
- 1982-03-31 JP JP57054288A patent/JPS58171842A/en active Pending
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS62232155A (en) * | 1986-04-01 | 1987-10-12 | Toshiba Corp | Semiconductor integrate circuit device |
JPH01164060A (en) * | 1987-12-21 | 1989-06-28 | Hitachi Ltd | Semiconductor device |
EP0675425A3 (en) * | 1989-06-30 | 1995-11-29 | Fujitsu Personal Syst Inc | A method for reducing power consumed by a computer. |
EP0749060A1 (en) * | 1989-06-30 | 1996-12-18 | Fujitsu Personal Systems, Inc. | A clock system |
JPH03241403A (en) * | 1990-02-20 | 1991-10-28 | Canon Inc | Electronic equipment |
FR2690768A1 (en) * | 1992-04-30 | 1993-11-05 | Innovatron Sa | Data exchange between smart card and reader with adaptive voltage supply - uses low voltage on card with capability to accept higher voltage supply from reader if it is available |
US5889429A (en) * | 1996-01-22 | 1999-03-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and semiconductor integrated circuit device |
EP1008923A4 (en) * | 1996-09-25 | 2009-09-09 | Panasonic Corp | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characterictics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input/output characteristics of frequency-volt |
US6424184B1 (en) | 1996-09-25 | 2002-07-23 | Matsushita Electric Industrial Co., Ltd. | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characteristics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input |
EP1008923A1 (en) * | 1996-09-25 | 2000-06-14 | Matsushita Electric Industrial Co., Ltd. | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characterictics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input/output characteristics of frequency-volt |
DE19748031B4 (en) * | 1997-03-26 | 2004-08-05 | Mitsubishi Denki K.K. | Integrated semiconductor circuit device with a clock frequency invariant voltage step-down circuit |
US5903513A (en) * | 1997-03-26 | 1999-05-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device with clock frequency invariant voltage step-down circuit |
US7900067B2 (en) | 1997-06-27 | 2011-03-01 | Broadcom Corporation | Battery powered device with dynamic and performance management |
US8504852B2 (en) | 1997-06-27 | 2013-08-06 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
US7149184B2 (en) | 2001-01-26 | 2006-12-12 | Fujitsu Limited | Transmission rate monitoring apparatus and method |
WO2003036722A1 (en) * | 2001-10-26 | 2003-05-01 | Fujitsu Limited | Semiconductor integrated circuit device, electronic device having the circuit device packaged therein, and power consumption reducing method |
US7302598B2 (en) | 2001-10-26 | 2007-11-27 | Fujitsu Limited | Apparatus to reduce the internal frequency of an integrated circuit by detecting a drop in the voltage and frequency |
US7320079B2 (en) | 2001-10-26 | 2008-01-15 | Fujitsu Limited | Semiconductor integrated circuit device, an electronic apparatus including the device, and a power consumption reduction method |
JP2008503084A (en) * | 2004-06-15 | 2008-01-31 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Adaptive control of power supplies for integrated circuits. |
US8120410B2 (en) | 2004-06-15 | 2012-02-21 | St-Ericsson Sa | Adaptive control of power supply for integrated circuits |
WO2005125012A1 (en) * | 2004-06-15 | 2005-12-29 | Koninklijke Philips Electronics N.V. | Adaptive control of power supply for integrated circuits |
US10020799B2 (en) | 2016-05-09 | 2018-07-10 | Renesas Electronics Corporation | Semiconductor integrated circuit |
US10361683B2 (en) | 2016-05-09 | 2019-07-23 | Renesas Electronics Corporation | Semiconductor integrated circuit |
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