JPS58114453A - Liquid-crystal display device - Google Patents
Liquid-crystal display deviceInfo
- Publication number
- JPS58114453A JPS58114453A JP21404281A JP21404281A JPS58114453A JP S58114453 A JPS58114453 A JP S58114453A JP 21404281 A JP21404281 A JP 21404281A JP 21404281 A JP21404281 A JP 21404281A JP S58114453 A JPS58114453 A JP S58114453A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- drain
- liquid crystal
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 18
- 239000011159 matrix material Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910001120 nichrome Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 24
- 229910052697 platinum Inorganic materials 0.000 description 12
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 241000600169 Maro Species 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は液晶と薄膜トランジスタマトリックスアレイと
から成る液晶表示装置に係り、特に表示画面のコント2
ストの向上に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a liquid crystal display device comprising a liquid crystal and a thin film transistor matrix array, and particularly relates to a display screen control device.
Regarding improvement of strikes.
(2)技術の背景
M1図は薄膜トランジスタマトリックスプレイを宮む液
晶表示装置を示す平面図であり、X選択線1とY選択線
2によりて薄膜トランジスタ3と液晶駆動電極4の対を
マトリックス状に配列している。第2図は第1図のA
−A ’断面図であり、薄膜トランジスタはガラス基板
5上にゲートに&6とゲート絶縁膜7と7モーフアスシ
リコン族8とソース電極9とドレイン11L極10とパ
ッジベーン田ン膜11と遮光膜12とを積層して構成さ
れ、ゲート電極6はX洒択線1と接続され、ソース電極
9はY選択線2と接続され、ドレイン電極10は液晶駆
動電極4ζ接続されている。−万、他のガラス基板5上
には透明電極15がコーテングされ、この透明電極15
と液晶駆動電極4とが狭い平行なギャップを持つて対向
するように両ガラス基板5および14は組み合せられる
。前記狭い平行なギャップに液晶17が充填され、液晶
表示装置が形成される。なお、第2図の13と16は液
晶を配向させるためのポリイミド談たはポリビニールア
ルコールの皮膜であり、一つの液晶駆動電極が一つの画
素に対応している。(2) Background of the technology Figure M1 is a plan view showing a liquid crystal display device with a thin film transistor matrix play, in which pairs of thin film transistors 3 and liquid crystal drive electrodes 4 are arranged in a matrix by X selection lines 1 and Y selection lines 2. are doing. Figure 2 is A of Figure 1.
-A' is a sectional view, and the thin film transistor has a gate on a glass substrate 5, a gate insulating film 7, a morphous silicon group 8, a source electrode 9, a drain 11, an L pole 10, a pudge vane film 11, and a light shielding film 12. The gate electrode 6 is connected to the X selection line 1, the source electrode 9 is connected to the Y selection line 2, and the drain electrode 10 is connected to the liquid crystal drive electrode 4ζ. - 10,000, a transparent electrode 15 is coated on the other glass substrate 5, and this transparent electrode 15
Both glass substrates 5 and 14 are combined so that the liquid crystal drive electrodes 4 and 4 face each other with a narrow parallel gap. The narrow parallel gap is filled with liquid crystal 17 to form a liquid crystal display. Note that 13 and 16 in FIG. 2 are polyimide or polyvinyl alcohol films for orienting the liquid crystal, and one liquid crystal drive electrode corresponds to one pixel.
以上は従来知られている薄膜トランジスタマトリックス
プレイを含む代表的な液晶表示装置の構底を喫明したも
のであるが、本構成の一1i11素について一気的等価
回路を描けば第3図のようになる。The above is a clarification of the basic structure of a typical liquid crystal display device including a conventionally known thin film transistor matrix display, but if we draw an equivalent circuit for 11i11 elements of this configuration at once, it will be as shown in Figure 3. Become.
同図で1.2.および3はそれぞれ前述のX選択線、X
選択線、および薄膜トランジスタであり、CおよびR′
は液晶17を充填した時の液晶駆動電極4と透明電極1
5の間の静電容量および漏洩抵抗である。18はX選択
線またはX選択線を駆動するためのパルス電源であり、
lは靜電容1kcに蓄えられた電荷がOFF状態の1l
jl)ランジスタのドレインおよびソースを通りて放電
するときの放′l1ILIt流である。放電電流は正し
くは液晶の漏洩抵抗R′およびゲート絶縁属の漏洩抵抗
によりても流れるが、その値は前記放′に電流工に比べ
てきわめて小さいのでここでは省略して考える。In the same figure, 1.2. and 3 are the aforementioned X selection line, X
selection line, and thin film transistor, C and R'
are the liquid crystal drive electrode 4 and transparent electrode 1 when filled with liquid crystal 17
The capacitance and leakage resistance between 5 and 5. 18 is an X selection line or a pulse power source for driving the X selection line;
l is 1l when the charge stored in the static capacity 1kc is in the OFF state
jl) is the radiation 'l1ILIt current when discharging through the drain and source of the transistor. The discharge current also flows due to the leakage resistance R' of the liquid crystal and the leakage resistance R' of the gate insulating metal, but their values are extremely small compared to the discharge current, so their discussion will be omitted here.
以上のような薄膜トランジスタマトリックスアレイを宮
む液晶表示装置においては多数のX:s折線と多数のY
−s折線を順次切り換え、多数の画素を画面の一端から
他端までスキャンユングして一1面を表示Tる方式が採
用されている。この方式の場合、ある画素は他の画素が
選択されているとき通常駆動されていない。したがりて
そのkgはItイ1hO)スキャンユングが終って次の
画面の駆動まで何らかの手段によりて表示を保持してい
ないと画面のコントラストの低下が生ずることになる。In a liquid crystal display device including a thin film transistor matrix array as described above, there are many X:s fold lines and many Y
A method is adopted in which the -s fold lines are sequentially switched and a large number of pixels are scanned from one end of the screen to the other to display an entire screen. In this scheme, some pixels are normally not driven when other pixels are selected. Therefore, if the display is not maintained by some means after scanning is completed until the next screen is driven, the contrast of the screen will deteriorate.
この保持手段として前述の静電容量C(#!3図記載)
に蓄えられた電荷を利用する方式が知られている。ただ
しこの電荷は前述の放電電流工によりて徐々lこ減少し
て行くので、放電の時定数ORと1サイクルのスキャン
ユング時間Tとの間には次のような関係が必要である。As this holding means, the above-mentioned capacitance C (#!3 shown in figure)
A method is known that utilizes the electric charge stored in However, since this charge is gradually reduced by the above-mentioned discharge current process, the following relationship is required between the discharge time constant OR and the scanning time T of one cycle.
OR≧T
ここでCは前述の静電容量で、Bは放電電流Iが流れる
径路の電気抵抗で、換言すれば薄膜トランジスタのOF
F時のソース・ドレイン間抵抗ROFFに略一致する。OR≧T Here, C is the capacitance mentioned above, and B is the electrical resistance of the path through which the discharge current I flows, in other words, the OF of the thin film transistor
It approximately matches the source-drain resistance ROFF at F.
したがって1秒間50コマのjiii面で表示するとす
ればTは20m5となり、液晶駆動電極の大きさを20
0μmX200μm1電極間ギャップを10μmとすれ
ば0は約0.4PFとなるのでRoyyは5X10I0
Ω以上を必要とする。Therefore, if 50 frames per second are displayed on the jiii screen, T will be 20 m5, and the size of the liquid crystal drive electrode will be 20
0μmX200μm1 If the inter-electrode gap is 10μm, 0 is approximately 0.4PF, so Royy is 5X10I0
Ω or more is required.
(段 従来技術の間辿点
第4因はソース・ドレイン間電圧V抑をIOVとしたと
きのゲート電圧Voに対するソース・ドレイン間抵抗の
変化4I性の一実例である。ゲート電圧VGが零のとき
の値が前述のRoyyであり、同図の斜線で示した範囲
は特性のバラツキを示している。本図で判る通りゲート
電圧Voが高いとき、即ちトランジスタがONのときの
ソース・ドレイン間抵抗にはバラツキは殆どないか、O
FFめときには非常に大きなバラツキがあり、実際問題
として前述のような5X10100以上の値を再現性良
く達成することは極めて困難である。門た、放電の時定
数CI−Lの条件式から判る通り、静電容量Cを大きく
する方法が考えられ、その手段として各−床内(ど薄膜
コンデンサを付加する方法が考えられるが、この場合に
は液晶表示装置の構造を複雑とし、特性の良い薄膜コン
デンサを得ることは前述のRoyyを再現性良く高める
場合と同様極めて困難である。(Step 4) The fourth factor in the prior art is an example of the change in the source-drain resistance with respect to the gate voltage Vo when the source-drain voltage V suppression is IOV.When the gate voltage VG is zero, The value when the gate voltage Vo is high, that is, when the transistor is ON, is the value between the source and drain. There is almost no variation in resistance, O
There is a very large variation when it comes to FF, and as a practical matter, it is extremely difficult to achieve the above-mentioned value of 5×10100 or more with good reproducibility. As can be seen from the conditional expression for the discharge time constant CI-L, there is a way to increase the capacitance C, and one possible way to do this is to add a thin film capacitor in each floor. In some cases, the structure of the liquid crystal display device becomes complicated, and it is extremely difficult to obtain a thin film capacitor with good characteristics, as in the case of improving Royy with good reproducibility.
(4)発明の目的
不発明の目的は前述のようなOFF時のソース・ドレイ
ン間抵抗ROFFにバラツキがあっても各画素内に薄膜
コンデンサを付加するような困難な手段を採らずに前述
の放電時定数に対する条件を満足させ、画面のコントラ
スト低下を防止する手段を液晶表示装置内に構すること
にある。(4) Purpose of the invention The purpose of the invention is that even if there is variation in the source-drain resistance ROFF during OFF as described above, the above-mentioned The object of the present invention is to provide a means within the liquid crystal display device that satisfies the conditions for the discharge time constant and prevents a decrease in screen contrast.
(5)発明の構成
本発明は放1llcit淀工の径路内にその電流工に対
しては逆方向となるシ盲ットキー障壁を設け、OFF時
のソース・ドレイン間抵抗にシ曹ットキー障壁の逆方向
抵抗が加算されるようにし、前記放電時定数ORの抵抗
Rを増加させ、目的を達成しようとするものである。具
体的にはパルス電源18(#g3図記載)が負パルスを
発生するときはアモーファアスシリコン膜とドレイン電
極の間にシ璽ットキー障壁を形成し、正パルスを発生す
るときはアモーファスシリコンル6とソース電極の間に
シ璽ットキー障壁を形成する。この71ツトキー障壁は
アモーファスシリコン膜とアルミニウム等のソースまた
はドレイン電極との間に白金または金等の薄膜を挿入し
て形成するか、または、その電極自体を白金または金と
することによりて形成する。(5) Structure of the Invention The present invention provides a blind lattice barrier which is in the opposite direction to the current flow in the path of the current flow, and the resistance between the source and drain when OFF is set to The objective is to be achieved by adding directional resistance and increasing the resistance R of the discharge time constant OR. Specifically, when the pulse power supply 18 (illustrated in figure #g3) generates a negative pulse, an amorphous silicon barrier is formed between the amorphous silicon film and the drain electrode, and when a positive pulse is generated, an amorphous silicon barrier is formed between the amorphous silicon film and the drain electrode. A shield barrier is formed between the gate electrode 6 and the source electrode. This 71 key barrier is formed by inserting a thin film of platinum or gold between the amorphous silicon film and a source or drain electrode such as aluminum, or by making the electrode itself platinum or gold. do.
(6)発明の実施例
第5図は負パルス駆動でアモーファスシリコン膜8とド
レイン電極10との間にシ1ットキー障壁を形成する場
合の一実施例を示す図である。まず、ガラス基板5上に
Ni0rを約100dX空蒸着し、パターンユングして
グー)IE電極を形成し、次にSin、を約aoooX
とアモーファスシリコンを約500 OA連続してプラ
ズマOVD法により被着し、一括してバターニングし、
ゲート絶縁膜7と7モ一フアスシリコンM8を形成する
。次に白金を約100dX空蒸着し、パターンユングし
てシ1ットキー障壁用白金膜19を形成する・次にAノ
を約2oooX真空蒸着し、パターン=yグしてソース
電極9、ドレイン電極10.Y選択線2、および液晶駆
動電極4を形成する。次に8i0またはSin、を50
0OA−1,am真空蒸着し、パターンユングしてパッ
ジベージ謬ンjlll’)形ETる。最後にNi0rを
約100OA真空蒸着し、パターンユングして遮光膜1
2を形成する・最後の遮光膜は外部の光によってアモー
ファスシリコン膜の電気抵抗が変動するのを防ぐためで
ある。なお、ソース・ドレイン間距離は30xmxンー
スおよびドレイン電極の幅は200−m1液晶駆動電極
の大きさは200μmX200Amである。vEG図は
本実施例の電気的等価開路であり、第3図の等価回路に
比べてシ璽F)〒−ダイオード20が付加された点、パ
ルス電源18が負パルスを発生する点、および放電電流
工等の電流が逆向きである点以外は同一である。ji7
図は第8図(1)のようにガラス基板5上に真空蒸着に
より約2000ムのTa (M。(6) Embodiment of the Invention FIG. 5 shows an embodiment in which a Schittky barrier is formed between the amorphous silicon film 8 and the drain electrode 10 by negative pulse driving. First, Ni0r is vapor-deposited at about 100 dX on the glass substrate 5, patterned to form an IE electrode, and then Sin is deposited at about 100 dX.
Approximately 500 OA of amorphous silicon was continuously deposited using the plasma OVD method, and then buttered all at once.
A gate insulating film 7 and a 7-morphous silicon M8 are formed. Next, platinum is vacuum-deposited at about 100 dX, and patterned to form a platinum film 19 for the Schitt key barrier.Next, A is vacuum-deposited at about 200X, and the pattern is y-g, source electrode 9 and drain electrode 10. .. A Y selection line 2 and a liquid crystal drive electrode 4 are formed. Next, 8i0 or Sin, 50
0OA-1, am vacuum evaporated, patterned and patterned. Finally, about 100OA of Ni0r is vacuum-deposited and patterned to form a light-shielding film 1.
The purpose of the last light shielding film 2 is to prevent the electric resistance of the amorphous silicon film from changing due to external light. Note that the distance between the source and drain is 30×m×200 μm, the width of the drain electrode is 200 μm, and the size of the liquid crystal drive electrode is 200 μm×200 Am. The vEG diagram is an electrically equivalent open circuit of this example, and compared to the equivalent circuit of FIG. They are the same except that the current flowing through the electric current is in the opposite direction. ji7
As shown in FIG. 8(1), approximately 2000 μm of Ta (M) is deposited on a glass substrate 5 by vacuum evaporation.
でもよい)電極2二を形成し、その上に前記実施例と同
じプロセスによりア毫−ツァスシリコン膜8、白金31
19およびアルミエクム電極22を形成したシ璽ットキ
ーダイオードの抵抗特性である。An electrode 22 is formed thereon, and an aluminum-Tsass silicon film 8 and a platinum 31
19 and an aluminum Ecum electrode 22 are formed.
電極サイズも実施例に合せて長さ2004n% 111
0μmにし、本特性が薄膜トランジスタ上に形成された
シ1ットキー障壁の特性と同一であると見なされるよう
にしである。したがって前記実施例の特性は第4171
Jの抵抗値と本図の抵抗値を加え合せた特性と見なされ
る・本図でRfは順方向特性で、Bblは逆方向特性で
ある。したがりて薄膜トランジスタのOFF時の最小抵
抗108Ω(第4図参照)とシ1クトキーダイオードの
逆方向抵抗101!Ω以上を加えれば要求条件である5
X10”Ω以上を光分に満足する・一方液晶をスイッチ
ングするために必要な電流は前記実施例の場合的10−
’A以上であり、ソースに印加する駆動パルスをIOV
とすれは薄膜トランジスタのON抵抗とシ■ットキーダ
イオードの順方向抵抗の和は1080以下が要求される
。本実施例の場合ソース・ドレイン間′鴫圧が5V〜I
OVの間ではソース・ドレイン間抵抗は殆んど変らない
ので、第4図および第7図711)ら、ケート電圧がI
OV位でシ曹ットキーダイオードの電圧降下が1.5V
位において充分に前記要求を満足することが明らかであ
る。なお、シ冒ットキーダイオードの逆方向抵抗のバラ
ツキは薄膜トランジスタのOFF時ソース争ドレイン間
抵抗のバラツキに比べ容易に、格段に小さく出来るので
シ璽ットキーダイオードの逆方向抵抗の/<ラツキによ
る問題はない。The electrode size is also 2004n% in length according to the example.
0 μm so that this characteristic is considered to be the same as that of a Schittky barrier formed on a thin film transistor. Therefore, the characteristics of the above embodiment are as follows.
It is considered that the characteristic is the sum of the resistance value of J and the resistance value in this figure. In this figure, Rf is the forward direction characteristic and Bbl is the reverse direction characteristic. Therefore, the minimum resistance when the thin film transistor is OFF is 108Ω (see Figure 4) and the reverse resistance of the switch key diode is 101Ω! If Ω or more is added, the required condition is 5.
X10''Ω or more is satisfied for the light component.On the other hand, the current required to switch the liquid crystal is 10-Ω in the case of the above embodiment.
'A or more, and the drive pulse applied to the source is IOV
The sum of the ON resistance of the thin film transistor and the forward resistance of the Schittky diode is required to be 1080 or less. In this example, the voltage between the source and drain is 5V to I.
Since the source-drain resistance hardly changes between OV, as shown in Figures 4 and 7 (711), the gate voltage is
At around OV, the voltage drop of the Shiso-Dottky diode is 1.5V.
It is clear that the above requirements are fully satisfied in this respect. Incidentally, the variation in the reverse resistance of the Schottky diode can be easily and significantly reduced compared to the variation in the resistance between the source and the drain when the thin film transistor is OFF, so there is no problem due to the variation in the reverse resistance of the Schottky diode. There isn't.
本実施例では負パルス駆動で、シ館ットキー障壁をドレ
イン側に形成した場合を述べたが、正パルス駆動で、シ
lットΦ−障壁をソース側に形成する場合も同様なプロ
セスにより、同様な特性が得られる。また、シ1ットキ
ー障壁を7モーフアスシリコン膜とソース電極またはド
レイン電極との間に白金薄膜を挿入して形成する代りに
これら電極材料を白金で形成しても全く同様な特性が得
られる。ただしこの場合には電極である為に白金の膜厚
は2000A程直を必要とし、電極材料費が増大すると
いう欠点を持りている。また、アモーファスシリコンに
対してシ璽ットキー障壁を形成するメタルには白金の他
に金などがあり、白金に限定するものではなく、本発明
の主旨は単にシ嘗ット中−障壁を付加することにある。In this embodiment, we have described the case in which the Schitt key barrier is formed on the drain side using negative pulse driving, but a similar process can be used to form the Schitt Φ- barrier on the source side using positive pulse driving. Similar characteristics can be obtained. Further, instead of forming the Schittky barrier by inserting a platinum thin film between the 7-morphous silicon film and the source or drain electrode, the same characteristics can be obtained even if these electrode materials are made of platinum. However, in this case, since it is an electrode, the thickness of the platinum film must be approximately 2000 Å, which has the disadvantage of increasing the cost of electrode materials. In addition, metals that form a shield barrier against amorphous silicon include gold in addition to platinum, and are not limited to platinum; the gist of the present invention is simply to add a barrier during shielding. It's about doing.
また、1Ii7図におけるRhは第g a(蜀のように
、前記実施例)構造に更に約40Xの厚さの8i0.j
i[23をアモーファスシリコン膜8と白金膜19の間
に挿入した場合の逆方向抵抗特性である。このようにす
ると逆方向特性が一層改善され、効果的である。In addition, Rh in Fig. 1Ii7 is added to the ga-th structure (like Shu, in the above embodiment) with a thickness of about 40X and 8i0. j
This is the reverse resistance characteristic when i[23 is inserted between the amorphous silicon film 8 and the platinum film 19. By doing so, the reverse direction characteristics are further improved and it is effective.
なお、この場合の順方向特性は8i0.膜のない第8図
(麿ンの特性、即ち第7図Rfと殆ど変らない。Note that the forward characteristic in this case is 8i0. The characteristics of Fig. 8 (Maro) without a film, that is, the characteristics are almost the same as those of Fig. 7 Rf.
また、ここで用いた8i0*J[はTie、等の他の絶
縁膜でもよい。また、840.の膜厚は10X以下では
効果が小なく、50X以上では順方向特性が劣化して来
る。Further, 8i0*J[ used here may be other insulating films such as Tie. Also, 840. When the film thickness is less than 10X, the effect is not small, and when it is more than 50X, the forward characteristics deteriorate.
(7)発明の効果
本発FIAによれば、前述のように容易に抵抗Rを増大
させることが出来、画素の表示を一画面のスキャンユン
グの間保持することが可能となり、再現性良くコントラ
ストの向上を計ることが出来る。(7) Effects of the invention According to the FIA of the present invention, as mentioned above, it is possible to easily increase the resistance R, and it is possible to maintain the pixel display during scanning of one screen, resulting in good reproducibility and contrast. It is possible to measure the improvement in
特に本発明は解像駅を高めるために画素密度を増大させ
た場合に、前記の静電容量0が小さくなるので効果的で
ある。Particularly, the present invention is effective when the pixel density is increased in order to improve the resolution, since the above-mentioned capacitance 0 becomes small.
第1図〜第4図は従来例を示すもので、第1区はトラン
ジスタマトリックスアレイを含む液晶表示装置の平面図
、第2図は同装置の部分断面図、第3図は同装置の電気
的等価回路、第4図は同装置のソース・ドレイン間抵抗
特性である。第5図。
第6凶、第7図のRfおよびRb3、第8図(it)は
本発明の一実施例を示す図で、87図Rbい第8図(b
)は他の実施例を示す図である。ここでlはX選択線、
2はY選択線、3は薄膜トランジスタ、4は液晶駆動電
極、5および14はガラス基板、6はゲート電極、7は
ゲート絶縁膜、8はアモーファスシリコン膜、9はソー
ス電極、lOはドレイン11UIi、11はバツシベ−
り冒ンlit、 12j’[光膜、13および16はポ
リイミドatたはポリビニールアルコールJJ、15は
透明11L極、17は液晶、18はパルス電源、19は
白金膜、20はシ璽ットキーダイオード、21はTa1
l極、22は人j%極、23はSiO,ilである。
第1図
第2図
第 3図
第4−図
ケ゛−ト電LVe(vン
祁50
第6図
第7図
第8図Figures 1 to 4 show conventional examples, where the first section is a plan view of a liquid crystal display device including a transistor matrix array, the second section is a partial sectional view of the same device, and the third section is an electrical diagram of the same device. The equivalent circuit shown in FIG. 4 is the source-drain resistance characteristic of the same device. Figure 5. Figure 6, Rf and Rb3 in Figure 7, and Figure 8 (it) are diagrams showing an embodiment of the present invention;
) is a diagram showing another embodiment. Here l is the X selection line,
2 is a Y selection line, 3 is a thin film transistor, 4 is a liquid crystal drive electrode, 5 and 14 are glass substrates, 6 is a gate electrode, 7 is a gate insulating film, 8 is an amorphous silicon film, 9 is a source electrode, IO is a drain 11UIi , 11 is Batsushibe
12j' [light film, 13 and 16 are polyimide AT or polyvinyl alcohol JJ, 15 is transparent 11L pole, 17 is liquid crystal, 18 is pulse power supply, 19 is platinum film, 20 is button key Diode, 21 is Ta1
1 pole, 22 is the human j% pole, and 23 is SiO, il. Figure 1 Figure 2 Figure 3 Figure 4 - Figure 50 Figure 6 Figure 7 Figure 8
Claims (1)
よびドレイン電極を付加して成る薄膜トランジスタのマ
トリックスプレイを含む液晶表示装置において、該ソー
ス電極または該ドレイ/電極のいずれか一万の電極と該
アモーファスシリコン換との間にシ嘗ットキー障壁を設
けたことを特許とする液晶表示装置。In a liquid crystal display device including a matrix layer of a thin film transistor in which a gate electrode, a source electrode, and a drain electrode are added to an amorphous silicon film, either the source electrode or the drain/electrode has 10,000 electrodes and the amorphous silicon film. This is a liquid crystal display device with a patented feature that provides a shutter key barrier between the silicon and the liquid crystal display.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21404281A JPS58114453A (en) | 1981-12-26 | 1981-12-26 | Liquid-crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21404281A JPS58114453A (en) | 1981-12-26 | 1981-12-26 | Liquid-crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58114453A true JPS58114453A (en) | 1983-07-07 |
Family
ID=16649308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21404281A Pending JPS58114453A (en) | 1981-12-26 | 1981-12-26 | Liquid-crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58114453A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855806A (en) * | 1985-08-02 | 1989-08-08 | General Electric Company | Thin film transistor with aluminum contacts and nonaluminum metallization |
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5159416A (en) * | 1990-04-27 | 1992-10-27 | Nec Corporation | Thin-film-transistor having schottky barrier |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
JPH0774372A (en) * | 1994-03-10 | 1995-03-17 | Citizen Watch Co Ltd | Thin film diode and manufacture thereof |
JPH0774374A (en) * | 1994-03-10 | 1995-03-17 | Citizen Watch Co Ltd | Thin film diode and manufacture thereof |
-
1981
- 1981-12-26 JP JP21404281A patent/JPS58114453A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855806A (en) * | 1985-08-02 | 1989-08-08 | General Electric Company | Thin film transistor with aluminum contacts and nonaluminum metallization |
US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
US5159416A (en) * | 1990-04-27 | 1992-10-27 | Nec Corporation | Thin-film-transistor having schottky barrier |
JPH0774372A (en) * | 1994-03-10 | 1995-03-17 | Citizen Watch Co Ltd | Thin film diode and manufacture thereof |
JPH0774374A (en) * | 1994-03-10 | 1995-03-17 | Citizen Watch Co Ltd | Thin film diode and manufacture thereof |
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