JPS5758280A - Method for making memory address - Google Patents

Method for making memory address

Info

Publication number
JPS5758280A
JPS5758280A JP13327580A JP13327580A JPS5758280A JP S5758280 A JPS5758280 A JP S5758280A JP 13327580 A JP13327580 A JP 13327580A JP 13327580 A JP13327580 A JP 13327580A JP S5758280 A JPS5758280 A JP S5758280A
Authority
JP
Japan
Prior art keywords
bit
data
signal
addresses
rank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13327580A
Other languages
Japanese (ja)
Other versions
JPS6048828B2 (en
Inventor
Hirotoshi Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP13327580A priority Critical patent/JPS6048828B2/en
Publication of JPS5758280A publication Critical patent/JPS5758280A/en
Publication of JPS6048828B2 publication Critical patent/JPS6048828B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To output parallel n-bit data as 2n-bit data, by writing data in two addresses through using an address shown by one of high rank bit signal of address signals as the boundary and making a two-set time division reading on the data. CONSTITUTION:Parallel n-bit data are written in high rank addresses and low rank addresses in a memory 3 whose bits A0-Ai-1 of a memroy address signal MA are the same value and only the highest rank bit Ai differs, through a data bus 8. Since a signal S1 having sections of ''1'' and ''0'' between a read cycle CY is supplied to the highest rank bit input Bi of the input at the B-side of a selector 2 when reading is made, parallel n-bit data respectively stored in high rank addresses and low rank addresses which use the signal MA as a low rank bit address are time division output from the memory 3, while the signal MA of a micro-processor 1 shows the same value. In this way, a data bus 7 obtains parallel 2n-bit data at the next cycle CY.
JP13327580A 1980-09-25 1980-09-25 Memory addressing method Expired JPS6048828B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13327580A JPS6048828B2 (en) 1980-09-25 1980-09-25 Memory addressing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13327580A JPS6048828B2 (en) 1980-09-25 1980-09-25 Memory addressing method

Publications (2)

Publication Number Publication Date
JPS5758280A true JPS5758280A (en) 1982-04-07
JPS6048828B2 JPS6048828B2 (en) 1985-10-29

Family

ID=15100816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13327580A Expired JPS6048828B2 (en) 1980-09-25 1980-09-25 Memory addressing method

Country Status (1)

Country Link
JP (1) JPS6048828B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057456A (en) * 1983-09-08 1985-04-03 Oki Electric Ind Co Ltd Memory access device of microprocessor
JPS60117286A (en) * 1983-11-29 1985-06-24 三菱電機株式会社 Video display controller
JPS6123237A (en) * 1984-07-11 1986-01-31 Sanyo Electric Co Ltd Instruction reading method of microcomputer
JPS6292056A (en) * 1985-10-17 1987-04-27 Fujitsu Ltd Read and write control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057456A (en) * 1983-09-08 1985-04-03 Oki Electric Ind Co Ltd Memory access device of microprocessor
JPS60117286A (en) * 1983-11-29 1985-06-24 三菱電機株式会社 Video display controller
JPS6123237A (en) * 1984-07-11 1986-01-31 Sanyo Electric Co Ltd Instruction reading method of microcomputer
JPS6292056A (en) * 1985-10-17 1987-04-27 Fujitsu Ltd Read and write control system

Also Published As

Publication number Publication date
JPS6048828B2 (en) 1985-10-29

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