JPS5733497A - Memory testing system - Google Patents

Memory testing system

Info

Publication number
JPS5733497A
JPS5733497A JP10719680A JP10719680A JPS5733497A JP S5733497 A JPS5733497 A JP S5733497A JP 10719680 A JP10719680 A JP 10719680A JP 10719680 A JP10719680 A JP 10719680A JP S5733497 A JPS5733497 A JP S5733497A
Authority
JP
Japan
Prior art keywords
memories
data
bit
parts
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10719680A
Other languages
Japanese (ja)
Other versions
JPS6035695B2 (en
Inventor
Hiroshi Ishikawa
Hisao Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55107196A priority Critical patent/JPS6035695B2/en
Publication of JPS5733497A publication Critical patent/JPS5733497A/en
Publication of JPS6035695B2 publication Critical patent/JPS6035695B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To perform a test for a memory including an address system test with a low cost, by dividing a memory into >=2pts. and supplying the same address signal from the adress selecting circuits corresponding to each of the divided two memories. CONSTITUTION:Address distributing parts 5 and 6 correspond to 4-bit memories 1-0 and 1-1 obtained by dividing an 8-bit memory into two parts, and the same address data ADD1 or ADDn is supplied to the parts 5 and 6 respectively. The upper 4 bits and the lower 4 bits of an 8-bit writing data WD are written into the designated addresses of the memories 1-0 and 1-1 respectively. At the same time, a check bit formed after being supplied to a parity generating circuit 3 is written into an area 17. The data RD read out of the memories 1-0 and 1-1 are transmitted to a parity checking circuit 19 to check wheter the correct writing and reading is carried out for the data.
JP55107196A 1980-08-06 1980-08-06 Memory test method Expired JPS6035695B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55107196A JPS6035695B2 (en) 1980-08-06 1980-08-06 Memory test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55107196A JPS6035695B2 (en) 1980-08-06 1980-08-06 Memory test method

Publications (2)

Publication Number Publication Date
JPS5733497A true JPS5733497A (en) 1982-02-23
JPS6035695B2 JPS6035695B2 (en) 1985-08-16

Family

ID=14452907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55107196A Expired JPS6035695B2 (en) 1980-08-06 1980-08-06 Memory test method

Country Status (1)

Country Link
JP (1) JPS6035695B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008046979A (en) * 2006-08-18 2008-02-28 Fujitsu Ltd Memory controller and control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008046979A (en) * 2006-08-18 2008-02-28 Fujitsu Ltd Memory controller and control method

Also Published As

Publication number Publication date
JPS6035695B2 (en) 1985-08-16

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