JPS57192063A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57192063A
JPS57192063A JP56076007A JP7600781A JPS57192063A JP S57192063 A JPS57192063 A JP S57192063A JP 56076007 A JP56076007 A JP 56076007A JP 7600781 A JP7600781 A JP 7600781A JP S57192063 A JPS57192063 A JP S57192063A
Authority
JP
Japan
Prior art keywords
region
substrate
implanted
electrode
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076007A
Other languages
Japanese (ja)
Inventor
Toru Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56076007A priority Critical patent/JPS57192063A/en
Publication of JPS57192063A publication Critical patent/JPS57192063A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of photomask processes and to simplify the manufacturing processes by forming a low impurity concentration diffusing region, a first conductive type source drain region, and a second conductive type source drain region by two photomask processes. CONSTITUTION:For example, when a CMOSIC including a high voltage resisting N channel MISFET is formed, a first photoresist mask 31, which covers a gate electrode 29a of an N channel FET forming region 23, a P well region 22 having a desired width in the vicinity of the electrode 29a, and a P channel FET forming region 24, are formed. P is ion-implanted into the surface of a substrate to obtain high concentration, and a highly concentrated, P implanted region 32 is formed in the part of the surface of the P<-> well 22 which is separated from the electrode by a desired distance through a gate oxide film 28. Then the mask 31 is removed. Thereafter, a second photoresist mask 31' having a window which exposeds the region 24 on the substrate to be treated is formed. Then N is ion- implanted into the surface of the substrate to obtain the high concentration, and a highly concentrated, B implanted region 33 is formed in the N<-> type Si substrate 21.
JP56076007A 1981-05-20 1981-05-20 Manufacture of semiconductor device Pending JPS57192063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076007A JPS57192063A (en) 1981-05-20 1981-05-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076007A JPS57192063A (en) 1981-05-20 1981-05-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57192063A true JPS57192063A (en) 1982-11-26

Family

ID=13592748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076007A Pending JPS57192063A (en) 1981-05-20 1981-05-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57192063A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972759A (en) * 1982-10-20 1984-04-24 Toshiba Corp Semiconductor device and manufacture thereof
JPS59210660A (en) * 1983-02-23 1984-11-29 テキサス・インスツルメンツ・インコ−ポレイテツド Method of producing cmos device
JPS6066459A (en) * 1983-09-21 1985-04-16 Seiko Epson Corp Semiconductor device
JPS6084859A (en) * 1983-10-14 1985-05-14 Toshiba Corp Complementary type semiconductor device and manufacture thereof
EP0166167A2 (en) * 1984-05-16 1986-01-02 Hitachi, Ltd. A process for manufacturing a semiconductor device comprising p-channel and n-channel MISFETs
JPS61263258A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of cmos type semiconductor device
JPS63204769A (en) * 1987-02-20 1988-08-24 Nippon Telegr & Teleph Corp <Ntt> Thin film transistor
JPH01103166A (en) * 1987-10-15 1989-04-20 Matsushita Electric Works Ltd Power supply
JPH06295990A (en) * 1993-12-27 1994-10-21 Nippondenso Co Ltd Manufacture of complementary mis transistor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972759A (en) * 1982-10-20 1984-04-24 Toshiba Corp Semiconductor device and manufacture thereof
JPH05865B2 (en) * 1982-10-20 1993-01-06 Tokyo Shibaura Electric Co
JPH02125465A (en) * 1983-02-23 1990-05-14 Texas Instr Inc <Ti> Manufacture of cmos device
JPS59210660A (en) * 1983-02-23 1984-11-29 テキサス・インスツルメンツ・インコ−ポレイテツド Method of producing cmos device
JPS6066459A (en) * 1983-09-21 1985-04-16 Seiko Epson Corp Semiconductor device
JPH065710B2 (en) * 1983-09-21 1994-01-19 セイコーエプソン株式会社 Semiconductor device
JPS6084859A (en) * 1983-10-14 1985-05-14 Toshiba Corp Complementary type semiconductor device and manufacture thereof
EP0166167A2 (en) * 1984-05-16 1986-01-02 Hitachi, Ltd. A process for manufacturing a semiconductor device comprising p-channel and n-channel MISFETs
JPS61263258A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of cmos type semiconductor device
JPH0630390B2 (en) * 1985-05-17 1994-04-20 松下電子工業株式会社 Method for manufacturing CMOS semiconductor device
JPS63204769A (en) * 1987-02-20 1988-08-24 Nippon Telegr & Teleph Corp <Ntt> Thin film transistor
JPH01103166A (en) * 1987-10-15 1989-04-20 Matsushita Electric Works Ltd Power supply
JPH06295990A (en) * 1993-12-27 1994-10-21 Nippondenso Co Ltd Manufacture of complementary mis transistor

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