JPS57150043A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57150043A
JPS57150043A JP56033904A JP3390481A JPS57150043A JP S57150043 A JPS57150043 A JP S57150043A JP 56033904 A JP56033904 A JP 56033904A JP 3390481 A JP3390481 A JP 3390481A JP S57150043 A JPS57150043 A JP S57150043A
Authority
JP
Japan
Prior art keywords
virtual computer
memories
bit
computer
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56033904A
Other languages
Japanese (ja)
Inventor
Naoki Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56033904A priority Critical patent/JPS57150043A/en
Publication of JPS57150043A publication Critical patent/JPS57150043A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To avoid the lowering of performance for a real computer, by forming the hardware information of each virtual computer in the virtual storage region within a main storage device through an IC memory and providing a VM address register to hold the number of the virtual computer. CONSTITUTION:The 16-bit program control register IC memories 11, 12-1N form each bit of the control register, etc. of a virtual computer. The outputs of VM address registers 21-24 are used for the input of an address signal line A for each of the IC memories 11, 12-1N. When the virtual computer is switched, the value of the registers 21-24 is rewritten by a control program and according to the number of the virtual computer. Thus the bit corresponding to the number of the corresponding virtual computer of the memories 11, 12-1N is selected and delivered through output signal lines 61, 62 and 6N.
JP56033904A 1981-03-11 1981-03-11 Information processor Pending JPS57150043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56033904A JPS57150043A (en) 1981-03-11 1981-03-11 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56033904A JPS57150043A (en) 1981-03-11 1981-03-11 Information processor

Publications (1)

Publication Number Publication Date
JPS57150043A true JPS57150043A (en) 1982-09-16

Family

ID=12399500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56033904A Pending JPS57150043A (en) 1981-03-11 1981-03-11 Information processor

Country Status (1)

Country Link
JP (1) JPS57150043A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123943A (en) * 1982-12-29 1984-07-17 Fujitsu Ltd Vm assist control system
JPS62264357A (en) * 1986-02-24 1987-11-17 スインキング　マシーンズ　コーポレーション Simulation of processor addition for parallel processor array
JPH02143338A (en) * 1988-11-24 1990-06-01 Nec Corp Information processor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142841A (en) * 1977-05-19 1978-12-12 Toshiba Corp Data processor
JPS5487130A (en) * 1977-12-23 1979-07-11 Fujitsu Ltd Conventional register access system
JPS5534774A (en) * 1978-09-04 1980-03-11 Fujitsu Ltd Information processing unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142841A (en) * 1977-05-19 1978-12-12 Toshiba Corp Data processor
JPS5487130A (en) * 1977-12-23 1979-07-11 Fujitsu Ltd Conventional register access system
JPS5534774A (en) * 1978-09-04 1980-03-11 Fujitsu Ltd Information processing unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123943A (en) * 1982-12-29 1984-07-17 Fujitsu Ltd Vm assist control system
JPH0447853B2 (en) * 1982-12-29 1992-08-05 Fujitsu Ltd
JPS62264357A (en) * 1986-02-24 1987-11-17 スインキング　マシーンズ　コーポレーション Simulation of processor addition for parallel processor array
JPH02143338A (en) * 1988-11-24 1990-06-01 Nec Corp Information processor

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