JPS57141966A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57141966A
JPS57141966A JP56027542A JP2754281A JPS57141966A JP S57141966 A JPS57141966 A JP S57141966A JP 56027542 A JP56027542 A JP 56027542A JP 2754281 A JP2754281 A JP 2754281A JP S57141966 A JPS57141966 A JP S57141966A
Authority
JP
Japan
Prior art keywords
region
film
type
diffused
polycrystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56027542A
Other languages
Japanese (ja)
Inventor
Toshimoto Kodaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56027542A priority Critical patent/JPS57141966A/en
Publication of JPS57141966A publication Critical patent/JPS57141966A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid break of Al wires to be provided later on, when P type and N type impurities are diffused, by diffusing the inpurities by using PSG instead of a predeposition method, and decreasing the difference in steps at a polycrystal Si gate electrode part. CONSTITUTION:A P type region 8 is formed on an N type semiconductor substrate, a thick field oxide film 9 is deposited on the entire surface, and a transistor forming region is removed. Then, a gate electrode 11 comprising polycrystal Si is provided on the central part of the surface between the exposed substrate 7 and the region 8 through a thin gate oxide film 10. A PSG film 12 is deposited only on the region 8 in order to form an N channel MOS transistor and heat treated, P in the film 12 is diffused, and N type source and drain regions 15 are formed in the region 8 so as to hold the electrode 11. Then the entire surface is coated by a BSG film 13, B in the film 13 is likewise diffused in the substrate 7, and P type source and drain regions 14 for a P channel MOS transistor are formed.
JP56027542A 1981-02-26 1981-02-26 Manufacture of semiconductor device Pending JPS57141966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56027542A JPS57141966A (en) 1981-02-26 1981-02-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56027542A JPS57141966A (en) 1981-02-26 1981-02-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57141966A true JPS57141966A (en) 1982-09-02

Family

ID=12223967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56027542A Pending JPS57141966A (en) 1981-02-26 1981-02-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141966A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358867A (en) * 1986-08-29 1988-03-14 Sony Corp Manufacture of semiconductor device
WO1997002594A1 (en) * 1995-07-03 1997-01-23 Intel Corporation Low damage source and drain doping technique
US5897364A (en) * 1996-06-24 1999-04-27 Chartered Semiconductor Manufacturing, Ltd. Method of forming N- and P-channel transistors with shallow junctions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358867A (en) * 1986-08-29 1988-03-14 Sony Corp Manufacture of semiconductor device
WO1997002594A1 (en) * 1995-07-03 1997-01-23 Intel Corporation Low damage source and drain doping technique
US5897364A (en) * 1996-06-24 1999-04-27 Chartered Semiconductor Manufacturing, Ltd. Method of forming N- and P-channel transistors with shallow junctions

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