JPS5693197A - Control system of main memory device - Google Patents

Control system of main memory device

Info

Publication number
JPS5693197A
JPS5693197A JP17247579A JP17247579A JPS5693197A JP S5693197 A JPS5693197 A JP S5693197A JP 17247579 A JP17247579 A JP 17247579A JP 17247579 A JP17247579 A JP 17247579A JP S5693197 A JPS5693197 A JP S5693197A
Authority
JP
Japan
Prior art keywords
data
memory element
main memory
faulty
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17247579A
Other languages
Japanese (ja)
Inventor
Shinichi Kubo
Masami Ishii
Takashi Aoki
Shigeki Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17247579A priority Critical patent/JPS5693197A/en
Publication of JPS5693197A publication Critical patent/JPS5693197A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To prevent a 1-bit error from affecting a 2-bit error, by shifting all data of a faulty memory element to a substitute memory element when the prescribed fault is detected to an element which is usually used.
CONSTITUTION: When the prescribed fault is detected 13 to several memory elements of the main memory 5 which are usually used, the all data of the faulty memory elements are shifted to the substitute memory element 12. During this shift of the data, the original faulty memory element is used for reading of the data, while the same data is written to both the original faulty memory element and the substituted memory element 12. Then a control is given so as to read out the data of the element 12 after the data of the faulty memory element is shifted to the element 12.
COPYRIGHT: (C)1981,JPO&Japio
JP17247579A 1979-12-26 1979-12-26 Control system of main memory device Pending JPS5693197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17247579A JPS5693197A (en) 1979-12-26 1979-12-26 Control system of main memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17247579A JPS5693197A (en) 1979-12-26 1979-12-26 Control system of main memory device

Publications (1)

Publication Number Publication Date
JPS5693197A true JPS5693197A (en) 1981-07-28

Family

ID=15942669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17247579A Pending JPS5693197A (en) 1979-12-26 1979-12-26 Control system of main memory device

Country Status (1)

Country Link
JP (1) JPS5693197A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478346A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Alternate memory control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478346A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Alternate memory control system

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