JPS5683948A - Processing of semiconductor - Google Patents

Processing of semiconductor

Info

Publication number
JPS5683948A
JPS5683948A JP16118379A JP16118379A JPS5683948A JP S5683948 A JPS5683948 A JP S5683948A JP 16118379 A JP16118379 A JP 16118379A JP 16118379 A JP16118379 A JP 16118379A JP S5683948 A JPS5683948 A JP S5683948A
Authority
JP
Japan
Prior art keywords
base plate
gettering
layer
psg
effective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16118379A
Other languages
Japanese (ja)
Inventor
Hidenobu Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16118379A priority Critical patent/JPS5683948A/en
Publication of JPS5683948A publication Critical patent/JPS5683948A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To provide a selective gettering and improve a reliability of a semiconductor device in an effective manufacturing step by a method wherein either a semiconductor containing some impurities or its oxide layer is arranged at an opposite side of an element forming plane. CONSTITUTION:N<+> layer 6 is selectively formed on a surface of P type Si base plate 1, then oxide 7 of added impurity such as PSG etc. is formed at the back or rear surface of the base plate. With this condition, when a heat treatment is applied to the base plate, the impurity P is dispersed into the base plate 1, and the fault crystal under LOCOS oxide film 5 is absorbed and removed. It is possible to perform a gettering without masking the surface so as to disperse a solid layer and then a processing may be made at a lower temperature than that of a gas phase. Then, PSG 7 is removed at 9 and electrode 8 is attached to a surface of the element. With this arrangement, the gettering may be performed at the most effective period in the final processing step, resulting in making the most effective operation.
JP16118379A 1979-12-12 1979-12-12 Processing of semiconductor Pending JPS5683948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16118379A JPS5683948A (en) 1979-12-12 1979-12-12 Processing of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16118379A JPS5683948A (en) 1979-12-12 1979-12-12 Processing of semiconductor

Publications (1)

Publication Number Publication Date
JPS5683948A true JPS5683948A (en) 1981-07-08

Family

ID=15730157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16118379A Pending JPS5683948A (en) 1979-12-12 1979-12-12 Processing of semiconductor

Country Status (1)

Country Link
JP (1) JPS5683948A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03233935A (en) * 1990-02-08 1991-10-17 Mitsubishi Electric Corp Semiconductor substrate
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion
DE19915078A1 (en) * 1999-04-01 2000-10-12 Siemens Ag Process for processing a monocrystalline semiconductor wafer and partially processed semiconductor wafer
JP2015233146A (en) * 2015-07-15 2015-12-24 三菱電機株式会社 Semiconductor device and manufacturing method of the same
US10475663B2 (en) 2012-10-02 2019-11-12 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03233935A (en) * 1990-02-08 1991-10-17 Mitsubishi Electric Corp Semiconductor substrate
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion
DE19915078A1 (en) * 1999-04-01 2000-10-12 Siemens Ag Process for processing a monocrystalline semiconductor wafer and partially processed semiconductor wafer
US6531378B2 (en) 1999-04-01 2003-03-11 Infineon Technologies Ag Method for processing wafer by applying layer to protect the backside during a tempering step and removing contaminated portions of the layer
US10475663B2 (en) 2012-10-02 2019-11-12 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing semiconductor device
US10950461B2 (en) 2012-10-02 2021-03-16 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP2015233146A (en) * 2015-07-15 2015-12-24 三菱電機株式会社 Semiconductor device and manufacturing method of the same

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