JPS56157044A - Insulating isolation of semiconductor element - Google Patents

Insulating isolation of semiconductor element

Info

Publication number
JPS56157044A
JPS56157044A JP6065780A JP6065780A JPS56157044A JP S56157044 A JPS56157044 A JP S56157044A JP 6065780 A JP6065780 A JP 6065780A JP 6065780 A JP6065780 A JP 6065780A JP S56157044 A JPS56157044 A JP S56157044A
Authority
JP
Japan
Prior art keywords
groove
layer
silicon
substrate
buried layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6065780A
Other languages
Japanese (ja)
Inventor
Akira Sato
Yoichi Tamaoki
Tokuo Kure
Akiko Horiguchi
Masahiko Kogirima
Masahiko Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6065780A priority Critical patent/JPS56157044A/en
Publication of JPS56157044A publication Critical patent/JPS56157044A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To contrive to enhance the integration of an integrated circuit by a method wherein a groove is provided in a silicon substrate having a buried layer reaching the substrate beyond the buried layer, the inner side face and the inner bottom face of the groove are covered with an insulating oxide film, and the inside of the groove is buried with polycrystalline silicon to make it as to form an isolation region between elements. CONSTITUTION:The P type silicon substrate 1, an N<+> type buried layer 2 and an N type epitaxial layer 3 are covered with thermal oxide films 4 and photo resist films 5, and the groove 6 to form the insulating isolation region is provided by etching up to the depth reaching the substrate 1 beyond the N<+> type buried layer using the photo resist layers as the mask. A polycrytalline silicon layer 9 is formed on the inner bottom face of the groove interposing the thermal oxide film 7, an Si3N4 film 8 between them, a polycrystalline silicon layer 14 is made to grow epitaxially up to the surface of the silicon wafer using the film as a nucleus, and a thermal oxide film 15 is formed on the surface to make it to form the insulating isolation layer. Accordingly the isolation between the elements is performed eliminating the reduction of active region to be caused by lateral directional oxidation to contrive to enhance the integration of the integrated circuit.
JP6065780A 1980-05-09 1980-05-09 Insulating isolation of semiconductor element Pending JPS56157044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6065780A JPS56157044A (en) 1980-05-09 1980-05-09 Insulating isolation of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6065780A JPS56157044A (en) 1980-05-09 1980-05-09 Insulating isolation of semiconductor element

Publications (1)

Publication Number Publication Date
JPS56157044A true JPS56157044A (en) 1981-12-04

Family

ID=13148620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6065780A Pending JPS56157044A (en) 1980-05-09 1980-05-09 Insulating isolation of semiconductor element

Country Status (1)

Country Link
JP (1) JPS56157044A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0097789A2 (en) * 1982-06-30 1984-01-11 International Business Machines Corporation Method of filling trenches in semiconductor substrates with silicon
US4626317A (en) * 1985-04-03 1986-12-02 Advanced Micro Devices, Inc. Method for planarizing an isolation slot in an integrated circuit structure
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US5066609A (en) * 1988-07-25 1991-11-19 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a trench capacitor
US5108946A (en) * 1989-05-19 1992-04-28 Motorola, Inc. Method of forming planar isolation regions

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0097789A2 (en) * 1982-06-30 1984-01-11 International Business Machines Corporation Method of filling trenches in semiconductor substrates with silicon
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4626317A (en) * 1985-04-03 1986-12-02 Advanced Micro Devices, Inc. Method for planarizing an isolation slot in an integrated circuit structure
US5066609A (en) * 1988-07-25 1991-11-19 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a trench capacitor
US5108946A (en) * 1989-05-19 1992-04-28 Motorola, Inc. Method of forming planar isolation regions

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