JPS56124233A - Method for formation of platinum silicic layer - Google Patents

Method for formation of platinum silicic layer

Info

Publication number
JPS56124233A
JPS56124233A JP2898580A JP2898580A JPS56124233A JP S56124233 A JPS56124233 A JP S56124233A JP 2898580 A JP2898580 A JP 2898580A JP 2898580 A JP2898580 A JP 2898580A JP S56124233 A JPS56124233 A JP S56124233A
Authority
JP
Japan
Prior art keywords
substrate
monitor
silicic
platinum
formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2898580A
Other languages
Japanese (ja)
Inventor
Mitsuo Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2898580A priority Critical patent/JPS56124233A/en
Publication of JPS56124233A publication Critical patent/JPS56124233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to indirectly monitor the condition of formation of a silicic platinum layer by a method wherein the variation of the resistance value occurring before and after the disposition process of the platinum silicic layer having the prescribed sheet resistance value. CONSTITUTION:A B-ion is injected on the surface of an N type Si substrate, excluding an SiO2 film, an annealing is performed thereon, a heat treatment is performed in an oxidizing atmosphere, the SiO2 film on the surface is removed by etching and a monitor substrate is formed. The substrate to be used for an element is pre-treated together with the monitor substrate and a Pt is sputtered in an Ar atmosphere. After formation of the Pt film having the prescribed thickness, the Ar is shut off, evacuated and picked out after cooling. After said substrate and the monitor substrate are treated in an N2 at the temperature of 600 deg.C for about 20min, they are processed in the mixture of nitric acid, hydrochloric acid and water at the mixing ratio by volume of 1:3:4 at the temperature of 80 deg.C for about 10min and then the unnecessary Pt is removed by etching. At this stage, the SiO2 film on the monitor substrate is removed using an HF solution and the sheet resistance value of the monitor substrate is measured. If this value is appropriate, the substrate for the element, which was processed together with the monitor substrate at the same time, is considered to have nothing unusual in the silicic platinum processing. Through this constitution, an abnormal substrate can be removed.
JP2898580A 1980-03-05 1980-03-05 Method for formation of platinum silicic layer Pending JPS56124233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2898580A JPS56124233A (en) 1980-03-05 1980-03-05 Method for formation of platinum silicic layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2898580A JPS56124233A (en) 1980-03-05 1980-03-05 Method for formation of platinum silicic layer

Publications (1)

Publication Number Publication Date
JPS56124233A true JPS56124233A (en) 1981-09-29

Family

ID=12263703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2898580A Pending JPS56124233A (en) 1980-03-05 1980-03-05 Method for formation of platinum silicic layer

Country Status (1)

Country Link
JP (1) JPS56124233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322812A (en) * 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
JP2019067874A (en) * 2017-09-29 2019-04-25 マツダ株式会社 Method of manufacturing peltier device and method of packaging the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445572A (en) * 1977-09-17 1979-04-10 Sanyo Electric Co Ltd Specific resistance monitoring method of epitaxial growth

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445572A (en) * 1977-09-17 1979-04-10 Sanyo Electric Co Ltd Specific resistance monitoring method of epitaxial growth

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322812A (en) * 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
JP2019067874A (en) * 2017-09-29 2019-04-25 マツダ株式会社 Method of manufacturing peltier device and method of packaging the same

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