JPS5585030A - Forming method for electrode of semiconductor device - Google Patents

Forming method for electrode of semiconductor device

Info

Publication number
JPS5585030A
JPS5585030A JP15762278A JP15762278A JPS5585030A JP S5585030 A JPS5585030 A JP S5585030A JP 15762278 A JP15762278 A JP 15762278A JP 15762278 A JP15762278 A JP 15762278A JP S5585030 A JPS5585030 A JP S5585030A
Authority
JP
Japan
Prior art keywords
positive resist
temperature
postbaking
resist
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15762278A
Other languages
Japanese (ja)
Inventor
Toshinobu Kita
Sadatake Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15762278A priority Critical patent/JPS5585030A/en
Publication of JPS5585030A publication Critical patent/JPS5585030A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)

Abstract

PURPOSE: To provide a wiring pattern of predetermined width when photoetching an electrode layer with a positive resist layer as a mask by forming the positive resist, and postbaking it at a temperature higher than a predetermined temperature to accompany thermal deformation.
CONSTITUTION: When photoetching an electrode layer 4 provided through an insulating layer 3 on the main surface of a semiconductor substrate 1 using a positive resist film 5b, a positive resist layer is formed, it is then postbaked at higher by 10W 20°C than the postbaking temperature of the positive resist with thermal deformation, and then etched. When coating, for example, the positive resist formed at 120W135°C of postbaking temperature for 10 minutes as an etching mask, the resist is thermally deformed at 140W145°C for 8W15 minutes. Thus, a wiring pattern can be formed following after the resist pattern.
COPYRIGHT: (C)1980,JPO&Japio
JP15762278A 1978-12-22 1978-12-22 Forming method for electrode of semiconductor device Pending JPS5585030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15762278A JPS5585030A (en) 1978-12-22 1978-12-22 Forming method for electrode of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15762278A JPS5585030A (en) 1978-12-22 1978-12-22 Forming method for electrode of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5585030A true JPS5585030A (en) 1980-06-26

Family

ID=15653747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15762278A Pending JPS5585030A (en) 1978-12-22 1978-12-22 Forming method for electrode of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5585030A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205451A (en) * 2007-01-25 2008-09-04 Toppan Printing Co Ltd Thin-film transistor array and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205451A (en) * 2007-01-25 2008-09-04 Toppan Printing Co Ltd Thin-film transistor array and method of manufacturing the same

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