JPS54153541A - Control system for interruption priority - Google Patents

Control system for interruption priority

Info

Publication number
JPS54153541A
JPS54153541A JP6260278A JP6260278A JPS54153541A JP S54153541 A JPS54153541 A JP S54153541A JP 6260278 A JP6260278 A JP 6260278A JP 6260278 A JP6260278 A JP 6260278A JP S54153541 A JPS54153541 A JP S54153541A
Authority
JP
Japan
Prior art keywords
interruption
input
output unit
data transfer
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6260278A
Other languages
Japanese (ja)
Inventor
Masahiro Kawakatsu
Shigeyuki Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6260278A priority Critical patent/JPS54153541A/en
Publication of JPS54153541A publication Critical patent/JPS54153541A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To establish the control system for interruption priority, by avoiding the interruption factors of lower priority from being received entirely, even if the interruption factors having greater priority are taken place one after another.
CONSTITUTION: The input and output unit in high speed performs data transfer processing between the main memory unit 3 and it in self-contained manner with exclusive channels 5 to 8 based on the start I/O instruction from the central processing unit 1. But, the low speed input and output unit I/O is connected to the central processing unit 1 via the peripheral adaptor 2. The interruption control register 15 and the interruption control circuit 17 provided in the peripheral adaptor 2 perform interruption processing to the microprocessor 13 to the data transfer request from the input and output unit I/O, and the input and output control register 16 has a plurality of registers and contributes to the data transfer, in which the command to the input and output unit I/O, control word information and status information are set.
COPYRIGHT: (C)1979,JPO&Japio
JP6260278A 1978-05-25 1978-05-25 Control system for interruption priority Pending JPS54153541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6260278A JPS54153541A (en) 1978-05-25 1978-05-25 Control system for interruption priority

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6260278A JPS54153541A (en) 1978-05-25 1978-05-25 Control system for interruption priority

Publications (1)

Publication Number Publication Date
JPS54153541A true JPS54153541A (en) 1979-12-03

Family

ID=13205031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6260278A Pending JPS54153541A (en) 1978-05-25 1978-05-25 Control system for interruption priority

Country Status (1)

Country Link
JP (1) JPS54153541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS623344A (en) * 1985-06-28 1987-01-09 Yokogawa Hewlett Packard Ltd Interruption system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS505009A (en) * 1973-03-29 1975-01-20
JPS51109741A (en) * 1975-03-22 1976-09-28 Hitachi Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS505009A (en) * 1973-03-29 1975-01-20
JPS51109741A (en) * 1975-03-22 1976-09-28 Hitachi Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS623344A (en) * 1985-06-28 1987-01-09 Yokogawa Hewlett Packard Ltd Interruption system

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