JPH1198027A - Inverse quantization method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the computational complexity that is needed for an inverse quantizer. SOLUTION: This inverse quantizer 25 includes an address generator 29 which receives a level and an EOB(end of block) as well as the zero run length that is used for decoding the compressed data generated by quantization of each block and its following zero run length coding and variable length coding and generated by the variable length encoding of the compressed data and then generates the address of an inverse quantization table from the zero run length value, and a control circuit 35 which controls the initialization and the block processing end of the generator 29 by the signal of the EOB. Then the quantizer 25 applies the inverse quantization (multiplication of an inverse quantization coefficient and the level value) to only the data on the level corresponding to the address that is designated based on the zero run length value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Moving Picture Image Coding Experts Group) and J
PEG (Joint Photographic Coding Experts Group)
Inverse quantization method used for compressed data decoders that decode compressed bit streams of images such as zero run-length decoding (Zero Run-Length Decoding) followed by inverse quantization (Inverse Quantization) And an inverse quantizer.

[0002]

2. Description of the Related Art In systems such as image compression, techniques such as arithmetic operations such as cosine transform and compression using variable length codes are used. These arithmetic operations are realized by a hard-wired system that performs processing by connecting necessary operations in a pipeline manner, or by software (program) processing using a digital signal processor or the like. The hard-wired system has the trouble of designing various operation blocks, but has the merit that the operation frequency may be equal to the data rate since each operation can be processed in parallel. On the other hand, the program method has an advantage that various processes can be performed by a single arithmetic core, but the operating frequency is usually higher than the data rate. It should be noted that MPEG, which is an international standard, is known as image compression. MPEG is the International Standards Organization / International Electrotechnical Commission Joint Technical Committee 1 / Specialized Subcommittee 29 (ISO / IEC JTC1 / SC29 (International
al Organization for Stan-dardization / International
Electrotechnical Commission, Joint Technical Comm
It is an abbreviated name of an organization for studying moving image coding for storage of itee 1 / Sub Commitee 29 :), which is an ISO 11 standard
172 is ISO 13818 as an MPEG2 standard. In these international standards, ISO117172-1 and ISO13818-1 in the item of system multiplexing,
ISO 11172-2 and ISO 1
3818-2 is an item of voice encoding which is ISO11172
-3 and ISO13818-3 have been standardized, respectively.

FIG. 5 is a block circuit diagram showing a flow of a decoding process in an MPEG video decoder.

In FIG. 5, a bit stream 1 of an MPEG video is first subjected to header information processing by a parser 2, and a variable length code therein is converted to a variable length decoder (VL).
D) It is sent to 3 and decoded. Data 9 such as a motion vector decoded by the variable length decoder 3 is stored in a motion compensation (Motion Com
pensation: motion compensation). on the other hand,
Image data 10 decoded by the variable length decoder 3
Is sent to the processing block 11 for image calculation.

The processing block 11 for this image operation includes a zero-run length decoder (ZL) 4, a zigzag scan converter (ZZ) 5, an inverse quantizer (IQ) 6, and an inverse cosine converter (IDCT) 7. It is included. The image data 10 from the variable-length decoder 3 is composed of three pieces of information of zero run length (Run), level (Level), and end of block (End_of_Block: EOB) indicating the end of the block. It is input to the processing block 11 for image calculation. In the processing block 11, information of the zero run length (run), the level (level), and the end of block (EOB) is input to the zero run length decoder 4 and decoded, and the information of the buffer constituting the zigzag scan converter 5 Then, arithmetic operations such as inverse quantization by the inverse quantizer 6 and inverse cosine transform by the inverse cosine transformer 7 are performed.

FIG. 6 shows details of the configuration from the variable length decoder 12 (variable length decoder 3 in FIG. 5) to the inverse quantizer 20 (inverse quantizer 6 in FIG. 5).

From the variable length decoder 12, a pair of a zero run length (run) 13 and a level (level) 14 and an end of block (EOB) indicating the end of the data of the block.
15 is a zero run length decoder 16 (FIG. 5).
To the zero run length decoder 4). The zero run length decoder 16 reconstructs one block (8 × 8 pixel matrix in MPEG video) from these pieces of information.

The data 17 from the zero run length decoder 16 is sequentially written to a zigzag scan buffer 18 having a function as a zigzag scan converter (the zigzag scan converter 5 in FIG. 5). The zigzag scan buffer 18 is usually configured as a double buffer, and has a zero run length decoder 16
While writing data 17 from the other, data 19 is read from the other, and this data 19 is sent to the inverse quantizer 20.

The inverse quantizer 20 mainly includes a table of inverse quantization coefficients (an inverse quantization table: Q-table) 21 and a multiplier 22 for multiplying the coefficient of the table 21 by the data 19. The data 19 is inversely quantized. Result 23 of the inverse quantization operation by the inverse quantizer 20
Is sent to the next inverse cosine converter (inverse cosine converter 7 in FIG. 5).

Referring to the configuration shown in FIGS. 5 and 6,
The data is compressed up to the zero run length decoder 4 (16), and the number of data per pixel when decoded is smaller than 1 on average. On the other hand, since data having the same number of pixels as the number of pixels is restored by the zero run length decoder 4 (16), the processing blocks thereafter need processing capability of the same number of data as the number of pixels per screen. Therefore, the zero run length decoder 4 (1
After the decoding process in 6), a clock rate equal to or higher than the pixel data rate is required.

[0011]

By the way, in the MPEG video decoder, which is the international standard for image compression, for example, when the size of a processed image is increased, the above-mentioned hard-wired system and the above-mentioned program system can be used. It is necessary to increase the processing capability of arithmetic operations.

The main arithmetic operations in the above-mentioned MPEG video decoder include an inverse quantization operation and an inverse cosine transform operation. In particular, the pipeline operation shown in FIG. 6 is used for the inverse quantization operation. The hard-wired method requires an operation speed corresponding to the number of pixels, for example,
In high-level (High Level) processing of MPEG, a high-speed arithmetic processing circuit four to six times the main level (Main Level: ML) is required.

Accordingly, the present invention has been made in view of such a situation, and it is an object of the present invention to reduce the amount of operation required in an inverse quantizer. The operation speed of the inverse quantizer can be reduced, and the operation unit that performs the inverse quantization operation by the program method can reduce the total amount of operation, reduce the processing capacity required by the digital signal processor, and It is an object of the present invention to provide an inverse quantization method and an inverse quantizer which enable realization of a common operation with another operation in an arithmetic core.

[0014]

SUMMARY OF THE INVENTION An inverse quantization method and an inverse quantizer according to the present invention provide compressed data generated by performing quantization on a block basis, followed by zero run length coding and variable length coding. Is used when decoding the compressed data, and receives the zero run length, the level, and the end of block generated by the variable length decoding of the compressed data, and calculates the address of the inverse quantization table from the zero run length value. The above-described problem is solved by generating, controlling the initialization of address generation and the end of block processing by an end-of-block signal, and dequantizing only data at an address level designated by a value of zero run length. I do.

That is, image data has a strong correlation with adjacent pixels, and image compression is performed by utilizing this property. In this compression, data that has been quantized after cosine transform is subjected to zero-run length coding. The compression is performed by using the data such that the frequency of occurrence of “0” in the data at this stage is high, and the zero run length (the length of continuous zeros by scanning the data) and the non-zero value (level) that appears at a low frequency. This is because it is effective to take out as a pair and then perform variable length coding. Therefore,
Even in a decoder that decodes this compressed data, the data generated by the zero-run length decoder includes as much "0" data as long as appropriate compression is performed. In the process after decoding of the variable code, the DC component is subjected to a special process such as a difference operation between blocks, but the operation by the inverse quantizer is basically performed with respect to the quantization coefficient and the quantization scale for all data. And post-processing such as saturation processing and mismatch control. At this time, if the input value to the inverse quantizer is “0”, the result of the inverse quantization is also “0”.
It is. The present invention makes use of this fact to omit the calculation by the inverse quantizer for the input value corresponding to "0", and to reduce the required number of processes as a whole.

As described above, according to the present invention, when the input value is "0", the calculation is omitted,
When the total operation amount in the inverse quantizer is reduced, for example, when the hard wired method by pipeline processing is realized,
The operating speed is reduced to facilitate design, and the programming method using a digital signal processor, etc.,
The reduction of the total amount of operation enables the reduction of the operating frequency and the addition of other processing.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

The decoder to which the dequantization method and the dequantizer of the present invention are applied is, for example, a video decoder for decoding a bit stream obtained by compressing an image such as MPEG or JPEG. Zero Run-Length Decoding) and subsequent components that perform Inverse Quantization,
Inverse quantization is performed without expanding all data into blocks by the zero-run length decoder, and the amount of calculation in the inverse quantization is reduced. Further, the present invention can be applied to an MPEG high level (High Level: HL) decoder or the like that requires a higher operation performance. For example, the processing capacity of the inverse quantizer is determined by the number of pixels to be processed. The decoding process of the bit stream can be realized even in a lower case, and it is possible to decode a bit stream having a high number of pixels without speeding up or parallelizing the circuit. In the description of the present embodiment, the description will be made along the processing of an MPEG video decoder. However, the technology of the present invention is applicable to any compression system that performs quantization and zero-run length coding. It is not limited to video decoding.

The video decoder according to the embodiment of the present invention extracts the position and value of non-zero data from the information of the zero run length (run) and the level (level) which are the inputs to the zero run length decoder. In this case, only the calculation of the data is performed, and the other calculations are omitted.

FIG. 1 shows an example of an input to the zero run length decoder of the video decoder according to the present embodiment. D in the figure
Indicates a DC component, A1, A2, and A3 indicate AC components, and blanks indicate that the value is "0". The dotted arrows in the figure indicate the order of scanning. Although the example of FIG. 1 shows the case of the normal scan, the same applies to the alternate scan.

In the example of FIG. 1, in addition to the DC component (D) in the 8 × 8 block, three A1, A2 and A3 A
The case where the C component is not zero and all other components are zero is shown. At this time, the zero run length (run), the level (level), and the end of block (EOB) of the inputs to the zero run length decoder are input. Each information is as shown in FIG.

In the block shown in FIG. 1, only four of the 64 data are non-zero. Therefore, if the inverse quantization operation is performed only on these four data, the operation as a block is completed. The value of the zero run length (run) indicates the position of data in the order of scanning, and is used as an address of a coefficient table for inverse quantization and an address for writing the result of inverse quantization to a buffer. That is, in the case of the example of the block in FIG. 1, the operation of the following operation expression is performed.

[0023] In the above operation, Q [x] [y] represents a two-dimensional address of the inverse quantization coefficient table. When the address calculation of the inverse quantization table is performed in parallel, this 8 × 8
The operation of the block is completed in four steps.

In the video decoder according to the embodiment of the present invention,
As described above, only the calculation corresponding to the non-zero data of the block is performed to reduce the total calculation amount. Here, the MPEG video decoding operation has various time restrictions, and processing within this time is essential. For example, 1
The frame time is the upper limit of the decoding process for one frame or two fields. In the data-dependent processing system described above, the processing capacity and margin of the arithmetic system are determined from a statistical viewpoint. As a result of the zero run length decoding in the above example, the worst case is when all 8 × 8 data are non-zero. In such a case, the present invention is not applicable in principle. As can be seen, the actual bitstream has statistical properties that the zero run is long enough and there are many zero elements, so that the present invention can be applied. Further, how much the margin of operation is, or how to correct when the worst processing capacity is momentarily insufficient, etc., is determined by the required quality of the system.

FIG. 3 shows, as a first embodiment of the present invention, a configuration example in which an inverse quantizer which is a main configuration of a video decoder is realized by applying a hard-wired system.

In FIG. 3, a variable length decoder (VLD) 24 at the preceding stage outputs a level 28 and a zero run length 2 as three pieces of information related to an image.
7. An end-of-block (EOB) 26 is supplied, and these three pieces of information are input to input terminals (reception units) of the inverse quantizer 25, respectively. The value of the zero run length 27 is input to the address generator 29, where the level 28
The address 37 to the inverse quantization table (Q-table) 30 corresponding to is calculated.

A value (coefficient) 31 from the inverse quantization table 30 fetched based on the address 37 is multiplied by a value of a level 28 by a multiplier 32, and then a processing block for performing mismatch control or the like. 33,
This is output as the result 34 of the inverse quantization.

From the inverse quantizer 25, the information of the zero run length 27 or the inverse run length is passed through the delay buffers 38 corresponding to the number of processing stages of the inverse quantizer 25 in order to manage the address of the buffer in the next stage. The value of the address 37 of the quantization table 30 is output as the output signal 39.

On the other hand, information of the end-of-block 26 from the variable length decoder 24 is input to the control circuit 35 of the inverse quantizer 25, and the start and end of the operation for each block are managed.

FIG. 3 omits some components that are actually required for decoding the MPEG video. For example, the quantization scale factor,
Normal scan, alternate scan, intra /
Although differences such as non-intra or luminance / chrominance are not taken into account, it is obvious that a similar configuration can be realized even if these factors are included.

Next, FIG. 4 shows a processing flowchart for realizing, as a second embodiment of the present invention, an inverse quantization operation which is a main operation of a video decoder by a program method. FIG. 4 shows a case in which address calculation and data calculation are performed in parallel. FIG. 4A shows a flowchart of address calculation, and FIG. 4B shows a flowchart of data processing. I have.

In the flowchart of FIG. 4, when the calculation of a block is started in steps ST1 and ST11, first, in the address processing of FIG.
In step ST2, the address of the inverse quantization table (Q-ta
ble adress), the address of the coefficient for DC “0” (2
Dimension address Q [0] [0]) is set. On the data processing side of FIG. 4B, in step ST12, calculation of the inverse quantization of the DC component is performed. That is, this step ST12
In the calculation of the inverse quantization of the DC component in, the level of the DC component (level [0] [0]) and the address “0” of the inverse quantization table (Q [0] [0] ) Is multiplied with the coefficient value.

Next, in the address processing of FIG.
In step ST3, the address (Q-
table adress) along with the value of zero run length (run) from the variable length decoder (Q [x] [y]), and the corresponding A
The coefficient for C is read from the inverse quantization table. In the data processing of FIG. 4B, calculation of the inverse quantization of the AC component is performed in step ST13. That is, this step S
In the calculation of the inverse quantization of the AC component in T13, the relationship between the level (level [x] [y]) of the AC component and the address (Q [x] [y]) of the inverse quantization table is calculated as in the above equation. Multiplication with a numerical value is performed.

Thereafter, in steps ST4 and ST14 of FIGS. 4A and 4B, it is determined whether or not the end-of-block (EOB) information has been received from the preceding variable length decoder. If the information of ()) does not come, it returns to the processing of steps ST3 and ST13, respectively, and if the information of the end of block (EOB) comes, it proceeds to steps ST5 and ST15 and ends the processing of the block. Steps ST4 and ST1
The end of block (EOB) in 4 is implemented as an interrupt or a flag. The control of the write position of the coefficient calculated by the inverse quantization into the register or the buffer is controlled by the value of the zero run length (run).

As described above, in the video decoder according to the embodiment of the present invention, the amount of operation in the inverse quantizer can be reduced, and the operating frequency can be reduced in any of the hard wired method and the program method. Becomes possible. That is, in the data-dependent operation method as in the embodiment of the present invention, it is only necessary to perform the calculation for non-zero data only, and for those for which the result is known to be zero, the calculation is omitted to improve the operation efficiency. realizable. A similar method can be used in the inverse cosine transformer after the inverse quantization, and this is a more effective implementation method when implementing these two blocks as one block.

In addition, the present invention not only skips the processing of the data whose quantized value is "0" as described above, but also intentionally skips the calculation of the quantized value. It can be applied in any case. If the application example does not require a high-frequency component, it is possible to omit the calculation in the high band by the same processing.

[0037]

As is apparent from the above description, according to the present invention, the zero run length, the level and the end of block generated by the variable length decoding of the compressed data are received, and the inverse quantization is performed based on the zero run length value. By generating the address of the table, controlling the initialization of the address generation and the end of the block processing by the end-of-block signal, and dequantizing only the data at the address level specified by the value of the zero run length,
The amount of operation required in the inverse quantizer can be reduced. For example, the operation speed of a hard-wired inverse quantizer implemented by a pipeline can be reduced, and the amount of operation can be reduced by an arithmetic unit that performs inverse quantization by a program method. It is possible to reduce the necessary processing capability of the signal processor and to realize the common operation core to share with other operations.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of an 8 × 8 block decoded by a zero run length decoder.

FIG. 2 is a diagram illustrating input information to a zero run length decoder.

FIG. 3 is a block circuit diagram showing a configuration example in which an inverse quantizer, which is a main configuration of a video decoder, is realized by applying a hard-wired system as a first embodiment of the present invention;

FIG. 4 is a processing flowchart for realizing, according to a second embodiment of the present invention, an inverse quantization operation that is a main operation of a video decoder by a program method;

FIG. 5 is a block circuit diagram showing a flow of a decoding process in an MPEG video decoder.

FIG. 6 is a block circuit diagram showing a conventional inverse quantizer used for a video decoder and its peripheral configuration.

[Description of Code] 24 Variable Length Decoder, 25 Dequantizer, 26 End of Block, 27 Zero Run Length, 28
Level, 29 address generator, 30 inverse quantization table, 32 multiplier, 33 processing block, 35
Control circuit, 38 delay buffer

Claims (2)

[Claims] 1. An inverse quantization method for decoding compressed data generated by performing quantization in units of blocks, followed by zero run length coding and variable length coding, wherein the variable length decoding of the compressed data is performed. Receive a zero-run length indicating the length of continuous zeros, a level that is a non-zero value, and an end-of-block indicating the end of a block, and generate an inverse quantization table from the value of the zero run-length. The initialization of the address generation and the end of the block processing are controlled by the end-of-block signal, and only the data of the level corresponding to the address specified by the value of the zero run length is inversely quantized. An inverse quantization method, characterized in that: 2. An inverse quantizer used for decoding compressed data generated by performing quantization in units of blocks, followed by zero run length coding and variable length coding, wherein the variable length of the compressed data is A receiving unit that receives a zero-run length indicating a continuous length of zero, a level that is a non-zero value, and an end-of-block indicating the end of a block, generated by decoding, and inverse quantization from the value of the zero run-length Address generating means for generating an address of the table, and control means for controlling the initialization of the address generating means and the end of the block processing by the end-of-block signal, and designated by the value of the zero run length. Dequantize only the data at the level corresponding to the address Quantizer.