JPH1186597A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute a burn-in test by providing a circuit which applys a mutually different potential in a bit line of a memory cell which executes reading/writing of data at the time of an ordinary operation and the bit line of a memory cell which is adjacent to the memory cell and is not used at the time of the ordinary operation. SOLUTION: When a signal S2 of L is applied to gate electrodes of switching transistor 12, 13 at the time of the burn-in test, a gate is opened and a negative voltage S1 is applied to the bit lines 6, 8. The bit lines 7, 9 are grounded and becomes zero potential, a prescribed potential difference is provided between mutually adjacent bit lines, a stress is loaded between the memory cells positioned between respective bit lines. Therefore, the generation of a defect between respective memory cells is accelerated, whereby a defect detecting ability at the time of executing the test is improved. Also, since the potential of respective bit lines are switched at one time by the use of wirings 10, 11, the time required for the burn-in test is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a burn-in test performed on a semiconductor memory, particularly a DRAM.

[0002]

2. Description of the Related Art Conventionally, the final step of manufacturing a semiconductor memory such as a DRAM includes an inspection step for inspecting a product and a reliability test. In this inspection process, a burn-in test is performed as a screening test for removing a semiconductor memory having an inherent defect and a potential cause of failure. The burn-in test is a test performed to remove a semiconductor device having an intrinsic defect or a device that causes a failure depending on time and stress from manufacturing variations.

[0003]

When a burn-in test is performed on a semiconductor memory such as a DRAM, a test time is shortened by applying an external temperature and voltage stress. However, in a conventional semiconductor memory,
In order to accelerate the test by giving a potential difference between adjacent memory cells and between bit lines, there is a problem that a burn-in device needs to be modified for each type of semiconductor memory, and a troublesome work such as modifying a test processing program is required. is there. In order to solve the above problem, there has been proposed a static memory in which a potential stress is directly applied from the outside between adjacent bit lines during an acceleration test of an SRAM (Japanese Patent Application Laid-Open No. Sho 62-2).
02396). However, such a memory has a problem that a special external terminal needs to be provided for directly applying a potential to the bit line inside the chip from the outside, and the circuit configuration is complicated.

[0004] Some conventional semiconductor memories such as DRAMs adopt a layout in which dummy cells and spare cells are provided next to memory cells (hereinafter simply referred to as memory cells) for reading and writing data during normal operation. Are known. A dummy cell is a cell that is not actually used, such as a word line fixed at “L”. Also,
The spare cell is a cell prepared as a substitute cell for a defective cell existing in the memory cell array. In a burn-in test of a semiconductor memory employing the layout, it is desirable to detect a defect between a memory cell located at an end of a memory cell array and a dummy cell adjacent to the memory cell.

[0005] However, as described above, the dummy cell is
Since the word line is fixed at "L", data cannot be written. Before the burn-in test for detecting defective cells, etc.,
Since no address is given to the spare cell, data cannot be written to any spare cell. Therefore, between the dummy cell and the spare cell, or
An appropriate potential difference, that is, stress cannot be applied between the dummy cell and the memory cell, and a sufficient burn-in test cannot be performed.

Accordingly, the present invention is directed to a semiconductor memory employing a layout having a spare cell and a dummy cell next to a memory cell for reading and writing data during a normal operation, and which is capable of performing a burn-in test more efficiently. An object of the present invention is to provide a semiconductor memory that has been adopted.

[0007]

A first semiconductor memory according to the present invention employs a layout in which a memory cell not used during normal operation exists next to a memory cell for reading and writing data during normal operation. In memory,
A bit line of a memory cell that reads and writes data during the normal operation, and a bit line of a memory cell that is adjacent to the memory cell and is not used during the normal operation,
A circuit for providing different potentials is provided.

[0008] The second semiconductor memory of the present invention comprises the first semiconductor memory.
Wherein the circuit connects one of bit lines of the adjacent memory cells to a substrate.

A third semiconductor memory according to the present invention includes the first semiconductor memory.
Wherein the circuit connects one of the bit lines of the adjacent memory cell to an I / O line.

A fourth semiconductor memory according to the present invention is a semiconductor memory adopting a layout in which a memory cell not used during normal operation exists next to a memory cell for reading and writing data during normal operation. A circuit is provided which outputs an "H" signal to a word line of a memory cell that is not used during operation and outputs "H" and "L" data signals to a bit line connected to the memory cell. And

According to a fifth aspect of the present invention, there is provided a semiconductor memory adopting a layout in which a memory cell not used during a normal operation exists next to a memory cell for reading and writing data during a normal operation. During operation, a bit line of a memory cell which is not used is fixed at a predetermined potential, and a bit line of a memory cell adjacent to the memory cell, which reads and writes data during the normal operation, has a different value from the predetermined potential. A circuit for writing a signal is provided.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) First Embodiment FIG. 1 is a diagram showing a DR which is a semiconductor memory according to a first embodiment.
FIG. 2 is a block diagram illustrating a configuration around an AM memory cell array 1; When an address is specified from outside to write or read data, the row address decoder 2 selects a predetermined word line WL based on the specified address. Also, the column address decoder 3
A predetermined bit line BL based on a designated address
Select The memory cells MC specified by the respectively selected word line WL and bit line BL become active, and data read / write is performed. When reading data, the data read from the memory cell MC is amplified by the sense amplifier 4 and then output to the outside via the I / O line 5.

FIG. 2 is a diagram showing the internal configuration of the memory cell array 1. In the memory cell array 1, sense amplifiers 4a, 4b,..., A pair of bit lines 6 and 7, 8, 9 and. Word lines DWL1,
DWL2 and a plurality of word lines WL1, WL2,
... Note that the dummy word lines DWL1, DW
L2 is grounded. Dummy cells MC0, MC1,... Are provided at locations where the respective bit lines intersect with the dummy word lines DWL1, DWL2, and at locations where the respective bit lines intersect with the word lines WL1, WL2,. Memory cells for reading and writing data during operation (hereinafter simply referred to as memory cells) MC2, MC3
... are arranged in order. Note that a plurality of word lines W
A configuration may be employed in which a part of L1, WL2,... Is used as a word line for a spare cell. Here, the spare cell is a cell prepared as a substitute cell for a defective cell existing in the memory cell array. Further, the bit lines 6 and 7 may be dummy bit lines.

In the present semiconductor memory, the memory cell array having the above configuration is provided with a wiring 10 for applying a predetermined negative voltage S1 to odd-numbered bit lines from the left in the drawing and a wiring 11 for grounding even-numbered bit lines. The application of a negative voltage S1 to the illustrated bit lines 6 and 8 is controlled by a switching transistor 12. The grounding of the bit lines 7 and 9 shown in the figure is controlled by the switching transistor 13. The value of the signal S2 applied to the gate electrodes of the switching transistors 12 and 13 usually takes a value of “H”, and when a burn-in test is executed, the value of “L” is set by an internal control circuit or a burn-in device.
Is switched to.

When an "L" signal S2 is applied to the gate electrodes of the switching transistors 12 and 13, the gate opens and a negative voltage S1 is applied to the bit lines 6 and 8. Also, the bit lines 7 and 9 are grounded and become zero potential. As a result, a predetermined potential difference is provided between the adjacent bit lines, and between the memory cells located between the bit lines, for example, between the dummy cell MC0 and the dummy cell MC1, between the dummy cell MC1 and the memory cell MC2 (the memory cell MC2). Is the same as in the case of a spare cell.), Stress is applied between the memory cells MC2 and MC3 and the like. As a result, the occurrence of defects between the memory cells is accelerated, and the capability of detecting defects during execution of the burn-in test is improved. Further, in the present semiconductor memory, since the potential of each bit line is switched at a time using the wirings 10 and 11, for example, a test pattern data is sequentially written for each bit and a stress is applied to the bit line in comparison with a burn-in test. The required time can be shortened.

By employing the above configuration, not only all the memory cells of the memory cell array, that is, not only between the memory cells but also between the memory cells (including the spare cells) located at the ends of the memory cell array and the dummy cells. Stress can be applied, and an appropriate burn-in test can be performed.

Hereinafter, the configuration of the semiconductor memory of the first embodiment will be described more specifically. FIG. 3 shows FIG.
FIG. 3 is a diagram showing a cell structure of a dummy cell MC1 and a memory cell MC2 shown in FIG. The dummy cell MC1 of the DRAM is
It comprises one capacitor 20 and one switching transistor 21. The dummy word line DWL2 is connected to the gate electrode of the switching transistor 21 forming the dummy cell MC1. The dummy word line DWL2 is grounded and maintained at "L" level. The bit line 6 is connected to the source electrode of the transistor 21. On the other hand, the memory cell MC
2 includes one capacitor 22 and one switching transistor 23. The word line WL1 is connected to the gate electrode of the switching transistor 23 forming the memory cell MC2. Word line WL1 is grounded and maintained at "L" level.
The bit line 7 is connected to the source electrode of the transistor 23.

As already described with reference to FIG. 2, the wiring 10 for applying the negative voltage S1 is connected to the bit line 6, and the wiring 11 for applying zero potential is connected to the bit line 7. ing. When the burn-in test is performed, an "L" signal S2 is applied to the gate electrodes of the switching transistors 12 and 13 from the internal control circuit or burn-in device, a negative voltage S1 is applied to the bit line 6, and a bit line 7 is applied. Is set to zero. As a result, a potential difference is provided between the bit lines 6 and 7, and stress is applied between the dummy cell MC1 and the memory cell MC2.

As shown in FIG. 3, in the manufacturing process, when foreign matter 25 is interposed between the dummy cell MC1 and the memory cell MC2 and the dummy cell MC1 and the memory cell MC2 are short-circuited, a current I flows through the bit lines 6 and 7.
During execution of the burn-in test, a defective portion can be detected by monitoring the value of the current I flowing between the memory cells.

The value of the voltage VG applied to the gate electrode of at least one of the switching transistors of the memory cells adjacent to each other among the plurality of memory cells constituting the memory cell array is 0.2 to 0.4 V from the ground potential. It is preferable to set a higher value. For example, as shown in FIG.
The voltage VG of the word line WL2 connected to the gate electrode is set to be higher than the ground potential by about 0.2 to 0.4 V. Thereby, the switching transistor 23 is easily turned on. That is, the current I easily flows when a short circuit occurs between the memory cells due to foreign matter or the like, and the accuracy of detecting a defect during execution of the burn-in test can be improved.

(2) Second Embodiment FIG. 5 shows a semiconductor memory DR according to a second embodiment.
FIG. 3 is a diagram showing a configuration of an AM memory cell. In the memory cell array, a pair of bit lines 41 and 4 extending from the sense amplifiers 40a, 40b,.
2, two dummy word lines DWL3 and DWL intersecting the bit lines 43 and 44,.
4 and a plurality of word lines WL3, WL4,. The dummy word lines DWL3 and DWL4 are grounded. Dummy cells MC0, MC1,... Are provided at locations where each bit line intersects with the dummy word lines DWL3, DWL4, and at locations where each bit line intersects with the word lines WL3, WL4 during normal operation. Memory cells (hereinafter simply referred to as memory cells) MC6, MC7,... For reading and writing data are arranged in order. Note that a plurality of word lines WL3, W
A configuration may be adopted in which a part of L4,... Is used as a word line for a spare cell. Here, the spare cell is a cell prepared as a substitute cell for a defective cell existing in the memory cell array. Also, bit line 4
1 and 42 may be dummy bit lines.

FIG. 6 is a diagram showing a configuration of the sense amplifier 40a. The sense amplifier 40a has bit lines 41 and 42 extending from a normal sense amplifier 40, and wirings 45 and 46 connected to a substrate via normally-on switching transistors 43 and 44, respectively. The signals φ1 and φ2 applied to the gate electrodes of the switching transistors 43 and 44 are controlled by an internal control circuit or a burn-in device.

When the burn-in test is executed, the internal control circuit or the burn-in device switches the signal φ1 or φ2 applied to one of the gate electrodes of the switching transistors 43 and 44 from “H” to “L” to switch the gate. And set the potential of the bit line 21 or 22 to the substrate potential V
Same as BB. In a DRAM, the substrate potential VB is usually
B is a negative value. Therefore, the bit lines 41 and 4
2, a potential difference is generated between the memory cells at positions between the bit lines 41 and 42, for example, between the dummy cells MC4 and MC5, between the dummy cells MC5 and MC6, between the memory cells MC6 and MC6. Stress is applied to the memory cells and the like, and the occurrence of defects between the memory cells can be accelerated. As a result, it is possible to improve the accuracy of detecting a defect during execution of the burn-in test.

By adopting the above configuration, not only between all the memory cells of the memory cell array, that is, between the memory cells, but also between the dummy cells and the memory cells (including the spare cells) located at the ends of the memory cell array. Stress can be applied, and an appropriate burn-in test can be performed.

FIG. 7 shows a sense amplifier circuit 40a provided in a DRAM which is a semiconductor memory according to the second embodiment.
It is a figure showing the composition of the modification of. In this modification, I / O lines are connected to bit lines 41 and 42 extending from a normal sense amplifier circuit 40 via I / O switches 53 and 54. That is, the I / O switches 53 and 54
To connect the bit lines 41 and 42 to the I / O line, and the signal input to the I / O pin
And 42 are controlled. During execution of the burn-in test, a negative voltage is applied to one of the bit lines 41 and 42. Thereby, the bit lines 41 and 4
2 between the memory cells at positions between the bit lines 41 and 42, for example, between the dummy cells MC4 and MC5, between the dummy cells MC5 and the memory cell MC6, and between the memory cells MC6 and Generation of a defect between the memory cell MC7 and the memory cell MC7 can be accelerated. As a result, it is possible to improve the accuracy of detecting a defect during execution of the burn-in test. Further, all the memory cells of the memory cell array, that is,
Stress can be applied not only between the memory cells but also between the dummy cells and the memory cells (including the spare cells) located at the ends of the memory cell array, and an appropriate burn-in test can be performed.

(3) Third Embodiment FIG. 8 shows a DRAM of a semiconductor memory according to a third embodiment.
3 is a diagram showing a configuration of a main part of the memory cell of FIG. Bit lines 601, 610, extending from a sense amplifier (not shown)
The bit line 601 on the left side of the drawing is a dummy bit line. Also, word lines 600, 611, 612, 61 provided to cross each bit line
Word line 600 located at the top of the drawing among 3,.
Is a dummy word line. Note that part of the word lines 611, 612, 613,... May be used as word lines for spare cells. In the memory cell array having this configuration, the memory cells 604, 605, 606, 607
Are dummy cells, and the memory cells 608 and 609 are
This is a memory cell located at an end of a normal memory cell array for reading and writing data during a normal operation. This semiconductor memory has a switch 6 for supplying a voltage of “H” to the word line 600 of the dummy cell when the burn-in test is performed.
02 and a switch 603 that enables writing of “L” and “H” data to the bit line 601 of the dummy cell. Switches 602 and 603 are switched based on a control signal S3 output from an internal control circuit or a burn-in device.

At the time of executing the burn-in test, each switch is turned on and the dummy word line 600 is set to "
H ”and the dummy bit line 601 has“
L "," H "," L ",... Are input, and" 0 "," 1 ",""are sequentially stored in the memory cells 604, 605, and 606.
The data of "0" is written.
Input the data of “H”, “L”, “H”,.
"1", "1" are sequentially stored in the memory cells 607, 608, and 609.
The data “0” and “1” are written, whereby the target memory cell 608 at the end of the memory cell array and the memory cells (including dummy cells) 605 and 60 around the target memory cell 608 are provided.
7, 609, and the occurrence of defects existing between the memory cell of interest 608 and its surrounding memory cells (including dummy cells) 605, 607, 609 is accelerated, and the burn-in test is performed. And the ability to detect a defect at the time of execution is improved.

By adopting the above configuration, not only between all the memory cells of the memory cell array, that is, between the memory cells, but also between the memory cells (including the spare cells) located at the ends of the memory cell array and the dummy cells. Stress can be applied, and an appropriate burn-in test can be performed.

Incidentally, without providing the switches 602 and 603, I / O lines (Read / Write) are applied to spare memory cells and dummy cells in the same manner as normal memory cells.
Line) may be connected to enable writing of data to an arbitrary address.

(4) Fourth Embodiment FIG. 9 is a diagram showing a configuration of a memory cell array of a semiconductor memory according to a fourth embodiment. Each sense amplifier 90 ~
93, a pair of bit lines 94 and 95, 96 respectively.
And 97, 98 and 99, and 100 and 101 are extended. Bit lines 94 and 95 are dummy bit lines. Further, the bit lines 96 and 97 may be used as bit lines for spare cells. A memory cell is provided at a position where each word line and bit line intersect by a known technique. In this semiconductor memory, the dummy bit lines 94 and 95 are set to a predetermined potential, for example, zero potential, via the switching transistor 102 in order to provide a predetermined potential difference between the dummy bit line 95 and the bit line 96. Wiring 103 to be provided. The signal S4 is input to a gate electrode of the switching transistor 102. The potential level of this signal S4 is normally "H", and is switched to "L" by an internal control circuit or a burn-in device during execution of a burn-in test.

The switching transistor 102 is turned on by the input of the signal S4 of "L", and the bit lines 94 and 95 are grounded. As a result, a potential difference occurs between the adjacent bit line 96 and a stress is applied between the cell connected to the dummy bit line 95, that is, the dummy cell and the memory cell connected to the bit line 96, The occurrence of defects between these cells is accelerated, and the capability of detecting defects during execution of the burn-in test can be improved.

By adopting the above configuration, not only between all the memory cells of the memory cell array, that is, between the memory cells, but also between the memory cells (including the spare cells) located at the ends of the memory cell array and the dummy cells. Stress can be applied, and an appropriate burn-in test can be performed.

(5) Fifth Embodiment FIG. 10 shows a DRA of a semiconductor memory according to a fifth embodiment.
FIG. 3 is a diagram showing a configuration of M memory cells. In the present semiconductor memory, spare cell arrays 151 and 152 and a memory cell array 153 for reading and writing data during normal operation are laid out at positions adjacent to the dummy cell array 150. In this semiconductor memory, the values of all the bit lines of the dummy cell array 150, the values of all the bit lines of the spare cell arrays 151 and 152, the values of all the bit lines of the dummy cell array 150, and the values of all the bits of the memory cell array 153 A wiring 155 is provided for setting the values of all bit lines of the dummy cell array 150 to a predetermined potential, for example, zero potential, so that the values of the lines are different from each other. The grounding of all the bit lines of the dummy cell array 150 is controlled by the switching transistor 154. The switching transistor 154 is a normally-on type transistor, and a control signal S5 of “H” is input to a gate electrode of the switching transistor 154 during a normal operation. The control signal S5 is supplied by an internal control circuit or a burn-in device during a burn-in test.
L ".

At the time of execution of the burn-in test, the control signal is switched to "L" by an internal control circuit or a burn-in device, the gate of the switching transistor 152 is opened, and all the bit lines of the dummy cell array 150 are set to zero potential. You. As a result, stress is applied between the dummy cell array 150 and the memory cell array 153 and between the dummy cell array 150 and the spare cell arrays 151 and 152, thereby causing a defect between cells arranged at the end of each array. Is accelerated, and the ability to detect a defect during execution of the burn-in test is improved.

By employing the above configuration, stress is applied not only between the memory cells in the memory cell array 153, but also between the memory cells located at the ends of the memory cell array 153 and the dummy cells, and between the spare cells and the dummy cells. And an appropriate burn-in test can be performed.

[0036]

According to the first semiconductor memory of the present invention, the bit line of the memory cell located at the end of the memory cell for reading and writing data during normal operation and the bit line used during normal operation adjacent to the memory cell are used. A predetermined potential difference is provided between the memory cell and the bit line of the memory cell not to be stressed. Thereby, not only between all the memory cells of the memory cell array of the semiconductor memory, that is, between memory cells for reading and writing data during normal operation,
Stress can also be applied between a memory cell (including a spare cell) located at an end of the memory cell array and a memory cell (dummy cell) not used during normal operation, and an appropriate burn-in test can be performed.

In the second semiconductor memory of the present invention, a bit line of a memory cell located at an end of a memory cell for reading and writing data in a normal operation, and a memory adjacent to the memory cell and not used in a normal operation Either one of the cell bit lines is connected to the substrate and brought to the substrate potential,
A predetermined potential difference can be provided to apply stress.
Thereby, not only between all the memory cells of the memory cell array of the semiconductor memory, that is, between memory cells for reading and writing data during normal operation, but also for memory cells (including spare cells) located at the end of the memory cell array,
Memory cells not used during normal operation (dummy cells)
Stress can be applied between them, and an appropriate burn-in test can be performed.

In the third semiconductor memory of the present invention, a bit line of a memory cell located at an end of a memory cell for reading and writing data in a normal operation, and a memory adjacent to the memory cell and not used in a normal operation By connecting one of the cell bit lines to an I / O line and applying a predetermined voltage from the I / O line, a predetermined potential difference can be provided between the bit lines to apply stress.
Thereby, not only between all the memory cells of the memory cell array of the semiconductor memory, that is, between memory cells for reading and writing data during normal operation, but also for memory cells (including spare cells) located at the end of the memory cell array,
Memory cells not used during normal operation (dummy cells)
Stress can be applied between them, and an appropriate burn-in test can be performed.

In the fourth semiconductor memory of the present invention, the word line of the memory cell not used during the normal operation
By outputting the "H" signal and alternately outputting the "H" and "L" data signals to the bit lines, it is possible to write desired value data to memory cells not used during normal operation. As a result, a predetermined potential difference is provided between a memory cell located at an end of a memory cell for reading and writing data during normal operation and a memory cell adjacent to the memory cell and not used during normal operation. This can provide a stress on all the memory cells of the memory cell array of the semiconductor memory,
That is, not only between memory cells for reading and writing data during normal operation, but also between memory cells (including spare cells) located at the end of the memory cell array and memory cells (dummy cells) not used during normal operation. Can also put stress and perform an appropriate burn-in test.

In the fifth semiconductor memory of the present invention, a predetermined potential difference is provided between a memory cell not used during normal operation and a memory cell located adjacent to the memory cell and located at an end of the memory cell array. Can give stress. Thereby, not only between all the memory cells of the memory cell array of the semiconductor memory, that is, between memory cells for reading and writing data during normal operation, but also for memory cells (including spare cells) located at the end of the memory cell array, Stress can be applied to a memory cell (dummy cell) not used during normal operation, and an appropriate burn-in test can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a semiconductor memory according to a first embodiment;
FIG. 2 is a diagram illustrating a configuration around a memory cell array of a RAM.

FIG. 2 is a diagram showing an internal configuration of a memory cell array.

FIG. 3 is a diagram showing a configuration of a dummy cell and a memory cell.

FIG. 4 is a diagram showing a configuration of a modification of the cell structure of the semiconductor memory according to the first exemplary embodiment;

FIG. 5 is a diagram illustrating a semiconductor memory according to a second embodiment;
FIG. 2 is a diagram illustrating a configuration of a memory cell of a RAM.

FIG. 6 is a diagram showing a configuration of a sense amplifier.

FIG. 7 is a diagram showing a configuration of a modified example of the sense amplifier.

FIG. 8 is a diagram illustrating a configuration of a semiconductor memory according to a third embodiment;

FIG. 9 is a diagram illustrating a configuration of a semiconductor memory according to a fourth embodiment;

FIG. 10 is a diagram illustrating a configuration of a semiconductor memory according to a fifth embodiment;

[Explanation of symbols]

1 memory cell array, 6, 7, 8, 9, 41, 42,
43,44,94,95,96,97,98,99,1
00, 101 bit lines, 12, 13, 43, 4
4,102,154 switching transistor,
4a, 4b, 40, 40a, 40b, 90, 91, 9
2,93 sense amplifier, 53,54 I / O switch, 602,603 switch

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hayato Ikeda 1-132 Ogino, Itami-shi, Hyogo Daio Electric Machine Co., Ltd. (72) Inventor Yutaka Ikeda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric (72) Inventor Masahiro Orito 2-6-1 Otemachi, Chiyoda-ku, Tokyo Mitsubishi Electric Engineering Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor memory adopting a layout in which a memory cell not used during normal operation exists next to a memory cell reading and writing data during normal operation, wherein the memory performs data reading and writing during the normal operation. The bit line of the cell and the bit line of the memory cell adjacent to the memory cell and not used during the normal operation are
A semiconductor memory provided with circuits that provide different potentials. 2. The semiconductor memory according to claim 1, wherein said circuit connects one of bit lines of said adjacent memory cells to a substrate. 3. The semiconductor memory according to claim 1, wherein said circuit connects one of bit lines of said adjacent memory cells to an I / O line. 4. A semiconductor memory adopting a layout in which a memory cell that is not used during normal operation exists next to a memory cell that reads and writes data during normal operation, wherein the word of the memory cell not used during normal operation is used. A semiconductor memory comprising: a circuit that outputs an “H” signal to a line and outputs “H” and “L” data signals to a bit line connected to the memory cell. 5. A semiconductor memory adopting a layout in which a memory cell that is not used during normal operation exists next to a memory cell that reads and writes data during normal operation, wherein a bit of the memory cell not used during normal operation is used. A circuit for fixing a line to a predetermined potential and writing a signal having a value different from the predetermined potential to a bit line of a memory cell adjacent to the memory cell and reading and writing data during the normal operation. Characteristic semiconductor memory.