JPH118602A - Reception circuit for digital broadcast - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a reception circuit for digital broadcast to easily decode plural optional channels. SOLUTION: The reception circuit is provided with a decoder circuit 16 that decodes data of one channel into data of plural channels, with another decoder circuit 17A that decodes data outputted from the decoder circuit 16 into original data. The decoder circuit 16 provides an output of an identification code that specifies the other decoder 17A when the circuit 16 outputs the decoded data of one channel. The other decoder circuit 17A decodes the data outputted from the decoder circuit 16 into the original data and provides an output of the original data only when the identification code from the decoder circuit 16 addresses the circuit 17A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiving circuit suitable for a digital audio broadcast receiver.

[0002]

2. Description of the Related Art In Europe, DAB (Digital Audio Broadcasting) according to the Eureka 147 standard is implemented. The signal processing on the transmitting side is as follows. (1) Digital audio data of a maximum of 64 channels is data-compressed by MPEG audio layer II for each channel. (2) Encode processing for error correction is performed on the data of each channel resulting from the term (1) by convolutional coding and interleaving on the time axis. (3) The result of item (2) is multiplexed into one channel. At this time, auxiliary data such as PAD is also added. (4) Interleave the result of item (3) on the frequency axis and add a symbol for synchronization. (5) The result of (4) is subjected to OFDM processing (orthogonal frequency division multiplexing processing) and further D / A converted. (6) The carrier signal is subjected to QPSK modulation (quadrature modulation) according to the result of the item (5), and this QPSK signal is transmitted.

[0003]

According to the present invention, when a plurality of channels are simultaneously selected and decoded in a digital broadcast receiver for simultaneously broadcasting digital data of a plurality of channels as described above, this can be easily performed. Is to do so.

[0004]

Therefore, according to the present invention, there is provided a digital broadcast for multiplexing digital data of a plurality of channels into data of one channel and broadcasting the multiplexed data. In a receiving circuit for receiving a broadcast, a decoder circuit for decoding the data of the one channel into the data of the plurality of channels and another decoder circuit for decoding data output from the decoder circuit to the original data are provided. The decoder circuit, when outputting the decoded data of one channel, outputs an identification code identifying the another decoder circuit, and the another decoder circuit outputs the identification code from the decoder circuit. Only when the device specifies itself, the data output from the decoder circuit is It is intended to a receiving circuit of a digital broadcasting which is adapted to decode and output the data. Therefore, each data is effectively supplied to only the designated decoder circuit and decoded.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the example shown in FIG. 1, arbitrary seven channels can be simultaneously selected from the above-mentioned 64 channels, and the audio signals of the seven channels are changed to A channel to G channel (output channel). This is the case when outputting.

That is, in FIG. 1, a broadcast wave signal of DAB is received by an antenna 11, and the received signal is
The signal is supplied to a front end circuit 12 configured in a superheterodyne format and converted into an intermediate frequency signal. The intermediate frequency signal is supplied to an A / D converter circuit 13 and converted into a digital signal.

The digital signal is supplied to a quadrature demodulation circuit 14 to demodulate baseband data. The data is supplied to an FFT circuit 15 for OFDM demodulation, and the OFDM demodulated data is supplied to a Viterbi decoder circuit 16. Supplied to At this time, a channel selection signal (channel selection signal, program selection signal) is supplied from the system control microcomputer 40 to the decoder circuit 16.

Thus, in the decoder circuit 16,
Deinterleaving and error correction are performed as decoding processing on the data of the channel selected by the selection signal. In this case, the selection of the channel, that is, deinterleaving and error correction, is valid up to seven channels in this example. In addition,
In the following description, the processed data of the seven valid channels is referred to as data D01 to D07.

The data D01 to D07 of the seven channels subjected to the deinterleaving and error correction are output from the decoder circuit 16 in a time-division manner, and supplied to the data decompression circuits 17A to 17G in parallel (commonly). .

Further, for example, an audio signal obtained from the data D01 is output to the B channel. Data D
The audio signal obtained from 02 is output to the G channel. An audio signal obtained from the data D03 is output to the A channel. ...... Outputs the audio signal obtained from the data D07 to the F channel. If so, data indicating this is supplied from the microcomputer 40 to the decoder circuit 16. That is, data specifying an output channel (A channel to G channel) when outputting an audio signal is transmitted from the microcomputer 40 to the decoder circuit 1.
6.

Further, the data decompression circuits 17A to 17G are given identification numbers (addresses) of, for example, "1" to "7", and are supplied with an identification code (address signal) ID corresponding to the identification numbers. Only the supplied data is effectively taken in and processed.

When the data D01 to D07 are supplied from the decoder circuit 16 to the data decompression circuits 17A to 17G in a time-division manner, the identification code ID is transmitted from the decoder circuit 16 to the data decompression circuit in synchronization with the data D01 to D07. 17A ~
17G. In this case, for example, data D01-
If the audio signal obtained from D07 is output to the A channel to the G channel as described above, the decoder circuit 16 outputs ID = 2 (B channel) data D02 when the data D01 is output. When ID = 7 (G channel) When data D03 is output, ID = 1 (A channel)... When data D07 is output, ID = 6 (F channel). Is output. That is, an identification code ID of a value designating an output channel (data decompression circuits 17A to 17G) of an audio signal obtained from data D01 to D07 is output.

Therefore, when the output channel is set as described above, when the data D01 to D07 are output from the decoder circuit 16, and when the data D01 is output, the data is taken into the decompression circuit 17B. When the data D02 is output, it is taken into the expansion circuit 17G. When the data D03 is output, it is taken into the expansion circuit 17A. When the data D07 is output, it is taken into the decompression circuit 17F. Becomes

That is, the data D01 to D07 are supplied to all the data decompression circuits 17A to 17G, but are taken into only the data decompression circuit indicated by the identification code ID, and are effective only in the data decompression circuit.

In the data decompression circuits 17A to 17G, the fetched data is decoded into the original digital audio data by the next decoding process, in this case, MPEG data decompression. And
These digital audio data are supplied to the D / A converter circuits 18A to 18G and are D / A converted into original analog audio signals.
G respectively.

Further, at this time, the Viterbi decoder circuit 1
A part of the data is supplied from R6 to the RDI circuit 22 to be converted into data of a predetermined transfer format. Further, for example, the synchronous processor 23 is configured by a DSP and the AF of the front end circuit 12 is
C is performed, and processing such as synchronization in the FFT circuit 15 is performed.

Thus, according to this receiver, for example, 7
Although audio signals of two channels can be obtained at the same time, in this case, in particular, according to this receiver, when outputting data from the decoder circuit 16, the processing destination of the data (data expansion circuits 17A to 17G) is specified. Since the identification code ID is also output, data of a plurality of channels can be easily decompressed.

For the same reason, it is easy to change which channel signal of the broadcasted channel is output to which output channel (A channel to G channel) only by changing the value of the identification code ID. can do. Moreover, the configuration for this is also simple.

Further, the circuits 14 to 16 and 1
If the 7A, 22, and 23 are integrated into a single chip IC in the LSI 10, a receiver that requires only one channel of audio signal uses only the LSI 10 and a receiver that requires a plurality of channels of audio signals at the same time. LS
If a data expansion circuit and a D / A converter circuit are connected to I10 (the number of channels -1), the LSI 10 can be used for a receiver having any number of channels.

The data D01 from the decoder circuit 16
To D07 and the identification code ID are common to all the decompression circuits 17A to 17G.
When converting to C, the number of external pin terminals is not related to the number of channels and does not increase with the number of channels.

In the above description, the identification code ID and
The data D01 to D07 are supplied to the data decompression circuits 17A to 17G through separate signal lines. For example, a header section is provided at the beginning of each of a predetermined amount of data D01 to D07, and an identification code is provided in the header section. If the ID is provided, the signal line can be shared.

In the above description, the present invention relates to a DAB
Although the present invention is applied to a receiving circuit of a receiver, the present invention can be applied to a digital broadcast receiver that multiplexes a plurality of digital data into one data and broadcasts the data at the same time.

[0023]

According to the present invention, audio signals of a plurality of channels can be easily and simultaneously obtained. Further, it is possible to easily change which channel signal of the broadcast channel is output to which output channel. Moreover, the configuration for this is also simple.
Further, when the IC is formed, the IC can be used for a receiver having any number of channels, and the IC can be easily formed.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

[Explanation of symbols]

10: LSI, 12: front-end circuit, 13: A /
D converter circuit, 14: orthogonal demodulation circuit, 15: FFT
Circuit, 16: Viterbi decoder circuit, 17A to 17G: data expansion circuit, 18A to 18G: D / A converter circuit, 22: RDI circuit, 23: reproduction synchronization circuit, 40: microcomputer

Claims (3)

[Claims] 1. A receiving circuit for multiplexing digital data of a plurality of channels into data of one channel and broadcasting the multiplexed data, wherein the receiving circuit receives the digital broadcast. And a separate decoder circuit for decoding the data output from the decoder circuit into the original data. The decoder circuit decodes the decoded 1 When outputting data of one channel, outputting an identification code specifying the another decoder circuit; the other decoder circuit only outputs the decoder code when the identification code from the decoder circuit specifies itself; Digital that decodes the data output from the circuit to the original data and outputs it Broadcast receiving circuit. 2. The digital broadcast receiving circuit according to claim 1, wherein said another decoder circuit is a data decompression circuit, and said data decompression circuit specifies that said identification code from said decoder circuit specifies itself. And a digital broadcast receiving circuit for outputting original digital audio data only when the data output from the decoder circuit is expanded. 3. A digital broadcast receiving circuit according to claim 2, wherein at least said decoder circuit and said data decompression circuit are integrated into one IC.