JPH1165522A - Drive method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a drive method for a plasma display panel making operating points in address periods equal, even if a difference is generated in residual wall charge amounts due to the difference in the resets of a subfield performing the writing of all pixels and a subfield performing the erasure of pixels. SOLUTION: In a drive method, in which one field is constituted of plural subfields including a subfield A in which after a priming pulse Pxp for performing a discharge with respect to all pixels is impressed between row electrodes X, Y, a reset period when wall charge is erased by making impression voltage between both row electrodes zero is provided and a subfield B in which a reset period when only pixels discharged in a preceding subfield are made discharged to be erased by impressing an erasing pulse Exp for discharging only the pixels is provided, even when wall charge states after the resets of respective subfields are different, the subfields are made to address at the same operating points by changing address pulses Awp of scanning pulses Scyp which are two kinds of subfields.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC type plasma display panel (hereinafter referred to as AC-PDP),
In particular, the present invention relates to a method of driving a surface discharge type AC-PDP.

[0002]

2. Description of the Related Art As is well known, a plasma display panel has a structure in which minute discharge cells (also referred to as display cells or pixels) are formed between two glass plates, and is variously studied as a thin television or display monitor. An AC plasma display panel (AC-PDP) having a memory function is known as one of them. One of the AC-PDPs is a surface discharge type AC-PDP.
There is PDP.

FIG. 5 is a perspective view showing the structure of a surface discharge type AC-PDP.
Are described in, for example, JP-A-7-140922 and JP-A-7-140922.
287548. In FIG. 5, 1
Is a surface discharge type plasma display panel, 2 is a front glass substrate as a display surface, 3 is a rear glass substrate opposed to the front glass substrate 2 with a discharge space interposed therebetween, and 4 and 5 are opposite to each other on the front glass substrate 2. The first row electrodes X1 to Xn and the second row electrodes Y1 to Yn, 6
Is a dielectric layer coated on these row electrodes 4 and 5, and 7 is MgO (magnesium oxide) formed on the dielectric layer 6 by a method such as vapor deposition.

[0004] Reference numeral 8 denotes a row electrode 4 on the rear glass substrate 3.
Column electrodes W1 to Wm formed so as to be orthogonal to
Reference numeral 9 denotes a phosphor layer formed on the column electrode 8;
The phosphor layers 9 emitting red, green, and blue light are provided in stripes in order. Reference numeral 10 denotes a partition formed between the column electrodes 8. The partition 10 has a role of separating the discharge cells and also a role of a column for preventing the plasma display panel from being crushed by the atmospheric pressure. A discharge gas such as a Ne—Xe mixed gas or a He—Xe mixed gas is sealed in the space between the glass substrates at a pressure equal to or lower than the atmospheric pressure, and a pair of row electrodes 4 and 5 and a pair of column electrodes 8 orthogonal thereto are provided. The discharge cell at the intersection of becomes a pixel. Hereinafter, the first row electrode 4
May be called an X electrode, the second row electrode 5 may be called a Y electrode, and the column electrode 8 may be called a W electrode.

Next, the operation will be described. A shown in FIG.
In the C-PDP, a first row electrode 4 and a second row electrode 5 are covered with a dielectric layer 6, and during display, a voltage pulse is alternately applied between the two row electrodes, and a polarity is applied every half cycle. Is generated, causing the display cell to emit light. In the color display, the phosphor layer 9 formed in each cell is excited by ultraviolet light from discharge to emit light. Since the first row electrode 4 and the second row electrode 5 that perform discharge for display are covered with the dielectric layer 6, once a discharge occurs between the electrodes of each cell,
The electrons and ions generated in the discharge space move in the direction of the applied voltage and accumulate on the dielectric layer 6. This dielectric layer 6
The charges such as electrons and ions accumulated above are called wall charges.
The electric field formed by the wall charges acts in a direction to weaken the applied electric field, and thus the discharge is rapidly extinguished with the formation of the wall charges.

When an electric field whose polarity is inverted to that of the previous discharge is applied after the discharge is extinguished, the electric field formed by the wall charges overlaps with the applied electric field. It becomes possible. Thereafter, the discharge can be maintained by inverting the low voltage every half cycle. Such a function is a function originally provided in the AC-PDP, and this function is called a memory function. A discharge sustained at a low applied voltage using this memory function is called a sustain discharge, and a voltage pulse applied to the first row electrode 4 and the second row electrode 5 every half cycle is called a sustain discharge pulse. This sustain discharge is continued as long as the sustain discharge pulse is applied, until the wall charge is extinguished. Eliminating the wall charges is called erasing, and forming the wall charges on the dielectric layer 6 first is called writing.

Writing is performed for an arbitrary cell on the screen of the AC-PDP, and thereafter, by performing a sustain discharge, characters, figures, images, etc. can be displayed. In addition, writing, sustaining discharge, and erasing can be performed at high speed. By doing so, a moving image can be displayed. In the case of performing a gray scale display, it can be performed by controlling the time for emitting light by the sustain discharge.

Next, a gray scale display method of the AC-PDP will be briefly described. FIG. 6 shows, for example, JP-A-7-16021.
FIG. 9 is a configuration diagram of one field in the case of performing a gradation display disclosed in Japanese Patent Application Publication No. 8 (JP-A-8). One field is a time for outputting one picture on the screen, and about 16.6 ms in the case of NTSC.
ec (60 Hz). In the drawing, a display line is a line in the row direction composed of first and second row electrodes 4 and 5 of the AC-PDP. The horizontal direction of the figure shows the flow of time.

As shown, one field is divided into several sub-fields, and each sub-field is
It consists of a reset period, an address period, and a sustain discharge period. For example, 256 gradations (2 ⁸ gradations) when performing display,
Eight subfields in one field (SF1, SF1
2,..., SF8), and the duration of the sustain discharge period of each subfield is set to 2 ⁿ (n = 0 to 7). The reset period is a period in which all the cells of the AC-PDP are kept in the same state, and there are cases where the wall charges of all the cells are set to “absent” and “set”. The erasure for eliminating the wall charges corresponds to this reset.

The address period is a period in which an arbitrary display cell on the screen is controlled by the matrix selection of a row electrode and a column electrode so as to control "present" and "absent" of the wall charge of each cell. This is performed during the address period. During the sustain discharge period, the sustain discharge is performed only on the cells having the wall charge “present” after the address period. The light emission due to the sustain discharge is used for display, and the cells that emit light by the sustain discharge within one field are illuminated brighter. Thus, gradation display can be performed by controlling the light emission time for each cell.

The driving method for separating the address period and the sustain discharge period over the entire screen of the AC-PDP as described above is called an "address / sustain separation method", and is a known method which has become common in current AC-PDPs. Technology. On the other hand, the reset method and address method in each subfield are AC-
This is an important technology that affects PDP performance.

FIG. 7 is a diagram showing a voltage waveform in one subfield for explaining a conventional method of driving a plasma display panel disclosed in Japanese Patent Application Laid-Open No. 7-160218. The voltage waveform shown in FIG. 7 includes, in order from the top, a column electrode W, a first row electrode X, and a second row electrode Y1, Y2, Yn.
3 shows an applied voltage waveform. Here, first, in the reset period, the entire-surface write pulse Pxp is applied to the first row electrodes X commonly connected to all the screens at time a in the drawing. This full write pulse Pxp may be called a priming pulse. Hereinafter, unless otherwise specified, it is referred to as a priming pulse.

The priming pulse Pxp is set to be equal to or higher than the discharge starting voltage between the first row electrode X and the second row electrode Y, and is applied for a sufficiently long time of about 10 μsec. All cells emit discharge light regardless of non-light emission. At this time, the priming auxiliary pulse Pwp is also applied to the column electrode W. This is because the priming assist pulse Pwp is applied to the first row electrode X and the column electrode W so that the electric potential difference between the X-W electrodes is reduced. Is set to a value that is approximately の of the voltage between the X and Y electrodes. When the priming pulse Pxp is applied, XY
A strong discharge occurs between the electrodes, and a large amount of wall charges accumulate between the X and Y electrodes, and the discharge ends.

Next, in the figure, at time b, the priming pulse Pxp falls, and when the voltage applied to the first row electrode X and the second row electrode Y stops, the priming pulse between the X and Y electrodes is applied. An electric field due to the wall charges accumulated at Pxp remains. Since this electric field is large and the discharge can be started again by itself, the discharge occurs again between the X and Y electrodes.
However, since there is no externally applied voltage, the electrons and ions generated by this discharge are not attracted to the row electrodes X and Y,
It is neutralized and disappears.

As described above, all cells are written irrespective of the presence / absence of the wall charge in the previous subfield,
Then, by erasing, the wall charges of the cells on the entire screen can be set to the “absent” state, and the reset is performed. Even when there is no externally applied voltage, the discharge is performed only by the accumulated wall charges, and the discharge in which the wall charges are erased is called a self-erasing discharge.

At the end of the reset period and at time c in the figure, wall charges hardly remain on the first row electrode 4 and the second row electrode 5. On the other hand, a small amount of charged particles generated by the discharge due to the previous entire writing pulse Pxp remains in the discharge cell. The charged particles are for ensuring discharge in the next writing, and serve as a seed for the writing discharge. For this reason, the whole-surface write pulse Pxp is called a priming pulse, and therefore, this method, which combines the priming effect and the erasing effect with one pulse, is considerably required for stable operation of the plasma display panel. This is a good method. In addition, since the erasing by the self-erasing discharge can be performed only by lowering a high voltage pulse, it is a good erasing method for stably operating the AC-PDP.

In the address period, a negative scan pulse Scyp is sequentially applied to the independent second row electrodes Y1 to Yn, and scanning is performed. On the other hand, a positive address pulse Awp is applied to the column electrode W according to the content of the image data. The scan pulse S applied to the second row electrode Y
cyp and the address pulse Awp applied to the column electrode W.
Can select any cell on the screen in a matrix.
Since the total voltage value of the scan pulse Scyp and the address pulse Awp is set to be equal to or higher than the discharge starting voltage between the Y-W electrodes of the cell, the cell to which the scan pulse Scyp and the address pulse Awp are simultaneously applied is the Y-W electrode Discharge occurs between the two.

During the address period, the common first row electrode X is kept at a positive voltage value. Although this voltage value does not discharge between the X and Y electrodes even when summed with the voltage value of the scan pulse Scyp, when a discharge occurs between the Y and W electrodes, this discharge is used as a trigger and at the same time, between the X and Y electrodes. However, the voltage value is set so that discharge occurs. The discharge between the X and Y electrodes that is triggered by the discharge between the Y and W electrodes may be referred to as a write sustain discharge. By this write sustaining discharge, wall charges are accumulated on the first and second row electrodes.

After the scanning of the entire screen is completed, the sustain discharge pulse Sp is applied to the entire screen all at once, and the sustain discharge is performed only in the cells addressed during the address period and storing the wall charges. Then, the next subfield starts again, and the priming pulse Pxp is applied to all the cells in the reset period to perform the reset.

As described above, after all the cells are discharged before each subfield and the wall charges are accumulated in all the cells, the reset for making the wall charges of all the cells “absent” by the self-erasing discharge is performed. While addressing can be performed in a state, light is emitted in each subfield.
In the case of gradation display, discharge occurs at the rise and fall of the entire-surface write pulse. Therefore, 2 × 8 = 16 and 1
Light is emitted at least 16 times in the field, and the brightness of black display increases, resulting in a screen with low contrast.

Since the seeding effect by the above-described whole writing is maintained for a relatively long time, it is not always necessary to perform the seeding effect in each subfield. As a method of suppressing an increase in luminance of black display due to full-surface writing, there is a method of reducing the number of times of full-field lighting per field. FIG.
FIG. 7 is a diagram showing a voltage waveform in one subfield in the driving method of the plasma display disclosed in Japanese Patent Publication No. 766. In FIG. 8, the entire write pulse Pxp applied during the reset period is the same as that of FIG.
Is set to be equal to or higher than the discharge starting voltage between the first and second row electrodes Y, but the pulse width is as short as about 1 μsec.

This driving method uses a priming pulse Px
When there is a wall charge that acts in a form superimposed on p, and when there is no wall charge, when a voltage pulse exceeding the start of discharge is applied, the time from the rise of the pulse to the start of discharge, that is, This is based on the PDP characteristic that a large difference exists in the discharge delay time.
The discharge delay time varies depending on the cell structure and the type of the charged gas, but a typical value is 10 when a wall charge exists.
0 nsec to 600 nsec, and 1.0 μsec or more when there is no wall charge. Therefore, if the pulse width of the priming pulse Pxp is 1 μsec, only the cells that were lit in the immediately preceding subfield can be selectively lit and reset.

Therefore, by using this driving method, for example, in a subfield in one field, the entire writing / resetting is performed by using the driving method with a wide pulse width of the priming pulse Pxp in FIG. The field is selectively turned on / reset by using a driving method with a narrow pulse width of the priming pulse Pxp shown in FIG. 8, so that the number of times of full-field lighting per field can be reduced and the increase in luminance of black display can be suppressed.

Also, in FIG. 8, a cell having a high voltage value for starting discharge even when no wall charge is present and controlling the pulse width to control the subfield in which the entire writing is performed and the cell lit in the immediately preceding subfield. Although only the sub-field for selectively lighting is separated from the sub-field, the above-described separation can be performed by changing the voltage value of the entire-surface write pulse Pxp and setting the voltage so as to exceed the discharge start voltage only in the cell where the wall charge exists. it can. Hereinafter, in this case, it is called an erase pulse Exp, and depending on the pulse width of the erase pulse Exp, it may be called a narrow erase pulse or a wide erase pulse.

For narrow width erasure and wide width erasure,
-Since it is well known to PDP engineers, it will not be described in detail here, but its content is described in, for example, "Plasma Display" (Kenichi Ohwaki et al .: Kyoritsu Shuppan, 1983)
Year issue). The narrow erase pulse is a pulse having a voltage value similar to that of the sustain discharge pulse and a pulse width of about 0.5 μsec. When this pulse is applied, the pulse is interrupted before the progression of the discharge, that is, before the formation of the wall charge of the opposite polarity, so that the wall charge is erased.

[0026]

Here, the priming pulse Pxp in the reset period of one subfield is used.
By changing only the pulse width of the subfield, the subfield for writing and erasing the entire surface and the subfield for selectively lighting and erasing only the cells lit in the immediately preceding subfield are separated, and these two types of subfields are used. A problem in forming one field will be described.

The driving method shown in FIG. 8 utilizes the fact that a difference occurs in the discharge delay time depending on the presence or absence of the wall charge even when the discharge start voltage is applied. Greatly affects the display history of adjacent cells, that is, the state of space charge of adjacent cells. Therefore, a cell which does not have a wall charge and normally takes 1.0 μsec or more to discharge is discharged with a delay time of about 0.6 μsec when an adjacent cell is turned on, and a priming pulse (overall surface) is generated. There was a problem that control could not be performed by dividing only the pulse width of (write pulse) Pxp.

As a result, the contrast was partially reduced. Further, depending on the cell, the discharge is forcibly terminated with an incomplete pulse width, so that the cell has such a wall charge that a self-erasing discharge does not occur. Therefore, there is a problem that it may cause erroneous writing.

When a cell having no wall charge is driven with a pulse width that does not cause a discharge even if it is affected by space charge of an adjacent cell, for example, about 0.6 μsec or less, the wall illuminated in the immediately preceding subfield is not lit. The cell in which the charge exists cannot be controlled due to the variation. In other words, some of them are not discharged at all, and even if they are discharged, they have wall charges to such an extent that self-erasing discharge does not occur.

Further, a driver IC for supplying the column electrode W
Is determined by the priming auxiliary pulse Pwp, and the priming auxiliary pulse Pwp
However, when the priming assist pulse Pwp is reduced, the discharge between the X-W electrodes increases, and a large amount of wall charges are accumulated on the column electrodes W. Although there is no problem in itself, the priming pulse P
If the pulse width xp is different, the amount of wall charges accumulated on the column electrode W is different, the operating point is different depending on the type of subfield, and the margin is narrowed.

Next, by changing the voltage value of the priming pulse Pxp in the reset period of one subfield, only the subfield for lighting and erasing the entire surface and the cell lit in the immediately preceding subfield are lit and erased. A problem in a case where a subfield is separated from the subfield and one field is formed using these two types of subfields will be described.

According to this method, since the voltage is set so that the sum of the wall charge and the externally applied voltage exceeds the discharge starting voltage, the cell having no wall charge is reliably discharged without any discharge at all. Fields can be separated. However, there is a difference between the reset using the self-erasing discharge and the reset using the narrow or wide erasing, in the state of the wall charges after the erasing.

When the priming pulse Pxp is applied, the column electrode W participates in the discharge, and the column electrode W is in a state where wall charges are accumulated. However, when the erasing pulse Exp is applied, the potential difference between the X-W electrodes hardly disappears, and the column electrodes W do not participate in the discharge at all. Accordingly, no wall charge is accumulated on the column electrode W, and the state of the wall charge on both column electrodes W is different, so that there is a problem that control cannot be performed with the same voltage value during the address period. .

In order to prevent the column electrode W from participating in the discharge when the priming pulse Pxp is applied, the voltage of the priming auxiliary pulse Pwp is set to Pxp /
2 and the withstand voltage of the driver IC supplied to the column electrode W must be increased.

The present invention has been made in order to solve the above-mentioned problems, and a plasma having one field composed of two types of subfields, that is, a subfield for performing full writing and a subfield for performing erasing. In the display driving method, even if a difference occurs in the amount of remaining wall charges due to the difference between the resets of the two types of subfields, the operating point in the address period can be made equal and the reduction of the margin can be suppressed. The purpose is to obtain.

[0036]

In order to achieve the above object, a method of driving a plasma display panel according to the present invention comprises the steps of: forming a first substrate covered with a dielectric layer on a first substrate; A plurality of displays formed in a matrix by arranging third electrodes intersecting the first and second electrodes on a second substrate arranged in parallel with the first substrate. A method for driving a plasma display including cells, comprising: a reset period for erasing wall charges accumulated on the dielectric layer in each subfield obtained by dividing one field for image display into a plurality of fields; An address period in which a discharge is generated between the first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell to be stored to accumulate wall charges on the dielectric layer; The first electrode and the second And a sustain discharge period in which sustain discharge using the wall charge accumulated in the dielectric layer at the machining gap,
In addition, the one field includes the first field during the reset period.
A priming pulse having a predetermined voltage value and a pulse width for discharging all the display cells is applied between the first electrode and the second electrode between the first electrode and the second electrode. A first priming assist pulse for generating a weak discharge between the electrodes is applied to turn on all the cells, and then at least a wall charge between the first electrode and the second electrode is erased. In the subfield of the type and the reset period, between the first electrode and the second electrode,
An erasing pulse having a voltage value and a pulse width for discharging only the cell discharged in the previous subfield is applied, and the first electrode or the second electrode is applied to the third electrode.
An erasing auxiliary pulse for generating a weak discharge between the electrodes is applied to discharge only the cells discharged in the previous subfield, and at least the wall charges between the first electrode and the second electrode are reduced. In a method for driving a plasma display panel having at least two types of sub-fields including a second type of sub-field to be erased, the first electrode or the second type in the address period of the first type of sub-field. A first potential difference between an electrode and the third electrode, and a first potential difference between the first electrode or the second electrode and the third electrode during an address period of the second type of subfield. 2 is different from the potential difference of (2).

Further, the present invention is characterized in that the first potential difference is made smaller than the second potential difference.

Further, the voltage applied to the first electrode or the second electrode is equalized, and only the voltage applied to the third electrode is changed.

Further, the voltage applied to the third electrode is equalized, and the voltage applied to the first electrode or the second electrode is changed.

The voltage of the erase pulse applied during the reset period of the second type of subfield is equal to the voltage of the sustain discharge pulse applied to the first electrode or the second electrode during the sustain discharge period. It is characterized by being equal.

The voltage of the erase pulse applied during the reset period of the second type of subfield is equal to the voltage value of the first pulse applied during the reset period of the first type of subfield. It is characterized by the following.

According to another aspect of the present invention, there is provided a method for driving a plasma display panel, wherein first and second electrodes covered with a dielectric layer are provided side by side on a first substrate. The first and second substrates are placed on a second substrate which is disposed to face
A driving method for a plasma display having a plurality of display cells formed in a matrix by arranging a third electrode that intersects a plurality of sub-electrodes, wherein one field for displaying an image is divided into a plurality of sub-fields. A reset period for erasing wall charges accumulated on the dielectric layer in a field; and a first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell selected in a matrix. Between the first electrode and the second electrode by using the wall charge accumulated on the dielectric layer, and an address period in which a discharge is caused during the period to accumulate wall charges on the dielectric layer. And a sustain discharge period for performing a sustain discharge is performed, and the one field includes a predetermined voltage value for discharging all display cells between the first and second electrodes during a reset period. Priming with pulse width And applying a priming auxiliary pulse to the third electrode to cause a weak discharge between the first electrode or the second electrode to light all the cells. A first device for eliminating wall charges between the first electrode and the second electrode.
In the subfield of the type and the reset period, the first
Between the first electrode and the second electrode, an erasing pulse having a voltage value and a pulse width for discharging only the cell discharged in the previous subfield is applied, and the first electrode is applied to the third electrode. Alternatively, an erasing assist pulse for generating a weak discharge between the second electrodes is applied to discharge only the cells that have been discharged in the previous subfield, and at least between the first electrodes and the second electrodes In a method of driving a plasma display panel having at least two types of sub-fields, the second type of sub-fields and the second type of sub-fields, the first type of sub-field is provided for the third electrode. If the voltage value of the priming assist pulse applied during the reset period of the second type is different from the voltage value of the erase assist pulse applied during the reset period of the second type subfield, And it is characterized in Rukoto.

Further, a voltage value of the erasing auxiliary pulse applied during a reset period of the second type of subfield is smaller than a voltage value of the priming auxiliary pulse.

The voltage value of the erase assist pulse applied during the reset period of the second type of subfield is not more than a GND level.

The voltage of the erasing pulse applied during the reset period of the second type of subfield is a voltage value of the sustain discharge pulse applied to the first electrode or the second electrode during the sustain discharge period. It is characterized by being equal to

Further, the voltage of the erase pulse applied during the reset period of the second type of subfield is equal to the voltage value of the priming pulse applied during the reset period of the first type of subfield. It is assumed that.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a partial cross-sectional view of a cell of a surface discharge type plasma display panel to which the method for driving a plasma display panel according to Embodiment 1 of the present invention is applied. As shown in FIG. 1, the display cell of the surface discharge type plasma display panel 1 is configured as follows.
That is, the front glass substrate 2 serving as a display surface and the rear glass substrate 3 are arranged to face each other with the discharge space interposed therebetween, and the first row electrode 4 (Xi) is provided on the front glass substrate 2 as a row electrode.
And a second row electrode 5 (Yi). A dielectric layer 6 is provided on the row electrodes 4 and 5, and a MgO layer is further provided thereon.
(Magnesium oxide) 7 is formed.

A column electrode 8 (Wj) is provided on a rear glass substrate 3 facing the front glass substrate 2 so as to be orthogonal to the row electrodes 4 and 5 (Xi, Yi). The body layer 9 is formed. Partition walls 10 for separating the discharge cells are formed between the column electrodes 8, and the discharge space between the front glass substrate 2 and the rear glass substrate 3 of each discharge cell separated by the partition walls 10 is Ne−. A discharge gas such as a Xe mixed gas or a He-Xe mixed gas is sealed.

FIG. 2 is a timing chart of voltage waveforms for explaining a method of driving the plasma display panel according to the first embodiment of the present invention. In FIG. 2, the voltage waveforms are, in order from the top, a column electrode Wj, a first row electrode Xi, and a second row electrode Xi.
Is a voltage waveform applied to the row electrode Yi. Also, the first
The subfield A of the type includes a priming pulse (full write pulse) P for performing full write and full erase.
xp is a subfield applied to the first row electrode Xi;
The second type of subfield B is a subfield in which an erase pulse Exp for erasing wall charges is applied to the first row electrode Xi. Pwp is the priming pulse P
a priming assist pulse applied to the column electrode Wj at the same timing as xp, Ewp an erasing assist pulse pulse applied to the column electrode Wj at the same timing as the erase pulse Exp,
Sp is a sustain discharge pulse for performing sustain discharge, Scyp is a scan pulse for scanning, and Awp-A and Awp-B are address pulses applied in accordance with the display data contents of subfields A and B, respectively.

In the first embodiment, for example, the priming pulse Pxp has a pulse width of 7 μsec and a voltage of 3 μs.
10 V, the priming assist pulse Pwp has a voltage of 15
0 V, the erase pulse Exp has a pulse width of 0.5 μsec.
Thus, the voltage is 150 V, the erase assist pulse Ewp is 150 V, the sustain discharge pulse Sp is 180 V,
The voltage of the scan pulse Scp is set to -180 V, and the address pulse Awp-A and the address pulse Awp-
B is set so that the voltage is different between 60V and 80V, respectively.

Next, the operation will be described. In the first embodiment, one field corresponds to the priming pulse P.
A description will be given of a configuration including a first type of subfield A having xp and a second type of subfield B having the erasing pulse Exp. The subfields A and B need not be executed in order with respect to each other, but may be executed in any order. Also, the number of subfields A and the number of subfields B in one field are not necessarily equal, and the number of subfields A is set to 1 and the number of subfields B is set to 7 times.
The total subfield of the field may be eight.
This total number of subfields is also arbitrary.

In the subfield A, when the priming pulse Pxp is applied to the first row electrode Xi, the priming pulse Pxp is applied between the first row electrode Xi and the second row electrode Yi regardless of whether the previous subfield is turned on or off. Discharge occurs at Then, a large amount of wall charges accumulate between the two row electrodes, and the discharge stops. At this time, a priming assist pulse Pwp for weakening the discharge with the row electrode Xi is also applied to the column electrode Wj. When the priming assist pulse Pwp has a voltage value that is half of the priming pulse Pxp, the discharge is minimal, and the amount of wall charges accumulated on the column electrode Wj is the smallest.
If the priming assist pulse Pwp exceeds half the voltage value of the priming pulse Pxp, a discharge occurs between the column electrode Wj and the second row electrode Yi, which has an adverse effect. For this reason, it is desirable that the voltage value of the priming auxiliary pulse Pwp be Pwp = Pxp / 2.
Considering the withstand voltage of the IC that supplies the voltage to the column electrode Wj,
Actually, the voltage of the priming assist pulse Pwp is about 150 V at the maximum. Naturally, the smaller the voltage of the priming auxiliary pulse Pwp is, the better the circuit configuration is.

Next, when the priming pulse Pxp falls and all the electrodes become 0 V, a self-erasing discharge is generated only by the wall charges accumulated between the two row electrodes, and the wall charges are extinguished. The wall charges on the column electrodes Wj also decrease, but cannot be completely eliminated. This remaining amount is defined by the voltage value of the priming assist pulse Pwp. That is, when the voltage of the priming auxiliary pulse Pwp is low and a large amount of wall charges are accumulated on the column electrode Wj at the rise of the pulse, the remaining amount is large, and the voltage of the priming auxiliary pulse Pwp is Pxp / 2.
In the case where almost no wall charge is accumulated on the column electrode Wj in the vicinity of the voltage, there is almost no remaining amount.

In the address period, the scan pulse S
cyp and the address pulse Awp-A are applied to the first row electrode X.
i and the cell selected from the cells arranged in a matrix and applied to the column electrode Wj, a discharge occurs between the first row electrode Xi and the column electrode Wj, and the first row electrode X
address sustain discharge also occurs between i and the second row electrode Yi,
A wall charge is formed on the first and second row electrodes. At this time, the potential difference between the first row electrode Xi and the column electrode Wj is 240
V (= 60V − (− 180V)), but actually, the priming pulse Pxp (priming auxiliary pulse Pw
Since the wall charges on the column electrodes Wj remaining at the fall of p) are also superimposed, a potential difference of about 260 V is applied between the gaps. Cells not selected by the scan pulse Scyp and the address pulse Awp-A do not form wall charges.

After scanning all the cells during the address period and accumulating wall charges in any cells, when the sustain discharge period starts,
The sustain discharge pulse Sp is applied to all the cells. At this time, the cells in which the wall charges are formed perform the sustain discharge, and the cells in which the wall charges are not formed do not perform the sustain discharge.

When the sustain period of the first type subfield A ends and the reset period of the second type subfield B ends, an erase pulse Exp is applied. Since the erase pulse Exp has a low voltage value of 150 V, only the cell that emitted light in the immediately preceding subfield is discharged to erase the wall charges. On the other hand, cells that did not emit light in the previous subfield are not affected. As a result, there is no wall charge in all cells again, and reset is performed. Further, since the voltage value of the erase pulse Exp is low, the column electrode Wj and the first
Does not occur with the row electrode Xi, and no wall charge is accumulated on the column electrode Wj.

In the address period of subfield B, the same operation as in subfield A is performed. However, since the wall charges are not accumulated on the column electrode Wj, the operating voltage differs from that of the subfield A. Therefore, the address pulse Aw
At pB, 80 V higher than the address pulse Awp-A by 20 V is applied, and the potential difference between the row electrode Xi and the column electrode Wj becomes 260 V (= 80 V-(-180 V)). Thus, the potential difference between the gaps estimated on the column electrode Wj in the subfield A is equal to 260 V, and the same operation as in the subfield A can be performed. The subsequent sustain period is the same operation as in the subfield A.

As in the first embodiment, the amount of wall charges accumulated on column electrode Wj during the reset period in subfields A and B is estimated, and address pulses Axp-A, Axp-A applied during the address period are estimated. By independently controlling B, the operating points in the two types of subfields A and B can be equalized, and the margin can be widened.

In the first embodiment, the voltage of the erasing pulse Exp is set to 150 V. However, the voltage of the priming pulse Pxp may be set equal to the voltage of the priming pulse Pxp, and the pulse width may be reduced to about 0.5 μsec. Also in this case, subfield A
And column electrode Wj in the reset period of subfield B
Since the upper accumulated wall charges are different, as in the first embodiment, by controlling the voltage value in the address period in each of the two types of subfields, the operating points can be equalized and the margin can be increased. . In addition, the voltage of the erase pulse Exp may be made equal to the sustain discharge pulse Sp. It goes without saying that such a setting simplifies the circuit configuration.

Embodiment 2 Next, FIG.
6 is a timing chart of voltage waveforms for explaining a method of driving the plasma display panel according to the first embodiment. In the first embodiment described above, the address pulses Awp-A and Awp-B
And sub-field A
And the operating point of the subfield B are equal, but in the second embodiment, the address pulse Awp is common,
By making the voltage values of the scan pulses Scyp-A and Scyp-B different in the subfields A and B, the operating points in the two types of subfields are made equal. For example, the voltage of the scan pulse Scyp-A in the subfield A is -180 V, and the voltage of the scan pulse Scyp-B in the subfield B is-.
200V. As a result, the margin can be increased as in the first embodiment.

In the first embodiment, the voltage value of the address pulse Awp-A and the voltage value of the address pulse Awp-B depend on whether or not there is data.
There is a difference between 80V and 0V in the subfield B. However, in the second embodiment, the data is 60 V in both subfields. Therefore, the first embodiment is more advantageous as a margin in consideration of erroneous writing. However, in the second embodiment,
Since the data is always 60 V or 0 V, the power loss can be smaller than in the first embodiment.

Embodiment 3 Next, FIG.
6 is a timing chart of voltage waveforms for explaining a method of driving the plasma display panel according to the first embodiment. In the driving method of the plasma display panel according to the third embodiment shown in FIG. 4, priming pulse Pxp has a voltage of 310 V
The priming assist pulse Pwp has a voltage of 150 V
The erase pulse Exp has a voltage of 180 V, the erase assist pulse Ewp has a voltage of 20 V, the sustain pulse Sp has a voltage of 180 V, and the scan pulse Scyp has a voltage of -180.
V and the voltage of the address pulse Awp is set to 60 V, respectively.

The subfield A is the same as in the first and second embodiments. In the reset period in the subfield B, the priming pulse Pxp (= 310
V), the voltage of the erasing pulse Exp (= 180 V) is lower, but the voltage of the erasing auxiliary pulse Ewp (= 20 V) is also lower, so that it is applied to the row electrode Xi and the column electrode Wj in the subfields A and B. Potential difference (310V
(−150V = 180V−20V = 160V) are equal.
Therefore, the amount of wall charges on the column electrode Wj after the reset period is equal to that in the subfield A. Therefore,
In the address period, discharge can occur at the same operating point without changing the applied voltage depending on the type of subfield.

In the third embodiment, the potential difference between row electrode Xi and column electrode Wj during the reset period of subfield A and row electrode X during the reset period of subfield B
Although the erasing auxiliary pulse Ewp is set so that the potential difference between i and the column electrode Wj becomes equal, it is not always necessary to configure the auxiliary erasing pulse Ewp so that it equals the potential difference between the column electrode Wj and the column electrode Wj at the end of the reset period of the subfield A. It suffices that the remaining wall charge amount and the remaining wall charge amount on the column electrode Wj at the end of the reset period of the subfield B become equal.
Therefore, the erase assist pulse Ewp may be set to be equal to or lower than the GND level.

In the third embodiment, the erase pulse E
Although the voltage of xp is set to 180 V, it may be equal to the voltage value of the priming pulse Pxp. The effect in this case is the same as that described in the first embodiment. Further, the voltage value of the erase pulse Exp may or may not be equal to the sustain pulse Sp. However, it is needless to say that the circuit configuration can be simplified by using the same voltage value.

Furthermore, the voltage of the priming assist pulse Pwp is set to a high value of 150 V in common with the first, second and third embodiments. According to the driving method of (1), even if the amount of the residual wall charges on the column electrode Wj is large, the operating points in the address period of the subfield A and the subfield B can be set equally, so that the setting of the priming auxiliary pulse Pwp The voltage value can be reduced, and the withstand voltage of the driver IC supplied to the column electrode Wj can be reduced.

Further, in common with the first and second embodiments, the potential difference between the row electrode Yi and the column electrode Wj in the address period is smaller in the subfield A and larger in the subfield B. This is because a voltage of Pxp / 2> Pwp is applied to the column electrode Wj during the reset period in the subfield A. Assuming that Pxp / 2 <P
When a voltage of wp is applied, negative wall charges are accumulated on the column electrode Wj. In this case, the potential difference between the row electrode Yi and the column electrode Wj in the address period must be larger in the subfield A and smaller in the subfield B. Further, erroneous writing can be prevented by applying an address pulse in a state where a reverse charge is applied. However, the withstand voltage of the driver IC that supplies a voltage to the column electrode Wj must be increased.

Similarly, in the third embodiment, Pwp>
Ewp is indicated because there is a relationship of Pxp / 2> Pwp. Considering that Pxp / 2 <Pwp allows negative wall charges to be accumulated on the column electrode Wj to prevent erroneous writing, Pwp <Ewp. However, as described above, there is a problem that the withstand voltage of the driver IC that supplies the voltage to the column electrode Wj increases.

[0069]

As described above, according to the driving method of the plasma display panel according to the present invention, the distance between the first electrode or the second electrode and the third electrode during the address period in the first type of subfield is obtained. By making the first potential difference different from the second potential difference between the first or second electrode and the third electrode in the address period in the second type subfield, 1
Even if the field is configured, it is possible to drive the device under the same operating conditions, and as a result, it is possible to widen the margin. Further, since the voltage value of the address period can be set arbitrarily regardless of the state of the wall charge at the end of the reset period for each subfield, the voltage value of the priming assist pulse applied to the third electrode can be reduced, and Can be reduced.

Further, by driving under the condition that the first potential difference is smaller than the first potential difference and the second potential difference,
The withstand voltage of the driver IC supplied to the third electrode can be reduced.

Further, the first potential difference and the second potential difference are made different by equalizing the voltage applied to the first electrode or the second electrode and changing only the voltage applied to the third electrode. In addition, erroneous writing can be prevented and the margin can be widened.

Further, the first potential difference and the second potential difference can be made different by changing the voltage applied to the first electrode or the second electrode so that the voltage applied to the third electrode is equal. , Power loss can be reduced.

Further, by making the voltage of the erasing pulse applied during the reset period of the second type of subfield equal to the voltage applied to the first electrode or the second electrode during the sustain discharge period, the circuit configuration can be improved. It can be simplified.

The voltage of the erasing pulse applied during the reset period of the second type of subfield is made equal to the voltage of the priming pulse applied during the reset period of the first type of subfield. Can be simplified.

Further, the voltage value of the priming auxiliary pulse applied during the reset period of the first type subfield is different from the voltage value of the erase auxiliary pulse applied during the reset period of the second type subfield. Thereby, the state of wall charges at the end of the reset period in each subfield can be equalized, addresses can be addressed at the same operating point, and the margin can be widened.

Further, by driving the voltage value of the erasing auxiliary pulse applied during the reset period of the second type subfield under a condition smaller than the voltage value of the priming auxiliary pulse, the driver IC for supplying the third electrode can Withstand voltage can be reduced.

The voltage value of the erase assist pulse applied during the reset period of the second type subfield is GN.
When the level is equal to or lower than the D level, the voltage value of the priming assist pulse applied during the reset period of the first type of subfield can be reduced, and the withstand voltage of the driver IC supplied to the third electrode can be reduced.

Further, by making the voltage of the erase pulse applied during the reset period of the second type subfield equal to the voltage applied to the first electrode or the second electrode during the sustain discharge period, the circuit configuration can be simplified. Can be

Further, the voltage of the erase pulse applied during the reset period of the second type of subfield is changed to the first type.
The circuit configuration can be simplified by making the voltage equal to the voltage of the priming pulse applied in the reset period of the type subfield.

[Brief description of the drawings]

FIG. 1 is a diagram showing a surface discharge type AC-applied with a driving method of a plasma display panel according to each embodiment of the present invention.
It is sectional drawing of the cell of PDP.

FIG. 2 is a voltage waveform diagram showing a method for driving the plasma display panel according to Embodiment 1 of the present invention.

FIG. 3 is a voltage waveform diagram showing a method for driving a plasma display panel according to Embodiment 2 of the present invention.

FIG. 4 is a voltage waveform diagram showing a method for driving a plasma display panel according to Embodiment 3 of the present invention.

FIG. 5 is a perspective view showing a general surface discharge type plasma display panel.

FIG. 6 is a configuration diagram of one field when performing gradation display in a normal AC type plasma display panel.

FIG. 7 is a voltage waveform diagram in one subfield showing a method of driving a plasma display panel according to a first conventional example.

FIG. 8 is a voltage waveform diagram in one subfield showing a method of driving a plasma display panel according to a second conventional example.

[Explanation of symbols]

Reference Signs List 1 plasma display panel, 2 front glass substrate, 3 back glass substrate, 4 first row electrode (X electrode), 5 second row electrode (Y electrode), 6 dielectric layer, 7
MgO (magnesium oxide), 8 row electrodes, 9 phosphor layers, 10 barrier ribs, Pxp priming pulse (full writing pulse), Pwp priming auxiliary pulse,
Exp erase pulse, Exp erase auxiliary pulse, Aw
p, Awp-A, Awp-B Address pulse, Sp
Sustain pulse, Scyp, Scyp-A, Scyp-B
Scan pulse.

Claims (11)

[Claims] A first substrate covered with a dielectric layer on a first substrate;
And a second electrode arranged side by side, and a third electrode intersecting the first and second electrodes is arranged on a second substrate facing the first substrate in a matrix. A method for driving a plasma display including a plurality of display cells to be formed, wherein wall charges accumulated on the dielectric layer are erased in each subfield obtained by dividing one field for image display into a plurality of fields. During a reset period, a discharge is caused between the first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell selected in a matrix to accumulate wall charges on the dielectric layer. An address period, and a sustain discharge period in which a sustain discharge is performed between the first electrode and the second electrode using wall charges accumulated on the dielectric layer, and the one field includes: During the reset period, the first and second A priming pulse having a predetermined voltage value and a pulse width for discharging to all display cells is applied between the poles, and the third electrode is slightly weakened between the first electrode or the second electrode. Priming auxiliary pulse to cause
After all the cells are turned on, at least a first type of subfield in which wall charges between the first electrode and the second electrode are erased, and the first electrode and the first electrode are reset during a reset period. An erase pulse having a voltage value and a pulse width for discharging only the cells discharged in the previous subfield is applied between the second electrodes, and the first electrode or the second electrode is applied to the third electrode. An erasing auxiliary pulse for generating a weak discharge between the electrodes is applied to discharge only the cells discharged in the previous subfield, and at least the wall charges between the first electrode and the second electrode are reduced. In a method for driving a plasma display panel having at least two types of sub-fields including a second type of sub-field to be erased, the method comprises the steps of: A first potential difference between the first electrode or the second electrode and the third electrode, and the first electrode or the second electrode during an address period of the second type of subfield. A method for driving a plasma display panel, wherein a second potential difference between an electrode and the third electrode is made different. 2. The method according to claim 1, wherein the first potential difference is smaller than the second potential difference. 3. The voltage applied to the first electrode or the second electrode is equalized, and only the voltage applied to the third electrode is changed.
Or the driving method of the plasma display panel according to 2. 4. The plasma according to claim 1, wherein the voltage applied to the third electrode is equalized, and the voltage applied to the first electrode or the second electrode is changed. Display panel driving method. 5. The voltage of the erase pulse applied during a reset period of the second type of subfield is equal to the voltage of a sustain pulse applied to the first electrode or the second electrode during a sustain discharge period. 5. The method of driving a plasma display panel according to claim 1, wherein: 6. The voltage of the erase pulse applied during a reset period of the second type of subfield is equal to the voltage of the first type.
5. The method of driving a plasma display panel according to claim 1, wherein the voltage value is equal to a voltage value of a first pulse applied during a reset period of a type of subfield. 7. A first substrate covered with a dielectric layer on a first substrate.
And a second electrode arranged side by side, and a third electrode intersecting the first and second electrodes is arranged on a second substrate facing the first substrate in a matrix. A method for driving a plasma display including a plurality of display cells to be formed, wherein wall charges accumulated on the dielectric layer are erased in each subfield obtained by dividing one field for image display into a plurality of fields. During a reset period, a discharge is caused between the first electrode or the second electrode and the third electrode corresponding to an arbitrary display cell selected in a matrix to accumulate wall charges on the dielectric layer. An address period, and a sustain discharge period for performing a sustain discharge between the first electrode and the second electrode using a wall charge accumulated on the dielectric layer, and performing a sustain discharge. One field, during the reset period, A priming pulse having a predetermined voltage value and a pulse width for discharging all display cells is applied between the first and second electrodes, and the first electrode or the third electrode is applied to the third electrode. Applying a priming auxiliary pulse between the two electrodes to generate a weak discharge,
After all the cells are turned on, at least a first type of subfield in which wall charges between the first electrode and the second electrode are erased, and the first electrode and the first electrode are reset during a reset period. An erase pulse having a voltage value and a pulse width for discharging only the cells discharged in the previous subfield is applied between the second electrodes, and the first electrode or the second electrode is applied to the third electrode. An erasing auxiliary pulse for generating a weak discharge between the electrodes is applied to discharge only the cells discharged in the previous subfield, and at least the wall charges between the first electrode and the second electrode are reduced. In a method of driving a plasma display panel having at least two types of sub-fields including a second type of sub-field to be erased, the first type of sub-field is provided with respect to the third electrode. The driving method of a plasma display panel, characterized in that varying the voltage value of the erase auxiliary pulse applied to the voltage value and the reset period of subfields of the first second type of priming the auxiliary pulse applied in the reset period of the field. 8. The plasma display panel according to claim 7, wherein a voltage value of the erasing auxiliary pulse applied during a reset period of the second type of subfield is smaller than a voltage value of the priming auxiliary pulse. Drive method. 9. The voltage value of the erase assist pulse applied during a reset period of the second type of subfield is G
9. The driving method for a plasma display according to claim 8, wherein the driving voltage is equal to or lower than an ND level. 10. The voltage of the erase pulse applied during a reset period of the second type of subfield is equal to the voltage value of a sustain pulse applied to the first electrode or the second electrode during a sustain discharge period. 8. The method according to claim 7, wherein
10. The method for driving a plasma display panel according to any one of claims 9 to 9. 11. The erasing pulse voltage applied during the reset period of the second type subfield is equal to the voltage value of the priming pulse applied during the reset period of the first type subfield. The method for driving a plasma display panel according to any one of claims 7 to 9, wherein