JPH11353887A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which a read and write operation can be performed in a short time. SOLUTION: The nonvolatile semiconductor memory is provided with a memory array which comprises a plurality of blocks, a status register in which first data indicating the state of the memory array, a block status register 210 in which second data indicating the state of one out of the plurality of blocks is stored, and a control circuit which controls the output of the first data and the second data to a data bus 212. The number of bits of the data bus 212 is equal to, or larger than, the number in which the number of bits of the first data and the number of bits of the second data are added. The control circuit controls the output of the first data and the second data to the data bus 212 in such a way that the first data and the second data are outputted simultaneously to the data bus 212.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device used for a computer or a portable information device. More specifically, the present invention relates to a memory capable of electrically writing and erasing data and a configuration and an operation method of a status register and a block status register corresponding to the memory. In particular, the function of the memory array for two chips
The present invention relates to a nonvolatile semiconductor memory device having a configuration integrated on one chip (a structure called a dual work), having a bus of 16 bits or more, and having a status register and a block status register.

[0002]

2. Description of the Related Art One of conventional nonvolatile memories is an EPR.
There is OM (Erasable Programmable Read-Only memory). In the EPROM, data can be written on the user side, but when erasing data, data in all memory arrays is erased collectively by irradiating ultraviolet rays. Therefore, every time data is rewritten, the EPROM
It was necessary to remove the material from the base.

The above-mentioned EPROM has a small memory cell area and is suitable for integrating a large capacity, but requires a package with a window to erase data by irradiating ultraviolet rays, and requires a programmer (or writer). In order to perform writing by a writing device called, it is necessary to remove the EPROM from the system at the time of writing.

On the other hand, a conventional EEPROM can electrically rewrite data in a system. However, since the memory cell area is about 1.5 to 2 times that of the EPROM, the price is high and the capacity is large. Accumulation was technically difficult.

Therefore, recently, a flash memory (or flash EEPROM) has been used as an intermediate storage device between them.
M) was developed. This flash memory is a nonvolatile semiconductor memory device having a function of electrically erasing data in the entire chip or in a certain area of memory cells (called sectors or blocks) collectively. It can be as small as an EPROM. A memory cell of such a flash memory is disclosed, for example, in US Pat. 5249158,
U.S. Pat. 5245570.

FIG. 5 shows a memory cell 3 of a conventional flash memory.

The memory cell 3 has a floating gate type field effect transistor structure. A source 302 and a drain 303 are formed in a substrate 301, and a source 302 and a drain 303 are formed.
A floating gate 304 and a control gate 305 are formed in an upper portion between the gates 303 and 303. In such a flash memory, 1
Since a 1-bit (1 cell) memory can be constituted by the elements, a high degree of integration can be easily realized.

To write data into a memory cell, about 12 V is applied to the control gate electrode, about 7 V to the drain, and 0 V to the source.
A voltage of V is applied, and hot electrons generated near the drain junction are injected into the floating gate electrode. When data is written to a cell, the threshold voltage as viewed from the control gate electrode of the memory cell increases.

As shown in FIG. 5, a memory cell having a floating gate type field effect transistor structure has one
If the element is configured to be able to store multi-valued data (a value obtained by subdividing the value of the threshold voltage _Vth of the memory cell and expressing data of 2 n at intervals of several hundred mV), it is more advanced. Integration can be realized.

To write data to a memory cell, a source
Voltage to 0V, about 12V to the control gate electrode, and to the drain
A pulse of about 7 V for several microseconds is applied to the drain junction.
Hot electrons generated in the vicinity of
Inject into the pole. By writing to the cell, the memory cell
The threshold voltage as seen from the control gate electrode increases. V _th
To control the voltage of the control gate electrode
Or by changing the drain voltage.
Can also be implemented by changing the pulse width.
Wear.

On the other hand, to erase data, the control gate electrode is grounded, and a high positive voltage (about 12 V) is applied to the source. As a result, a high electric field is generated between the floating gate electrode and the source, and a tunnel phenomenon occurs through the thin gate oxide film. Using this tunnel phenomenon, electrons accumulated in the floating gate electrode are extracted to the source, and data can be erased. To erase data, you need to block
In general, data is erased in units of 16 Kbytes or 64 Kbytes. When data is erased, the threshold voltage seen from the control gate electrode becomes lower (the data value becomes "1"). At this time, since the memory cell does not have a select transistor, a negative threshold voltage (excessive erasure) causes a fatal operation failure (operation failure in which correct data cannot be read at the time of reading). ).

For reading, a low voltage of about 0 V is applied to the source and about 1 V to the drain, and a voltage of about 5 V is applied to the control gate. The magnitude of the channel current flowing at this time is "1" of information. Data is read out using the fact that it corresponds to “0”. The reason for setting the drain voltage to a low voltage is to prevent a parasitic weak writing operation (soft write) from occurring.

To read out multi-valued storage data,
Data reading is realized by applying a low voltage of about 0 V to the source and about 1 V to the drain, changing the voltage applied to the control gate, flowing a channel current, and utilizing the change in the voltage of the control gate electrode.

As described above, in the memory cell, writing is performed on the drain side and erasing is performed on the source side. Therefore, it is desirable to individually optimize a junction profile so as to be suitable for each operation. That is, since the source and the drain have an asymmetric structure, an electric field concentration type profile is used at the drain junction to increase the writing efficiency, and an electric field relaxation type profile that can apply a high voltage is used at the source junction.

When erasing data, a high voltage is applied to the source. At this time, the breakdown voltage of the source junction must be increased. For this reason, there is a problem that it is difficult to miniaturize the source electrode side and a problem that hot holes are generated near the source and a part thereof is trapped in the tunnel insulating film, thereby lowering cell reliability. Therefore, as another example of the data erasing method, there is a method called negative gate erasing. In the negative gate erase, a negative voltage (about -10 V) is applied to the control gate,
A power supply voltage (about 5 V) is applied to the source, and data is erased by a tunnel current. In this method, since the voltage applied to the source at the time of data erasing is low, there is an advantage that the junction breakdown voltage on the source side may be low and the gate length of the cell can be reduced. There is also an advantage that the data erase block size can be easily reduced by using the negative gate erase method. This method is called sector erase.

In a data erasing method in which a high electric field is applied to the source, a tunnel current flows between the bands, and the current value is several mA in the entire chip. For this reason, it is difficult to use a booster circuit. Therefore, conventionally, the high voltage V _PP for erasing was supplied from outside the chip. The negative gate erase method has an advantage that it is relatively easy to operate the device with a single power supply because the power supply voltage V _CC (5 V or 3 V) can be supplied to the source.

In the method using hot electrons for data writing, a current of about 1 mA flows per cell at the time of writing. Therefore, similarly to a conventional EEPROM, the current flowing per cell at the time of data writing is obtained by using an FN tunnel current. Some flash memories are configured to reduce the number. 2. Description of the Related Art As semiconductor processes have become finer and portable devices driven by batteries have become widespread, there is a demand for operating power supplies to be as low as possible. Therefore, 5
A product that performs a single operation at 3.3 V instead of a single operation at V is demanded and is being developed.

When data is read with a 3.3 V power supply (V _CC ), in the current flash EEPROM, data is read by applying a power supply potential (V _CC = 3.3 V) to a control gate line (word line). Alternatively, in order to realize a further high-speed operation and to expand an operation margin, data is read by applying an internally boosted voltage of about 5 V.

In such a nonvolatile semiconductor memory device,
Compared to a RAM (random access memory) in which writing and reading can be performed in a short time, there are many operating states (writing, block erasing, all-chip erasing, reading of a status register, and the like). Even if a large number of operating states are to be made to correspond to a combination of external control signals (/ CE, / WE, / CE, etc.), the conventional EPROM, EEP
The control signals in the ROM are not enough and new control signals need to be added. As a result, the usability is deteriorated. As shown in 5053990, a method of inputting and controlling a command without increasing the number of control signal lines has been devised, and is currently being implemented as the mainstream.

In this nonvolatile semiconductor memory device, the command input by the user is a command state machine (C
The circuit enters a circuit for recognizing a command called SM), and a write state machine (WSM) executes an operation (such as erasing / writing) corresponding to the command. In the existing flash memory, when the write state machine is executing a command, if the control signal level of / CE / OE is set to “LOW” to perform a read operation, the status register (SR) is not stored in the memory array but the data is stored. Will be read out. Even when the 16-bit data bus is used, the data indicating the status of the status register is output to the lower 8-bit bus without using the upper 8-bit data bus, regardless of the specified address.

FIG. 6 shows a conventional status register (S
R) shows the data stored.

The seventh bit of the status register stores a bit (WSSMS bit) indicating a write state machine state. A value “1” of the WSMS bit indicates a ready state, and a value “0” indicates a busy state. In the sixth bit of the status register, a bit (ESS bit) indicating an erase suspended state is stored. The value “1” of the ESS bit indicates the erase suspended state, and the value “0” indicates the erased state / erase completed state. The fifth bit of the status register stores a bit (ES bit) indicating an erased state. The value “1” of the ES bit indicates a block erase error state, and the value “0” indicates a block erase successful state. The fourth bit of the status register stores a bit (DWS bit) indicating a data write state. A value “1” of the DWS bit indicates a data write error state, and a value “0” indicates a data write success state.
In the third bit of the status register, a bit indicating the VPP state (VPPS bit) is stored. VPP
The value “1” of the S bit indicates the VPP low potential detection state and the operation stop state, and the value “0” indicates the normal VPP state.

Bits 2 to 0 of the status register are reserved for future expansion. These bits must be masked when polling the status register because these bits are for future expansion.

As a precaution when using the data stored in the status register, the RY / BY # output or the WSMS bit is checked and the operation (erasing suspension,
After confirming that the erase or data write has been completed, it is necessary to check that the corresponding status bit (ESS bit, ES bit, or DWS bit) indicates success. When the values of the DWS bit and the ES bit are set to “1” in the erasing operation, it indicates that an incorrect command sequence has been input. In this case, it is necessary to clear the data stored in each bit and perform the operation again. Furthermore, VPPS bit is different from an A / D converter does not perform the continuous display at V _PP level.
The write state machine queries the _VPP level only after a data write or erase command sequence is input, and notifies the system of appropriate data if _VPP is not on. The VPPS bit data indicates accurate feedback of V _PPL and V _PPH is not always guaranteed.

A block status register (BS) which stores the state of each erase block as data.
R) has a built-in nonvolatile semiconductor memory device. In the case of this type of device, it is possible to read the 8-bit data of the block status register by issuing a block status register read command. Even when a 16-bit data bus is used, the upper 8-bit bus is not used, and the data stored in the block status register corresponding to the selected address is output via the lower 8-bit bus.

FIG. 7 shows data stored in a conventional block status register (BSR).

The seventh bit of the block status register stores a bit (BS bit) indicating a block state. The value “1” of the BS bit indicates a ready state, and the value “0” indicates a busy state. A bit (BLS bit) indicating the block lock state is stored in the sixth bit of the block status register. The value “1” of the BLS bit indicates a block unlock state at the time of erasing / writing, and the value “0” indicates a block locking state at the time of erasing / writing. The fifth bit of the block status register stores a bit (BOS bit) indicating the block operation state. The value “1” of the BOS bit indicates an operation failure state, and the value “0” indicates an operation success state or an operation state. The fourth bit of the block status register includes a bit (BOAS) indicating a block operation suspended state.
Bit) is stored. BOAS bit value "1"
Indicates an operation stop state, and a value “0” indicates an operation continuation state.

When the value of the BOS bit is "0" and the value of the BOAS bit is "0", these bits indicate an operation success state or an operation state. When the value of the BOS bit is "0" and the value of the BOAS bit is "1", these bits indicate that an invalid operation has been performed. B
When the value of the OS bit is “1” and the value of the BOAS bit is “0”, these bits indicate an operation failure state.
When the value of the BOS bit is “1” and the value of the BOAS bit is “1”, these bits indicate an operation suspended state.

The third to zeroth bits of the block status register are reserved for future expansion. These bits must be masked when polling the block status register because these bits are for future expansion.

As a precaution when using the data stored in the block status register, RY / BY
# Check the output or BS bit and operate (block lock, erase suspend, erase, or write data)
Must be checked before the corresponding status bits (BOS bit, BLS bit) indicate success. Also, BOA
The S bit is not set until the data of the seventh bit becomes the value “1”. When the value of the BOS bit is “1” and the BO
When the value of the AS bit is "1", these bits indicate that the operation has been stopped by the abort command.

In this type of nonvolatile semiconductor memory device, the size of erase blocks in a chip is not uniform (US Pat.
o. 5249158) or equivalent (U.S. Pat.
245570).

In some of these nonvolatile semiconductor memory devices, both writing and erasing are performed by the FN tunnel current, and N or 16 memory cells are connected in series.
There is also a configuration using a memory cell called an AND type.
The NAND type has a slower read speed than the NOR type, but has the advantage that the memory cell size can be reduced.

As described above, normally, two values (one bit) are stored in one memory cell, but four values (two bits), eight values (three bits), and sixteen values (three bits) are stored. There is an attempt to record multi-values such as (4 bits).

Generally, in a non-volatile semiconductor memory device, the reading speed is as fast as about 100 nanoseconds, while the writing operation is as slow as about 20 microseconds and the erasing operation is as slow as about 1 second. Unlike ordinary SRAMs and DRAMs, data cannot be rewritten and read out at high speed in about 100 nanoseconds.
Therefore, when attempting to read data after the start of the erasing operation, wait until the erasing operation is completed, or issue an erasing operation temporary stop (suspend) command to cancel the operation.
The read operation needs to be performed after the erase operation is temporarily suspended after 0 microsecond.

In the existing flash memory, the following operation must be performed to read the data stored in the status register and the data stored in the block status register.

While the write state machine is executing the command, the control signal levels of / CE and / OE are set to "LOW" to perform a read operation, and the 8-bit data stored in the status register is read. Even if a 16-bit bus is used, the data indicating the status of the status register is output to the lower 8-bit bus without using the upper 8-bit bus, regardless of the address. When a block status register indicating the state of each erase block is incorporated, by issuing a block status register read command,
The 8-bit data stored in the block status register is read. Even if a 16-bit bus is used, the upper 8-bit bus is not used, and the data in the block status register corresponding to the selected address is output to the lower 8-bit bus.

At present, there is a nonvolatile semiconductor memory device having a built-in function of a memory array for two chips in one package. As an improvement of such a nonvolatile semiconductor memory device, a memory array for one chip is used. For example, when a write / erase operation is performed on a first memory array, a memory array for another chip (for example,
A nonvolatile semiconductor memory device capable of performing a read operation on the (second memory array) has been developed (for example, JP-A-6-180999 and JP-A-5-54682).

[0038]

However, in a conventional nonvolatile semiconductor memory device, even if two memory arrays, that is, a first memory array and a second memory array, are formed in one package device, two memory arrays are required. The procedure for reading the data stored in the register is the same as the conventional procedure.
The problem that the 8-bit data stored in any one of the registers can only be read in one read operation remains. That is, even if the nonvolatile semiconductor device has a data bus having a bit number larger than 8 bits, no attempt has been made to maximize the number of bits of the data bus.

In order to read the data stored in each of the two status registers corresponding to the two memory arrays in one package, first, the data of one status register is read, and then the data of the other status register is read. Read data. For this reason, a processing time including a time required for reading each data is required.

Even if a status register and a block status register (which stores data indicating the state of each erase block) are formed in a one-chip nonvolatile semiconductor memory device, they are stored in the status register. To read both the data and the data stored in the block status register, two procedures were required, and these data could not be read at once.

That is, even in a nonvolatile semiconductor memory device having a 16-bit data bus, only the data stored in any of the registers is output to the lower 8-bit bit line. To read the data of the two registers, the status register and the block status register, first issue a status register read command to read the data stored in the status register, and set the control signal levels of / CE and / OE to "LOW". Then, the read operation of the status register is started, and the data stored in the status register is read. The read 8-bit data (indicating the status of the status register) was sent via the lower 8 bits of the bus, and the upper 8-bit bus was never used.

Next, to read data stored in the block status register, an address is designated to select a block, a block status register read command is issued, and the control signal levels of / CE and / OE are set to "LOW". Then, the read operation of the block status register is started, and the data stored in the block status register is read. The read 8-bit data (indicating the state of the block status register corresponding to the selected address) was sent via the lower 8 bits of the bus, and the upper 8-bit bus was not used at all. Therefore, the operation becomes complicated, and the processing time for executing this operation is also required by the sum of the time required for reading the respective registers.

An object of the present invention is to improve the conventional nonvolatile semiconductor memory device, eliminate the above-mentioned problems, and provide a nonvolatile semiconductor memory device capable of performing a read / write operation in a short time. And

[0044]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory array having a plurality of blocks;
A status register for storing first data indicating a state of the memory array, a block status register for storing second data indicating one of the plurality of blocks, and a status register for storing the first data and the second data. A control circuit for controlling output to a data bus, wherein the number of bits of the data bus is equal to or greater than the sum of the number of bits of the first data and the number of bits of the second data; The control circuit controls the output of the first data and the second data to the data bus such that the first data and the second data are simultaneously output to the data bus. Objective is achieved.

[0045] The first data may be output to the data bus as data lower than the second data.

[0046] The second data may be output to the data bus as data lower than the first data.

According to another nonvolatile semiconductor memory device of the present invention, a plurality of memory arrays, a status register storing data indicating a state of one of the plurality of memory arrays, and a status register stored in the status register are provided. A control circuit for controlling output of the data to the data bus, wherein one of the plurality of memory arrays is selected in accordance with information for selecting an address, and a status corresponding to the selected memory array is selected. The first data is output from the register, the second data is output from the status register corresponding to one of the other memory arrays that has not been selected, and the number of bits of the data bus is the number of bits of the first data. Equal to or greater than the sum of the number of bits and the number of bits of the second data; Controlling the output of the first data and the second data to the data bus so that the second data is simultaneously output to the data bus; Reading from the memory array is performed at the same time, thereby achieving the above object.

[0048] The plurality of memory arrays may be formed in one chip.

According to another nonvolatile semiconductor memory device of the present invention, there are provided a plurality of memory arrays each having a plurality of blocks, and a plurality of statuses storing first data indicating one state of the plurality of memory arrays. A register, a plurality of block status registers storing second data indicating a state of one of the plurality of blocks, and a control circuit controlling output of the first data and the second data to a data bus. Wherein each of the plurality of status registers and each of the plurality of block status registers correspond to each of the plurality of memory arrays, and one of the plurality of memory arrays is arranged according to information for selecting an address. The first data is output from the selected status register corresponding to the selected memory array, and the selected memory is output. The second data is output from the block status register corresponding to the ray, and the number of bits of the data bus is equal to or greater than the sum of the number of bits of the first data and the number of bits of the second data. First
The output of the first data and the second data to the data bus is controlled such that the first data and the second data are simultaneously output to the data bus, thereby achieving the above object.

In another nonvolatile semiconductor memory device of the present invention, a memory array having a plurality of blocks, a status register storing first data indicating a state of one of the memory arrays, A control circuit for controlling output of data and second data different from the first data to a data bus, wherein the number of bits of the data bus is the number of bits of the first data and the number of bits of the second data. The first data and the second data
The output of the first data and the second data to the data bus is controlled such that data is output to the data bus at the same time, thereby achieving the above object.

Further, another nonvolatile semiconductor memory device of the present invention comprises a memory array having a plurality of blocks, a block status register for storing first data indicating a state of one of the plurality of blocks, Control means for controlling output of the first data and second data different from the first data to the data bus, wherein the number of bits of the data bus is the number of bits of the first data and the number of bits of the second data. The number of bits equal to or greater than
The output of the first data and the second data to the data bus is controlled such that the data and the second data are simultaneously output to the data bus, thereby achieving the above object.

Hereinafter, the operation will be described.

The nonvolatile semiconductor memory device configured as described above can read the data of two registers by one reading, so that the processing time for reading, erasing, writing, etc. can be reduced. Further, when a command is input and data is read, the states of the registers for two chips can be known at a time, and the user can easily know the state of the chips. Further, since a configuration in which a memory array for two chips is provided in a one-chip nonvolatile semiconductor storage device is possible, an extra circuit can be eliminated as compared with a conventional configuration in which a two-chip memory device is used. Occupied area can be reduced. Further, similarly to the related art, data of one register can be read by one reading, and compatibility with a conventional nonvolatile semiconductor memory device can be maintained.

Also, in the nonvolatile semiconductor memory device of the present invention, when the write state machine is executing a command (or to read the status register,
After issuing the command), when the control signal levels of / CE and / OE are set to "LOW" to perform the read operation,
The data stored in the status register can be read out instead of the data stored in the memory array.
Even when a plurality of status registers are provided, the control circuit controls the output of the first data from the first status register and the second data from the second status register to the data bus, and Since the second data is output at the same time, when CE # and OE # are set to “LOW”, the data of the status register corresponding to the memory array of one chip corresponding to the selected address is used as lower data. The data is output to the bus, and the data of the status register corresponding to the memory array for another chip can be output to the data bus as higher-order data.

Further, an address for selecting a block is inputted, and at the same time, the control signal levels of / CE and / OE are set to "L".
When a command is issued to set the status to "OW" and read the data of the block status register, the first data of the status register and the second data of the block status are read instead of the data stored in the memory array. . The control circuit is configured to control the first data from the status register and the second data from the block status register.
Since the output of the data to the data bus is controlled and the first data and the second data are output simultaneously, the data from the block status register corresponding to the memory array specified by the address is used as the lower data as the data bus. And the data from the status register corresponding to the memory array not selected by the address can be output to the data bus as higher-order data. further,
As in the conventional case, it is possible to output only the data of the register corresponding to the memory array selected by the address.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a nonvolatile semiconductor memory device 1 according to a first embodiment of the present invention.

In the following description, it is assumed that nonvolatile semiconductor memory device 1 is a flash memory. However, the present invention can be applied to non-volatile memories other than flash memories. The flash memory 1 includes a memory array 120 having a plurality of blocks 101 and a command state machine (C
SM) 102 and light state machine (WSM) 103
, A row (row) decoder 104 and a column (column) decoder 1
05, a block selection circuit 106, a status register (SR) 107, a data switching circuit 109, a block status register (BSR) 110, and a sense amplifier 116. The flash memory 1 has a 16-bit data bus 112 and an address bus 113. Further, the flash memory 1 includes an erase / write voltage generation circuit 115 for programs such as erase / write.

The status register 107 stores data indicating the state of the memory array. The block status register 110 stores one of the blocks 101.
Data indicating one of the states is stored. A block protection setting portion (BP) 108 schematically shows a state of whether or not the block is locked. Data indicating whether the block is locked is stored in the block status register 110 of each erase block.

A command 111 and a reset signal 114 are input to the command state machine 102, and the control signal levels of / CE, / WE, and / OE change in synchronization with the command 111 and the reset signal 114.

The command state machine 102 decodes the input command 111, and
Send the decrypted result to. The write state machine 103 executes an operation (such as erasing / writing) corresponding to the command 111. The row decoder 104 selects a word line (not shown) of the memory array 120, and the column decoder 105 selects a bit line (not shown) of the memory array 120. The storage state of the bit line selected by the column decoder 105 is sensed by the sense amplifier 116. The block selection circuit 106 selects one block from the n erase blocks 101. The write state machine 103 erases the data of the blocks collectively when the block selected by the block selection circuit 106 is not in the erasure prohibited state (block locked state). Conversely, when the block is in the erasure prohibited state (block locked state), the data stored in the block is not rewritten.

In order to perform the erasing operation, usually, first, one of the blocks 101 to be erased is selected, and data "0" is written to all the memory cells (not shown) in the selected block 101. (The threshold voltage _Vth is increased). Next, when all the _{Vths of the} memory cells in the block 101 to be erased have become equal to or more than the specified value, the data stored in the memory cells of the block is erased collectively ( _Vth is reduced). ). These series of operations are controlled by the write state machine 103, and the execution results are stored as data in the status register 107 and the block status register 110. The data stored in the block status register 110 includes, in addition to data indicating the lock state of each erase block 101, data regarding which block is selected by designating an address from the outside. is there.

The flash memory 1 has a 16-bit data bus 112 so that data can be exchanged between the command state machine 102 and the data switching circuit 109 and the outside. The width of the bus 112 may be other than 16 bits, and may be, for example, 24 bits or 32 bits.

A predetermined voltage is input to the erase / write voltage generation circuit 115 from an external power supply V _CC . The erase / write voltage generation circuit 115 generates a high voltage of about 12 V as necessary, or generates a negative potential when performing a negative gate erase.

The data switching circuit 109 is connected to the memory array 1
This is a circuit for selecting which of the data stored in 01, the data stored in the status register 107, and the data stored in the block status register 110 is to be read.

FIG. 2 shows a configuration of the data switching circuit 109 shown in FIG.

The data switching circuit 109 includes a plurality of tri-state gates 109-1 to 109-6 and a 1 / n block status register selection circuit 109-7. To the data switching circuit 109, a sense amplifier 116, a status register 107, and a block status register 110 are connected. The data output from the data switching circuit 109 is sent to a 16-bit data bus 112.

A 1 / n block status register selection circuit based on data specified as a block address
109-7 is 1 from n block status registers 110
Block status registers are selected.

Signals S1 to S3 are command state machines
102 (not shown in FIG. 2; see FIG. 1) is input to the data switching circuit 109. The levels of the signals S1 to S3 are indicated by (X, X, X). Here, X is level “H” or level “L”, and S1 and S
2, the signal of S3. For example, (H, L, L) indicates that the signal S1 is at the level “H”, and S2 and S3 are at the level “L”.

When the signal becomes (H, L, L), tristate gates 109-1 and 109-2 are connected to sense amplifier 116.
Pass the output from When the signal becomes (L, H, L), the tri-state gate 109-6 transmits the data stored in the block status register 110 as lower 8-bit data via the data bus 112, and The state gate 109-4 transmits the data stored in the status register 107 via the 16-bit bus 112 as upper 8-bit data. When the signal becomes (L, L, H), the tri-state gate 109-3 transmits the data stored in the status register 107 as lower 8-bit data via the 16-bit bus 112, and outputs the tri-state data. Gate 109-5 is the block status register 110
Is stored as the upper 8-bit data.
It is transmitted via a 6-bit bus 112.

Since the flash memory 1 includes the data switching circuit 109 for controlling the output of the data stored in the status register 107 and the block status register 110, the signals (L,
H, L) and signals (L, L, H), the data from the status register 107 and the block status register 110 is output not only to the lower bit line of the data bus 112 but also to the upper bit line. It is possible to
Therefore, it is possible to read the state of the register of the conventional two chips as data by one reading.

That is, the flash memory 1 can output the data from the status register 107 and the data from the block status register 110 to the data bus 112 at the same time.

Further, the flash memory 1 includes a 1 / n block status register selection circuit 109-7 and a data bus 1
Another tri-state gate can be provided between the lower 12 bit lines. By controlling this other tri-state gate, the data bus 112 is controlled in the same manner as in the conventional method.
It is also possible to output information from the block status register 110 using only the lower bit lines of.

[0074]

[Table 1]

Table 1 shows commands used in a conventional flash memory write-write cycle.

The write commands in this write-write cycle include data write, block erase, erase suspend, erase resume, and block lock.

In the flash memory 1 of this embodiment, writing can be controlled by using the command in the conventional write-write cycle as it is. When a block erase command is input, the first cycle / CE
And / WE control signal levels are both "L", and data having a value (20) _H is input. here,
(X) _H indicates a number X expressed in hexadecimal. The same notation is used below. Next, in the second cycle, the control signal levels of / CE and / WE both become "L" and the value (D
0) The data of _{H and} the block address to be erased are input.

When a write command is input, the control signal levels of / CE and / WE both become "L" in the first cycle, data of value (40) _H is input, and then / The control signal levels of CE and / WE both become "L", and data to be written to the memory cell and the address of the memory cell are input.

When a block lock command is input,
In the first cycle, the control signal levels of / CE and / WE both become "L" and data of value (77) _H is input. Then, in the second cycle, the control signal levels of / CE and / WE are changed to "L". Both become "L", and the address of the block for which data rewriting is prohibited and the data of the value (D0) _H are input. As a result, 108 bits of the block protection setting portion (BP) (shown in FIG. 1) are set (block lock state). The block protection setting section 108 is set for each block. When the block lock setting command is issued, the value of the block protection setting portion 108 becomes “H”, and rewriting of the data of the block is prohibited (when the value of the block protection setting portion 108 is “L”, rewriting is possible). . Data indicating whether the block is locked is stored in the block status register 110 of each erase block.

Since the erasing operation usually takes a long time, it is preferable to use an erasing interrupt command.
When the erase suspend command is input, the / C
The control signal levels of E and / WE both become "L",
Data having the value (B0) _H is input. In order to stop the erase operation and restart the erase operation, a restart command is used. When the restart command is input, the control signal levels of / CE and / WE both become "L" in the first cycle, and data having the value (D0) _H is input.

In order to obtain data indicating whether or not the erase operation or the write operation has succeeded, after the erase operation or the write operation is performed, the control signal levels of both / CE and / OE are set to “L”, and the status is changed. It is sufficient to read the 8-bit data of the register 107.

[0082]

[Table 2]

Table 2 shows commands used in a conventional flash memory write-read cycle.

The read command in the write-read cycle includes array read, status register read, clear status register, and block status register read.

As a command for reading from the flash memory 1, a command for a conventional flash memory can be used as it is.

For example, in the first cycle, / CE and /
The control signal levels of the WE are both set to “L” and the value (70) _H
, The status register 107 is set to the read mode, the control signal levels of / CE and / OE are both set to "L", and the state of the status register 107 can be read.

In the first cycle, data having the value (71) _H is written, and the block status register 11
0 The read mode is issued as a command, the control signal levels of / CE and / OE are both set to "L", a block selection address is input, and the block status register 11
0-bit data of 0 can be read.

(Second Embodiment) FIG. 3 shows a configuration of a nonvolatile semiconductor memory device 2 according to a second embodiment of the present invention.

In the following description, it is assumed that nonvolatile semiconductor memory device 2 is a flash memory. However, the present invention can be applied to non-volatile memories other than flash memories. The flash memory 2 has two memory arrays 201a, 201b
, A 16-bit data bus 212 and an address bus 213. The memory arrays 201a and 201b include a plurality of blocks (not shown). Flash memory 2
Are two status registers (SR1 shown in FIG. 3)
And SR2) 207a, b. The two status registers 207a and 207b are two memory arrays 201a and 201b, respectively.
It corresponds to. In addition, the flash memory 2 includes a block status register 210 (not shown in FIG. 3; see FIG. 4) corresponding to each of the two memory arrays 201a and 201b. The flash memory 2 is formed in one chip, and includes the memory arrays 201a and 201b for two chips and circuits corresponding thereto.
Called RK. The status register 207a stores data indicating the state of the memory array 201a,
The status register 207b stores data indicating the state of the memory array 201b. The plurality of block status registers 210 correspond to each of a plurality of blocks included in the memory arrays 201a and 201b, and data indicating a state of one of the plurality of blocks is stored in each block status register 210. ing.

The flash memory 2 includes a command state machine (CSM) 202, a write state machine (WSM) 203, a data switching circuit 209, and an erase / write voltage generation circuit 215.

The command 211 and the reset signal 214 are input to the command state machine 202, and the control signal levels of / CE, / WE, and / OE change in synchronization with this.
The command state machine 202 stores the input command 211
Then, data for instructing the memory array 201a or 201b to execute reading, erasing, writing, or the like is sent to the write state machine 203. For example, the command 211 for the memory array 201a
Is input, the write state machine 203 executes an operation (read / erase / write, etc.) corresponding to the command 211 on the memory array 201a.

The row decoders 204a and 204b correspond to the memory arrays 201a and 201b, respectively, and select word lines (not shown) of the memory arrays 201a and 201b. The column decoders 205a and 205b correspond to the memory arrays 201a and 201b, respectively, and select bit lines (not shown) of the memory arrays 201a and 201b. Sense amplifier 216a, b
Sense the storage state of the bit line. The block selection circuits 206a and 206b control erasing and writing of data stored in blocks of the memory arrays 201a and 201b.

Row decoder corresponding to memory array 201a
204a selects a word line of the memory array 201a, and a column decoder 205a selects a bit line of the memory array 201a.
The storage state of the bit line selected by the column decoder 205a is sensed by the sense amplifier 216a. Block selection circuit 20
Step 6a selects one block from the M erase blocks. When the block selected by the block selection circuit 206a is not in the erasure prohibited state (block locked state), the write state machine 203 collectively erases the data of the selected block. Conversely, the block selected by the block selection circuit 206a is in the erasure prohibited state (block locked state).
When, the data stored in the block is not rewritten.

A series of these operations are controlled by the write state machine 203, and the execution result is stored as data in the status register 207a and the block status register 203.
Stored in 210. The block status register 210 corresponding to the memory array 201a stores data indicating a locked state of each erase block (a state in which rewriting of data is set to be prohibited).

Similarly, the row decoder 204b corresponding to the memory array 201b selects a word line of the memory array 201b,
The column decoder 205b selects a bit line of the memory array 201b. The storage state of the bit line selected by the column decoder 205b is sensed by the sense amplifier 216b. The block selection circuit 206b selects one block from the M erase blocks. When the block selected by the block selection circuit 206b is not in the erasure prohibited state (block locked state), the write state machine 203 collectively erases the data of the selected block. Conversely, the block selection circuit
When the block selected by 206b is in the erasure prohibited state (block locked state), the data stored in the block is not rewritten.

A series of these operations are controlled by the write state machine 203, and the execution result is stored as data in the status register 207b and the block status register 203.
Stored in 210. The block status register 210 corresponding to the memory array 201b stores data indicating a locked state of each erase block (a state in which rewriting of data is set to be prohibited).

Even when data is written to the memory array 201a, if a read from the memory array 201b is input as a command, the row decoder 204b corresponding to the memory array 201b selects a word line of the memory array 201b. , A column decoder 205b corresponding to the memory array 201b selects a bit line of the memory array 201b. Further, the bit line of the memory array 201b selected by the column decoder 205b corresponding to the memory array 201b is sensed and output by the sense amplifier 216b corresponding to the memory array 201b.

A predetermined voltage is input to erase / write voltage generation circuit 215 from external power supply V _CC . The erase / write voltage generation circuit 215 generates a high voltage of about 12 V as necessary, or generates a negative potential when performing a negative gate erase.

The flash memory 2 includes two chips of memory arrays 201a and 201b and a circuit corresponding to the two chips. However, since the flash memory 2 includes the data switching circuit 209, the erasing operation for the memory array 201a can be performed. During execution, a read operation to the memory array 201b can be performed at the same time, so that the flash memory 2 can operate for two chips in the related art.

FIG. 4 shows the structure of the data switching circuit 209 shown in FIG.

The data switching circuit 209 has a plurality of tri-state gates 209-1 to 209-7 and a 1 / N block status register selection circuit 209-8. The data switching circuit 209 has status registers 207a,
b, N block status registers 210 and sense amplifiers 216 are connected. The data output from the data switching circuit 209 is sent to the 16-bit data bus 212. Signals S1 to S input to data switching circuit 209
4 is a signal transmitted from the command state machine 202 (not shown in FIG. 4; see FIG. 3).

The data switching circuit 209 is connected to the memory array 2
01a, b (not shown in FIG. 4; see FIG. 3), any of the data stored in the status registers 207a, b, and the data stored in the block status register 210 as data. Select whether to read. 1 / N block status register selection circuit 209-8 based on data designated as a block address
Selects one block status register from the N block status registers 210 (the total number N of the number of blocks corresponding to the memory array 201a and the number of blocks corresponding to the memory array 201b).

Signals S1 to S3 are command state machines
202 (not shown in FIG. 4; see FIG. 3) is input to the data switching circuit 209. The levels of the signals S1 to S4 are indicated by (X, X, X, X). X is a level “H” or “L”, and represents signals of S1, S2, S3, and S4 in order from the top. For example, (H, L, L, L) indicates that the signal S1 is at the level “H” and S2 to S4 are at the level “L”.

When the signal becomes (H, L, L, L),
Tristate gates 209-1 and 209-2 pass the sense amplifier output. When the signal becomes (L, H, L, L)
Tri-state gate 209-3 transmits the data stored in block status register 210 as lower 8-bit data via 16-bit bus 212.

When the signal becomes (L, L, H, L),
The tri-state gate 209-4 uses the data stored in the status register 207a corresponding to the memory array 201a (not shown in FIG. 4; see FIG. 3) as lower 8-bit data via the 16-bit data bus 212. Communicate
The tri-state gate 209-6 uses the data stored in the status register 207b corresponding to the memory array 201b (not shown in FIG. 4; see FIG. 3) as upper 8-bit data via the 16-bit data bus 212. To communicate.

When the signal becomes (L, L, L, H),
The tri-state gate 209-7 converts the data stored in the status register 207b corresponding to the memory array 201b (not shown in FIG. 4; see FIG. 3) as lower 8-bit data via the 16-bit data bus 212. Communicate
The tri-state gate 209-5 uses the data stored in the status register 207a corresponding to the memory array 201a (not shown in FIG. 4; see FIG. 3) as high-order 8-bit data via the 16-bit data bus 212. To communicate.

Since the flash memory 2 includes the data switching circuit 209 for controlling the output of the data stored in the two status registers 207a and 207b to the data bus 212, the signals (L, L) are sent from the command state machine 202. ,
H, L) and signals (L, L, L, H),
It is possible to output data from any of the status registers 207a and 207b not only to the lower bit line of the data bus 212 but also to the upper bit line of the data bus 212.

That is, the flash memory 2 stores the memory array 201a selected according to the information for selecting an address.
(Not shown in FIG. 4; see FIG. 3) and the status corresponding to the unselected memory array 201b (not shown in FIG. 4; see FIG. 3). The data from the register 207b can be simultaneously output to the data bus 212.

Further, the flash memory 2 outputs the signals (L, H, L, L) from the command state machine 202 (not shown in FIG. 4; see FIG. 3), so that the flash memory 2 operates in the same manner as the conventional method. The information from one of the block status registers 210 can be output using only the lower bit lines of the data bus 212.

(Third Embodiment) In the following description, it is assumed that the nonvolatile semiconductor memory device is a flash memory. However, the present invention can be applied to non-volatile memories other than flash memories.

Referring to FIGS. 3 and 4, the flash memory will be described using the same reference numerals as in the second embodiment.

The flash memory 2 is different from the second embodiment in that the status register 207b of the memory array 201b is different from that of the second embodiment.
Instead of inputting the data stored in the data switching circuit 209 to the tri-state gates 209-6 and 209-7 of the data switching circuit 209, the data stored in the block status register 210 of the memory array 201b is input to the tri-state gate 209- of the data switching circuit 209. Enter 6 and 209-7. Other configurations of the flash memory 2 are the same as those of the second embodiment.

Hereinafter, referring to FIG.
Will be described.

When a command 211 for the memory array 201a is input, a write state machine (WSM) 203
Performs an operation (read / erase / write, etc.) corresponding to the command 211 on the memory array 201a. The row decoder 204a corresponding to the memory array 201a selects a word line (not shown) of the memory array 201a, and the column decoder 205a selects a bit line of the memory array 201a. The bit line (not shown) selected by the column decoder 205a
The storage state is sensed by the sense amplifier 216a.

The block selection circuit 206a selects one block from M erase blocks (or sectors). When the block selected by the block selection circuit 206a is not in the erasure prohibited state (block locked state), the write state machine 203 collectively erases the data of the selected block. Conversely, the block selection circuit
When the block selected by 206a is in the erasure prohibited state (block locked state), the data stored in the block is not rewritten.

A series of these operations are controlled by the write state machine 203, and the execution result is stored as data in the status register 207a and the block status register 203.
210 (not shown in FIG. 3; see FIG. 4). The block status register 210 stores data reflecting the lock state of each erase block (a state in which data rewrite is set to be prohibited).

When data is written to the memory array 201a and a read from the memory array 201b is input as a command 211, the memory array 201b
The row decoder 204b corresponding to the memory array 201b selects the word line of the memory array 201b, and the column decoder 205b corresponding to the memory array 201b selects the bit line of the memory array 201b. The bit line of the memory array 201b selected by the column decoder 205b corresponding to the memory array 201b is
Are stored and sensed by the sense amplifier 216b corresponding to.

Flash memory 2 of the present embodiment
Has a data switching circuit 209. The data switching circuit 209 stores data stored in the memory arrays 201a and 201b, data stored in the status registers 207a and 207b, and data stored in the block status register 210. Select one of them to be read as data. As the block address, one block status register is selected from N block status registers 210 (the total number N of the number of blocks corresponding to the memory array 201a and the number of blocks corresponding to the memory array 201b).

Hereinafter, the flash memory 2 will be described with reference to FIG.
Will be described.

When the signal becomes (H, L, L, L),
Tri-state gates 209-1 and 209-2 are sense amplifiers
Pass 216 outputs. When the signal becomes (L, H, L, L), the tri-state gate 209-3 transmits the data stored in the block status register 210 as lower 8-bit data via the 16-bit bus 212.

When the signal becomes (L, L, H, L),
The tri-state gate 209-4 uses the data stored in the status register 207a corresponding to the memory array 201a (not shown in FIG. 4; see FIG. 3) as lower 8-bit data via the 16-bit data bus 212. Communicate
The tri-state gate 209-6 transfers the data stored in the block status register 210 corresponding to the memory array 201b (not shown in FIG. 4; see FIG. 3) to the upper 8 bits.
The data is transmitted via the 16-bit data bus 212 as bit data.

When the signal becomes (L, L, L, H),
The tri-state gate 209-7 transmits the data stored in the block status register 210 corresponding to the memory array 201b as lower 8-bit data via the 16-bit data bus 212.
The data stored in the status register 207a corresponding to the memory array 201a is transmitted via the 16-bit data bus 212 as upper 8-bit data.

The flash memory 2 has a data bus 21 for storing data stored in two registers, the status register 207a and the block status register 210.
Since it has the data switching circuit 209 for controlling the output to the signal 2, the signals (L, L, H, L) and the signals (L, L, H, L) from the command state machine 202 (not shown in FIG. L, L, L, H), the data bus 21 is output.
It is possible to output data from any of the above registers not only to the lower two bit lines but also to the upper bit lines.

That is, the flash memory 2 stores data from the status register 207a corresponding to the memory array 201a selected according to the information for selecting an address, and data from the block status register 210 corresponding to the memory array 201b not selected. And the data bus 2 at the same time
Can output to 12.

Further, the flash memory 2 outputs signals (L, H, L, L) from the command state machine 202, thereby using only the lower bit lines of the data bus 212 as in the conventional method. , The data from the block status register 210 can be output.

(Fourth Embodiment) In the following description, it is assumed that the nonvolatile semiconductor memory device is a flash memory. However, the present invention can be applied to non-volatile memories other than flash memories.

Referring to FIGS. 3 and 4, the flash memory will be described using the same reference numerals as in the second embodiment.

The flash memory 2 is different from the second embodiment in that the status register 207b of the memory array 201b is different from that of the second embodiment.
Instead of inputting the data stored in the data switching circuit 209 to the tri-state gates 209-6 and 209-7 of the data switching circuit 209, the data stored in the block status register 210 of the memory array 201a is input to the tri-state gate 209- of the data switching circuit 209. Enter 6 and 209-7. Other configurations of the flash memory 2 are the same as those of the second embodiment.

Hereinafter, referring to FIG.
Will be described.

When a command for the memory array 201a is input, the write state machine (WSM) 203 executes an operation (read / erase / write, etc.) corresponding to the command 211 on the memory array 201a. The row decoder 204a corresponding to the memory array 201a is a memory array.
The word line of the memory array 201a is selected by the word line of the memory array 201a. Column decoder 205a
The storage state of the bit line selected in is stored by the sense circuit 216a.

The block selection circuit 206a selects one block from M erase blocks (or sectors). When the block selected by the block selection circuit 206a is not in the erasure prohibited state (block locked state), the write state machine 203 collectively erases the data of the selected block. Conversely, the block selected by the block selection circuit 206a is in the erasure prohibited state (block locked state).
When, the data stored in the block is not rewritten.

The series of operations are controlled by the write state machine 203, and the execution results are stored as data in the status register 207a and the block status register 210 (not shown in FIG. 3; see FIG. 4). Also,
The block status register 210 stores data reflecting the lock state of each erase block (a state in which data rewrite is prohibited).

When data is written to the memory array 201a and a read from the memory array 201b is input as a command, the row decoder 204b corresponding to the memory array 201b selects a word line of the memory array 201b. , Column decoder corresponding to memory array 201b
205b selects a bit line of the memory array 201b. The bit line of the memory array 201b selected by the column decoder 205b corresponding to the memory array 201b has its storage state sensed by a sense circuit 216b corresponding to the memory array 201b and is output.

The flash memory 2 is a data switching circuit
209. The data switching circuit 209 stores the data stored in the memory arrays 201a and 201b and the status register 20.
Data stored in 7a, b, block status register
Select one of the data stored in 210 to be read as data. According to the block address, the data switching circuit 209 sets N block status registers 21 (the total number N of the number of blocks corresponding to the memory array 201a and the number of blocks corresponding to the memory array 201b).
Select one block status register from 0.

Hereinafter, the flash memory 2 will be described with reference to FIG.
Will be described.

When the signal becomes (H, L, L, L),
Tri-state gates 209-1 and 209-2 are sense amplifiers
Pass 216 outputs. When the signal becomes (L, H, L, L), the tri-state gate 209-3 transmits the data stored in the block status register 210 as lower 8-bit data via a 16-bit bus.

When the signal becomes (L, L, H, L),
Tri-state gate 209-4 transmits the data stored in status register 207a corresponding to memory array 201a as lower 8-bit data via a 16-bit data bus. Is transmitted via the 16-bit data bus 212 as higher-order 8-bit data.

When the signal becomes (L, L, L, H),
The tri-state gate 209-7 transmits the data stored in the block status register 210 corresponding to the memory array 201a as lower 8-bit data via the 16-bit data bus 212.
The data stored in the status register 207a corresponding to the memory array 201a is transmitted via the 16-bit data bus 212 as upper 8-bit data.

The flash memory 2 has a status register 207a and a data switching circuit 209 for controlling output of data stored in any two of the block status registers 210 to the data bus 212. Therefore, by outputting the signals (L, L, H, L) and the signals (L, L, L, H) from the command state machine 202, not only the lower bit line of the data bus 212 but also the upper bit line It is also possible to output data from any of the above registers.

That is, the flash memory 2 stores the data from the status register 207a corresponding to the memory array 201a selected according to the information for selecting the address and the block status register 21 corresponding to the memory array 201a.
Data from 0 can be output to the data bus 212 at the same time.

Further, the flash memory 2 outputs signals (L, H, L, L) from the command state machine 202, so that only the lower bit lines of the data bus 212 are used as in the conventional method. , The data from the block status register 210 can be output.

In the nonvolatile semiconductor memory device of the present invention, the memory cell may be a conventional memory cell as shown in FIG. 5, a memory cell using a ferroelectric thin film as a DRAM capacitor, or a gate oxide film. May be a memory cell using a ferroelectric thin film. Memory cells that use a ferroelectric thin film as the gate oxide film use polarization inversion and do not need to use a thin tunnel oxide film as in the conventional gate oxide film. Becomes possible.

In the nonvolatile semiconductor memory device of the present invention, the state in which the data in the memory array is erased is not limited to the case where the _Vth value of the memory cell corresponds to the low state. That is, in the nonvolatile semiconductor memory device of the present invention, the same effect can be obtained even when the state where the _{Vth of} the memory cell is large corresponds to erasing. In this case, programming may be performed by increasing the value of V _th of the memory cells collectively, and necessary data may be stored by _decreasing the value of V _th of each memory cell.

[0144]

As described above, according to the present invention, the control circuit controls the output of the first data from the status register and the second data from the block status register to the data bus, and Since the output and the output of the second data are performed at the same time, two times
The data of one register can be read, and the processing time can be reduced. In addition, data of one register can be read by one read, similarly to the conventional nonvolatile semiconductor memory device, and compatibility with the conventional nonvolatile semiconductor memory device can be maintained.

Further, according to the nonvolatile semiconductor memory device of the present invention, the first semiconductor memory device is provided with the first register from the status register corresponding to one memory array selected according to the information for selecting an address.
The control circuit controls the output of the data and the second data from the status register corresponding to one of the unselected memory arrays to the data bus, and outputs the first data and the second data. Since data output is performed at the same time and writing to the selected memory array and reading from another memory array are performed simultaneously, it is possible to read data of two registers in one reading operation. It is possible and the processing time can be shortened. Also, 1
The data indicating the state of the register for two chips can be read by two read operations, and the user can easily know the state of the chip. In addition, it is possible to provide a memory array for two chips in one chip.
Since the same operation as when a memory array of chips is used is possible, an extra circuit can be eliminated and a chip area can be reduced as compared with a case where a memory array is configured by two chips. Further, the data in one register can be read by one reading as in the conventional nonvolatile semiconductor memory device, and the compatibility with the conventional nonvolatile semiconductor memory device can be maintained.

Further, according to the nonvolatile semiconductor memory device of the present invention, the first semiconductor memory device stores the first data from the status register corresponding to one memory array selected in accordance with the information for selecting an address.
The control circuit controls the output of the data and the second data from the block status register corresponding to the selected one memory array to the data bus, and the first data and the second data are output.
Since the data and the output are performed simultaneously, the data of the two registers can be read by one reading, and the processing time can be reduced. Further, the state of the register for two chips can be known by one reading, and the user can easily know the state of the chip. Further, the data in one register can be read by one reading as in the conventional nonvolatile semiconductor memory device, and the compatibility with the conventional nonvolatile semiconductor memory device can be maintained.

Further, in the nonvolatile semiconductor memory device of the present invention, the control circuit controls the output of the first data from the status register and the second data different from the first data to the data bus, and Since the output with the second data is performed at the same time, two data can be read by one reading, and the processing time can be reduced. In addition, data of one register can be read by one read, similarly to the conventional nonvolatile semiconductor memory device, and compatibility with the conventional nonvolatile semiconductor memory device can be maintained.

Further, according to the nonvolatile semiconductor memory device of the present invention, the first data from the block status register and
The control circuit controls the output of the second data different from the first data to the data bus, and the output of the first data and the second data is performed simultaneously, so that two data are read by one reading. And the processing time can be reduced. In addition, data of one register can be read by one read, similarly to the conventional nonvolatile semiconductor memory device, and compatibility with the conventional nonvolatile semiconductor memory device can be maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory device 1 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a data switching circuit 109 shown in FIG.

FIG. 3 is a diagram showing a configuration of a nonvolatile semiconductor memory device 2 according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a data switching circuit 209 shown in FIG.

FIG. 5 is a diagram showing a memory cell 3 of a conventional flash memory.

FIG. 6 is a diagram showing data stored in a conventional status register (SR).

FIG. 7 shows a conventional block status register (BSR).
FIG. 3 is a diagram showing data stored in the.

[Explanation of symbols]

 2 Flash memory 201a, b Memory array 202 Command state machine 203 Write state machine 207a, b Status register 209 Data switching circuit 210 Block status register 212 Data bus

Claims (8)

[Claims] 1. A memory array having a plurality of blocks, a status register storing first data indicating a state of the memory array, and a block storing second data indicating a state of one of the plurality of blocks. A status register, and a control circuit for controlling output of the first data and the second data to a data bus, wherein the number of bits of the data bus is the number of bits of the first data and the number of bits of the second data. Equal to or greater than the sum of the number of bits, the control circuit controls the first data and the second data such that the first data and the second data are simultaneously output to the data bus. Controlling output to the data bus;
Non-volatile semiconductor storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first data is output to said data bus as data lower than said second data. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said second data is output to said data bus as data lower than said first data. 4. A plurality of memory arrays, a status register storing data indicating a state of one of the plurality of memory arrays, and controlling output of the data stored in the status register to a data bus. A memory circuit is selected from the plurality of memory arrays in accordance with information for selecting an address, and first data is output from a status register corresponding to the selected memory array, and the first data is not selected. The second data is output from the status register corresponding to one of the other memory arrays, and the number of bits of the data bus is determined by the number of bits of the first data and the number of bits of the second data. Equal to or greater than the sum, the control circuit outputs the first data and the second data simultaneously to the data bus. The first data and the second data
A nonvolatile semiconductor memory device that controls output of data to the data bus, and simultaneously performs writing to the selected memory array and reading from the other memory array. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said plurality of memory arrays are formed in one chip. 6. A plurality of memory arrays each having a plurality of blocks, a plurality of status registers storing first data indicating a state of one of the plurality of memory arrays,
A plurality of block status registers that store second data indicating a state of one of the plurality of blocks; and a control circuit that controls output of the first data and the second data to a data bus. Each of the plurality of status registers and each of the plurality of block status registers correspond to each of the plurality of memory arrays, and one of the plurality of memory arrays according to information for selecting an address.
One memory array is selected, first data is output from a status register corresponding to the selected memory array, and second data is output from a block status register corresponding to the selected memory array. The number of bits is equal to or greater than the sum of the number of bits of the first data and the number of bits of the second data, and the first data and the second data are simultaneously output to the data bus. Nonvolatile semiconductor memory device controlling output of the first data and the second data to the data bus as described above. 7. A memory array having a plurality of blocks, a status register storing first data indicating a state of one of the memory arrays, and a status register for storing the first data and second data different from the first data. A control circuit for controlling the output to the data bus, wherein the number of bits of the data bus is equal to or greater than the sum of the number of bits of the first data and the number of bits of the second data; A nonvolatile semiconductor memory device that controls output of the first data and the second data to the data bus such that one data and the second data are simultaneously output to the data bus. 8. A memory array having a plurality of blocks; a block status register for storing first data indicating a state of one of the plurality of blocks;
Control means for controlling output of data and second data different from the first data to a data bus, wherein the number of bits of the data bus is the number of bits of the first data and the number of bits of the second data And controlling the output of the first data and the second data to the data bus such that the first data and the second data are simultaneously output to the data bus. A non-volatile semiconductor storage device.