JPH11345129A - Interval timer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interval timer circuit, with which the load of a CPU is leveled by adding least circuits. SOLUTION: A frequency divider circuit 4 with a frequency dividing ratio switching function generates a count clock (d) to be supplied to an interval timer 5, by dividing the frequency of a system clock (a) supplied from a system clock generating part 1. A frequency dividing ratio is automatically switched, while receiving a signal (b), which specifies the task of heavy processing load, from an external event interrupt signal generating part 6 and the cycle of the count clock (d) is changed. Corresponding to the count clock (d) from the frequency divider circuit 4 with frequency dividing ratio switching function, the interval timer 5 measures interval time as a time interval to switch the processing of respective tasks and outputs an interval signal (c) to a CPU 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interval timer circuit, and more particularly, to an interval timer circuit of a multitask system in which a plurality of processes run in a central processing unit.

[0002]

2. Description of the Related Art In a computer system, when a central processing unit (computer; CPU) runs a plurality of programs (performs multitask processing), the CPU performing multitasking and peripheral circuits sequentially switch execution tasks. I have. However, in the case of a task having a heavy load and requiring a long processing time, the task cannot be processed within the allotted time for one task processing, and the processing of the CPU is shifted to another task. Then, the CPU waits until the next processing of the CPU is started, and the processing of the task is restarted after the processing is started. Therefore, there is a problem that a task with a heavy load takes a long time to complete the processing. That is, tasks are switched with a fixed interval timer that determines the task switching time of the CPU.

Further, when a method of controlling task switching based on task priority is used, there is a problem that the load on the CPU increases. That is, since the interval time is set irrespective of the load state of the CPU, task switching occurs when a fixed interval time elapses. CPU for this switching process
Is used, the load on the CPU increases when switching from a task with a heavy load or when switching to a task with a heavy load.

[0004] Japanese Patent Application Laid-Open No. 1-262843 discloses that the value of the interval time is linked to the load state of the CPU.
A method of changing dynamically has been proposed.

[0005]

Problems to be Solved by the Invention
In the case of the proposal described in Japanese Patent Laid-Open No. 3 (Kokai) No. 3, there is a problem that the circuit configuration becomes complicated and the circuit scale increases. That is, a circuit for constantly monitoring the load state of the CPU and a circuit for varying the interval time value according to the load are required.

It is an object of the present invention to provide a C
An object of the present invention is to provide an interval timer circuit for leveling a load on a PU.

[0007]

According to the present invention, there is provided an interval timer circuit for a multitasking computer system for executing a plurality of execution tasks by sequentially switching the execution tasks by using an interval signal. An interval time count clock generating means for generating a clock; an interval signal generating means for generating the interval signal by dividing the interval time count clock; and the interval time count clock according to the load of the task processing. An interval timer circuit characterized by including frequency dividing value control means for controlling the frequency dividing value of the generating means.

The interval time count clock generating means includes an n frequency dividing means for dividing the system clock by n, and a frequency dividing means for dividing the output of the n frequency dividing circuit by two.
A frequency dividing means, and a selecting means for selecting an output of the n frequency dividing means at normal times and an output of the frequency dividing means at the time of processing of a heavier load task. The dividing value control means selectively controls the selection means according to the load of the load.

The operation of the present invention is as follows. For example,
Identify interrupt requests from external events as heavy-duty tasks, and if there is an interrupt request from a heavy-load task, automatically increase the interval clock cycle of the interval timer and set the interval timer count value. The time allotted to the task is extended by extending the time interval of the interval time for switching the task processing without changing the time.

On the basis of an interrupt signal from an external event specified as a heavy-load process, the period of the count clock of the interval timer is directly extended to extend the interval of the interval time without changing the counter set value. ing. Therefore, the load on the CPU is not increased by the additional processing such as changing the count setting value in response to the interrupt signal.

[0011] Furthermore, since the frequency of the count clock supplied to the interval timer is reduced during the allocation time of the task with a heavy load, the power consumption of the interval timer using the count clock is reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an interval timer circuit according to the present invention. 1, an interval timer circuit according to the present invention includes a system clock generator 1 for generating a system clock a, and a CPU for controlling the entire computer system.
2, a peripheral circuit 3 of the CPU 2 and a frequency dividing circuit 4 having a frequency dividing ratio switching function for dividing the system clock a to generate an interval timer count clock d.

An interval timer 5 for counting an interval timer count clock d and generating an interval signal c; an external event interrupt for generating an interrupt signal based on an external event signal b for specifying a task with a heavy load from the external event 7 It has a signal generator 6.

The operation of the embodiment of the present invention will be described. In FIG. 1, a system clock generator 1 supplies a basic clock a of the entire circuit to each unit. A CPU (central processing unit) 2 controls the system of the present embodiment. The peripheral circuit 3 includes a memory, a bus control unit, a DMA controller, an I / O
These are system resources such as ports and peripheral circuits.

A frequency dividing circuit 4 having a frequency dividing ratio switching function is provided with a system clock a supplied from a system clock generator 1.
Is divided to generate a count clock d to be supplied to the interval timer 5. Further, since a task with a heavy processing load for the system of this embodiment is specified, and the count value is kept constant, a clock cycle for securing an interval time corresponding to the processing of the specified task is determined. The frequency dividing circuit 4 with the frequency dividing ratio switching function extends the clock cycle by switching the frequency dividing ratio, and count clocks d for securing an interval time for a task with a heavy load.
Can also be generated.

Further, it has a function of receiving the signal b from the external event interrupt signal generator 6 and automatically switching the frequency division ratio to change the cycle of the count clock (switch the count clock d).

The interval timer 5 measures an interval time, which is a time interval for switching the processing of each task, based on the count clock d from the frequency dividing circuit 4 having a frequency dividing ratio switching function, and outputs an interval signal c to the CPU 2. The external event interrupt signal generator 6 is configured to output the external event 7
The start and end of the external event are notified to the CPU 2 and the frequency dividing circuit 4 having the frequency division ratio switching function in response to an interrupt request from the CPU. The external event 7 informs the system of the present embodiment via the external event interrupt signal generator 6 of the occurrence of a task whose processing load is heavier than that of the system of the present embodiment.

In the time chart of FIG.
When executing the processing of a plurality of tasks, the execution task is switched by the interval signal output by the interval timer 5 for each allocation time, and the allocation and distribution of the system resources of the peripheral circuit 3 are controlled to execute the processing.

When the task processing by the external event 7 which is a heavy load task occurs, the external event interrupt signal generation unit 6 notifies the CPU 2 and the frequency dividing circuit 4 with the frequency division ratio switching function of the occurrence and termination of the external event. . When notified of the occurrence of a task that is heavier than the external event interrupt signal generator 6, the frequency dividing circuit 4 with the frequency dividing ratio switching function divides the system clock a at a frequency dividing ratio larger than the normal frequency dividing ratio and counts it. The period of the clock d is increased.

As a result, the interval time is extended while the count set value for the interval time measurement set in the interval timer 5 is fixed (see FIG. 3). Heavy load task, ie external event 7
Is processed within the extended interval time.

When the external event 7 is completed, the end of the task is notified to the CPU 2 and the frequency dividing circuit 4 having the frequency dividing ratio switching function by the external event interrupt signal generating section 6, and the frequency dividing circuit 4 having the frequency dividing ratio switching function is operated by the count clock. The cycle of d is restored, and the interval time becomes a normal length (see FIG. 3).

FIG. 4 is a detailed block diagram of the frequency dividing circuit 4 having the frequency dividing ratio switching function and the interval timer 5 shown in FIG. In FIG. 4, a system clock a is a basic clock of the present embodiment, and is supplied from the system clock generator 1. The n-divider circuit 9 is a clock divider circuit composed of an FF (flip-flop) circuit or the like, and divides the system clock a by n to generate a n-divided clock. The divide-by-two circuit 10 is a clock divider circuit configured by an FF circuit or the like, like the n-divider circuit 9, and further divides the divide-by-n clock by 2 to generate a 2n-divided clock. The selector 11 switches one of the n-divided clock from the n-divider 9 and the 2n-divided clock from the 2 divider 10 by an external event signal b and outputs it to the divide-by-2 circuit 12.

The external event signal b is a signal for selecting an input clock of the selector 11. Divide-by-2 circuit 12
Is output by dividing the input clock by 2 in the same manner as in the divide-by-2 circuit 10.
This becomes the n-divided clock.

The interval timer 5 uses the clock d input from the divide-by-2 circuit 12 as a count clock, measures an interval time based on a preset count value, and outputs an interval signal c for each interval time.
Is output.

This will be described in detail with reference to the time charts of FIGS. The external event signal b in FIG. 4, that is, the S (select) input of the selector 11 is inactive during a normal task, and at this time, the selector 11 outputs the clock of the input B, that is, the system clock which is the output of the n frequency dividing circuit 9. The clock a is selected by dividing the clock by n (divided by n clock) and output to the divide-by-2 circuit 12. as a result,
The interval timer 5 has a system clock a of 2n.
The frequency-divided clock (2n frequency-divided clock) is supplied as the count clock d. In the time chart of FIG. 3, it corresponds to a section of T0 to T1 and T1 to T2.

When an external event 7 as a task with a heavy processing load occurs, the external event signal b becomes active, and the selector 11 outputs the clock signal of the input A, that is, the output of the divide-by-2 circuit 10. A clock obtained by dividing the clock a by 2n (divided by 2n clock) is selected and output to the divide-by-2 circuit 12.

The divide-by-2 circuit 12 further divides the frequency by 2 and supplies the interval timer 5 with a clock obtained by dividing the system clock a by 4n (4n divided clock) as a count clock d. An interval signal c is output each time the counted value is counted.

The time chart in FIG. 3 corresponds to a section between T2 and T3. Since the cycle of the count clock is doubled in the section between T2 and T3 in FIG.
In this case, the count set value remains set in advance, but the measured interval time, that is, the interval of the interval signal c is doubled. In the meantime, the CPU 2 performs the process of the external event 7.

The time corresponding to the time allotted for the processing of the external event 7, that is, the time corresponding to the section between T2 and T3 in FIG. 3 (in this embodiment, twice the normal interval time) is determined in advance, and the count setting value is set. With fixed
To be able to measure twice the normal interval time,
A count clock d having a clock cycle twice as long as a normal count clock is supplied to the interval timer 5 while the external event signal b is active.

When the external event 7 ends, that is, when the processing of a task with a heavy load ends, the external event signal b becomes inactive, the count clock d supplied to the interval timer 5 becomes a 2n frequency-divided clock, and the interval signal c Also returns to normal (section of T3 to T4 in FIG. 3).

Referring to FIG. 2, another embodiment of the present invention will be described. The embodiment shown in FIG. 2 is basically the same as the embodiment shown in FIG. 1, except that an output clock from a frequency dividing circuit 4 having a frequency division ratio switching function is input to an interval timer 5 and a peripheral circuit 8. ing. The peripheral circuit 8 is a part of the circuit which does not hinder the operation even with the count clock d of the interval timer 5 (both the clock at the normal time and the clock at the time when the external event 7 occurs).

Therefore, while the external event 7, that is, a task with a heavy load is being processed, like the interval timer 5, it operates with a clock having a lower frequency than in the normal state, and thus consumes less power than in the normal state. There is the advantage of being lower.

[0033]

As described above, according to the present invention, the multi-task processing automatically extends the allocation time of task processing when processing a task with a heavy load.
There is an effect that it can be realized without applying a load to U and monitoring the load of the CPU and dynamically expanding or reducing the task processing allocation time dynamically.

That is, a heavily loaded task is specified in advance, and a processing time (interval time) corresponding to the heavily loaded task is determined. When a heavily loaded task occurs, a divider circuit for generating a count clock for an interval counter by a simple selector circuit. By switching the frequency division ratio, the interval time can be easily switched simply by switching the cycle of the count clock.

Further, there is an effect that power consumption can be reduced when processing a task with a heavy load. That is, the frequency of the count clock of the interval timer decreases during execution of a task with a heavy load.

Further, as in the case of the interval timer, the power consumption can be further reduced by lowering the frequency of the clock supplied to the circuit that can lower the clock frequency when executing a task with a heavy load.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a time chart of the embodiment of the present invention.

FIG. 4 is a detailed block diagram of a frequency dividing circuit with a frequency division ratio switching function.

[Explanation of symbols]

 1 System clock generator 2 CPU 3 Peripheral circuit 4 Divider circuit with frequency division ratio switching function 5 Interval timer 6 External event interrupt signal generator 7 External event

Claims (4)

[Claims] 1. An interval timer circuit of a multitasking computer system for executing a plurality of execution tasks by sequentially switching them with an interval signal, wherein the interval clock circuit generates an interval time count clock by dividing a system clock. An interval signal generating means for dividing the interval time count clock to generate the interval signal; and a part for controlling a frequency division value of the interval time count clock generating means according to the load of the task at the time of processing the task. An interval timer circuit including a peripheral value control unit. 2. The system according to claim 1, wherein said interval time count clock generating means comprises: n dividing means for dividing the system clock by n; divide-by-2 means for dividing the output of said n dividing means by 2; 2. The interval timer circuit according to claim 1, further comprising selection means for selecting the output of the n frequency dividing means and the output of the frequency dividing means when processing a task having a heavier load. 3. The interval timer circuit according to claim 2, wherein said dividing value control means selectively controls said selecting means according to the load of said load. 4. The interval timer circuit according to claim 1, further comprising means for supplying an output of said frequency-dividing means as a clock to a peripheral circuit during processing of said heavily loaded task. .