JPH1131068A - Reset vector switching method and information processor using the switching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continue the execution of a program by preparing plural external pins which are operated to instruct the start of a boot access, selecting an external pin, reading a reset vector address equivalent to the selected external pin to start the boot access at the read address, and accordingly restarting the processing at another reset vector at the time of a hardware failure. SOLUTION: A processor unit 1 has two reset pins (RST#0, #1) as the external pins. When these external pins are operated, the reset vector addresses equivalent to the external pins or another ROM 2 is accessed as necessary for the start of a boot access. As a result, an initialization program can be continuously processed even in the case of a hardware failure as long as the program processing is automatically started at another reset vector or another ROM 2 as necessary. Thus, the high reliability is secured for an information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector address switching method and an information processing apparatus using the method.

[0002]

2. Description of the Related Art With advances in semiconductor technology, microprocessors, memory LSIs, and peripheral LSIs have been supplied at a low cost. An information processing device such as a personal computer can be constructed. Further, by installing an operating system (OS), which has become a standard, in this information processing apparatus, abundant distribution software can be utilized, and data can be shared between the information processing apparatuses. .

By the way, the microprocessor which is the control center of the information processing apparatus described above starts executing the program from the address "****" as soon as the power is turned on. Therefore, a ROM that can store programs even when the power is turned off is required. Also, the microprocessor has a reset signal input terminal, and when a signal is supplied to it, various registers including the built-in program counter are cleared to zero and the memory is initialized, starting from the address "****" in the memory. Read the instruction and start the operation. FIG. 7 is a flowchart showing a conventional reset operation. The reset vector address is fixed. The program is read from the relevant address, a hardware test including a memory is performed, the OS is started, the hardware is initialized, and the application program is started.

[0004]

In the above-mentioned information processing apparatus having a microprocessor as a control center, even some of the hardware constituting the information processing apparatus breaks down and locks or stops the apparatus itself. . At this time, the reset switch is pressed down to try to start up the system again. However, if the ROM is faulty, the program processing cannot be continued. That is, since there is only one reset vector, the program stops when some hardware such as the ROM and the bus fails during the execution of the program. Here, even if the reset operation is attempted again, if the above-mentioned hardware failure occurs, the program stops again at the same place, and the processing cannot be continued.

The present invention has been made in view of the above circumstances, and has a plurality of reset vectors. When a hardware failure occurs, processing is restarted from another reset vector to avoid use of the hardware. It is an object of the present invention to provide a reset vector switching method for continuing program execution and an information processing apparatus using the same.

[0006]

SUMMARY OF THE INVENTION A reset vector switching method according to the present invention has at least two external pins operated to instruct to reset hardware and start boot access from a predetermined address. A reset vector address corresponding to the external pin is read by selecting and operating the external pin, and boot access is started from the address. Also, a rewritable register in which a boot access start address is set is allocated in the device, and when the power is turned on, the boot access is started from the written address with reference to the register.

The information processing apparatus of the present invention resets the memory storing the boot program and the hardware constituting the apparatus when the apparatus is initialized, and starts boot access from a predetermined address of the memory. A processor unit having at least two external pins operated for instructing, and a reset vector address corresponding to the external pin is read by selecting and operating the external pin, and boot access is started from the address. And a memory access control circuit. In addition, a memory in which a boot program is stored, a processor unit having a rewritable register in which a boot access start address is set, and when power is turned on, the boot access is started by referring to the register and writing the address. And a memory access control circuit.

With the above-described configuration, the use of the hardware can be avoided by having a plurality of reset vectors and restarting the processing from another reset vector when a hardware failure occurs. Can be continued, and the reliability is improved.

[0009]

FIG. 1 is a block diagram showing a configuration example of an information processing apparatus according to the present invention. In the figure, 1 is a processor unit. The processor unit 1 used in the embodiment of the present invention is a DIP having as many as 80 signal pins.
(Dual inline package) or QF
It is housed in a P (quad flat, package) package. Characteristically, two reset pins (RST # 0, RST # 0,
RST # 1), each having a corresponding reset vector, a register 11 for setting a reset vector address and a counter 12 being allocated, and a built-in nonvolatile memory 13 for storing the reset vector. It is. In the embodiment of the present invention, a flash memory is used as a non-volatile memory. The flash memory is not necessarily built in the processor unit 1 and may be externally attached. Details will be described later.

Reference numeral 2 denotes a ROM, and 3 denotes a RAM, which is read / written via a memory control circuit 4. 5 is a data bus and 6 is an address bus.

FIGS. 2 to 6 are views cited for explaining the operation of the embodiment of the present invention. The switching operation of a reset vector by an external pin, the switching of a reset vector by a register read, the switching of a reset vector by a register and a counter, the switching of a reset vector by an external pin and a counter, and the switching operation of a reset vector by a counter and a register are shown, respectively.

The operation of the embodiment of the present invention shown in FIG. 1 will be described below with reference to the flowcharts shown in FIGS.

In the flowchart shown in FIG. 2, a plurality of external pins operated to instruct to reset hardware and start boot access from a predetermined address are required. In the embodiment of the present invention, the processor unit 1
Indicates that two reset pins (RST # 0, RST # 0,
1) Have. By selecting and operating the external pin, a reset vector address corresponding to the external pin,
In some cases, another ROM 2 is accessed to start boot access.

That is, first, a reset signal is generated (S22) by turning on the power (S21). For example, a “LOW” level signal is output from the system
Keep input to T terminal. After the device reset (S23), the information of the external pin is read (S24), and the reset vector address corresponding to the specified external pin is read (S2).
5) Then, the program is read and executed from the address.

In the flowchart shown in FIG. 3, a rewritable register in which a boot access start address is set must be allocated in the processor unit 1.
It may be allocated to a register file built in the processor unit 1 or may be externally attached. When the power is turned on, the processor unit 1 refers to the contents of the register 11 and starts boot access of the ROM 2 from the written address.

That is, when the power is turned on (S31), a reset signal is generated (S32), and the device is reset (S33).
After that, the register 11 containing the reset vector address
Is read (S34), and booting is started from that address.

Note that the contents of the register 11 are also written in the flash memory 13, and the contents once written here are set by default until they are rewritten. A specific address at the time of power-on is set in the register 11, and thereafter, a value is held regardless of power-on / off.

In the flowcharts shown in FIGS. 4 and 5, in addition to the above-described configuration, a counter 12 that starts counting upon turning on the power is required. The operation of the counter 12 can be stopped by the processor unit 1. When the counter 12 reaches a designated value, the information processing device is reset, and when the counter does not stop, the information processing device is forcibly reset, and boot access is started from an external pin or an address indicated by the register 11. .

That is, in the flowchart shown in FIG. 4, a reset signal is generated (S41) by turning on the power (S41).
42), and after the device is reset (S43), the register 1
The value of 1 is read (S44). When the register value is “0”, the reset vector address, for example, “0 * 000”
0 is read, and when it is "1", the reset vector address "0 * FF00" is read.

On the other hand, when the power is turned on, the counting by the counter 12 is started (S46), and it is checked whether or not a predetermined value has been counted (S47). Here, when a specific value is checked, a default value "0" is set in the register 11 (S48), and the other components are reset (S49).

In the flowchart shown in FIG. 5, a reset signal is generated by turning on the power (S51), and after the device is reset (S52), the reset vector address "0 * 0" is set.
000 "is read (S53), and the boot process is started from that address.
2 is started (S54), and a check is made (S55) until a specific value is counted. Here, when a specific value is detected, a soft reset is executed. In the soft reset, the external pin is read (S57), and the address corresponding to the specified external pin is read (S58).
And restart the boot process. If no specific address is detected, it is checked whether or not a stop instruction of the counter has been issued (S59), and the above flow is repeated when there is no stop instruction.

Note that software reset does not simply involve connecting an output port to a reset terminal and outputting a required level. This is because the operation from the original power ON must be properly initialized.
In the embodiment of the present invention, the HALT signal is used as a trigger for software reset. Therefore, the reset can be performed by executing the HALT instruction. Here, the reset output by the hard wired circuit is called a hardware reset, and the reset by the output of the counter 12 is called a software reset. A reset input of the processor unit 1 or a device that is to be reset programmatically is obtained by ORing these two reset signals, and resetting is performed by both.

In the flowchart shown in FIG. 6, when the power is turned on, booting is started from a specific address, and a counter 12 is allocated in the processor unit 1. The counter 12 counts up at the same time when the power is turned on. Is started, and a reset signal is supplied to the information processing apparatus when the designated count value is reached. Further, the processor unit 1 has a register 11 which can instruct the counter 12 to stop counting up and which is cleared only when the power is turned on. The value is stored in the register 11 before the counter 12 issues the reset instruction. At this time, if the counter 12 is not stopped, the information processing apparatus is automatically reset. At this time, if the value of the register 11 is not the initial value, booting is started from an address other than the reset vector.

That is, a reset signal is generated by power ON (S61) (power ON reset S62), and after the device is reset, the register 11 is read (S63) and its value is checked (S64). Here, the register value is “0”
, The reset vector address “0 * 0000” is
If it is not "0", "0 * FF00" is read, and the boot process is started from that value. On the other hand, the counting by the counter 12 is started at the same time when the power is turned on (S65), and it is checked whether or not a specific value is counted (S66).
Here, when a specific value is detected, the value "1" is set in the register 11 (S67), and a software reset (S68) is executed. Incidentally, the register 11 is set to "0" at the time of a power ON reset, and retains or presets the previous value at the time of a software reset.

As described above, the present invention has at least two external pins which are operated to instruct to reset hardware and start boot access from a predetermined address, and select and operate the external pins. By reading the reset vector address corresponding to the external pin, a boot access is performed, or a rewritable register in which a boot access start address is set is assigned in the device. , A multi-boot access is realized by starting a boot access from the written address.

[0026]

As described above, according to the present invention, a plurality of reset vectors are provided, and when a hardware failure occurs, the processing is restarted from another reset vector, thereby avoiding the use of the hardware. Execution can be continued. As a result, even if there is a hardware failure, the initialization program can be continued by automatically starting from a different reset vector or, in some cases, from another ROM, providing a highly reliable information processing apparatus. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of the conventional example.

[Explanation of symbols]

1 processor unit, 2 ROM, 3 RAM, 4
... Memory control circuit, 5 data bus, 6 address bus, 11 register, 12 counter, 13 flash memory.

Claims (8)

[Claims] The present invention has at least two external pins operated to instruct to reset hardware and start boot access from a predetermined address. A reset vector switching method comprising: reading a reset vector address corresponding to (i) and starting a boot access from that address. 2. A rewritable register in which a boot access start address is set is allocated in the device, and when the power is turned on, the boot access is started from the written address with reference to the register. Reset vector switching method. 3. The reset vector address switching method according to claim 2, wherein the register is allocated to a nonvolatile memory, and the content once written is set as default until the content is rewritten. 4. A memory in which a boot program is stored and a hardware which constitutes the device are reset at the time of initialization of the device, and are operated to instruct to start boot access from a predetermined address of the memory. A processor unit having at least two external pins, a memory access control circuit that reads a reset vector address corresponding to the external pin when the external pin is selected and starts a boot access from the address; An information processing apparatus comprising: 5. A memory in which a boot program is stored, a processor unit having a rewritable register in which a boot access start address is set, and when power is turned on, booting from an address written with reference to the register. An information processing apparatus comprising: a memory access control circuit for starting access. 6. When power is turned on, a boot access is performed from a specific reset vector, a count is started at the same time as power is turned on, and a counter capable of instructing a count stop by a device is provided, and the counter reaches a designated value. 5. The information processing apparatus according to claim 4, wherein when the counter is not stopped, the apparatus is reset, and when the counter does not stop, the apparatus is reset, and boot access is started from an address indicated by the external pin. 7. When power is turned on, boot access is performed from a specific reset vector, and a register for selecting a reset vector and counting are started at the same time as power is turned on.
It has a counter that can instruct counting stop by the device, resets the device when the counter reaches the specified value, forcibly resets the device when the counter does not stop, and performs boot access from the address indicated by the register. The information processing apparatus according to claim 5, wherein the information processing apparatus is started. 8. When the power is turned on, a boot access is performed from a specific reset vector, and is cleared at the same time as the power is turned on, and an appropriate value is written before a reset issued when the counter reaches a specified value. 8. The information processing apparatus according to claim 7, further comprising a register, wherein the boot access is started from an address other than the reset vector when the register is not an initial value.