JPH11261076A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate transistor which is capable of operating at a high speed, by a method wherein a gate electrode and a gate wiring are formed of aluminum material so as to be lessened in resistance, and a silicide layer is formed on the surfaces of source/drain regions so as to lessen the source/drain regions in sheet resistance. SOLUTION: A gate electrode 2000 is equipped with a laminated conductive film composed of a metal layer 2110 which is formed to come into contact with a gate insulating film 1300 and an aluminum layer 2200, and the laminated conductive films are equipped with a metal layer formed on the side of the metal layer 2100 and an alumina layer formed on the surface of the aluminum layer 2200 by anodizing. By this constitution, the laminated conductive films are each covered with anodic oxide layers 2110 and 2210. The metal layer 2110 is formed of metal material whose melting point is higher than that of aluminum, so that the metal layer 2110 functions as a barrier layer to prevent aluminum from diffusing into the gate insulating film 1300. Therefore, a heat treatment can be carried out at temperatures of 500 to 650 deg.C after the gate electrode 2000 is formed, so that silicide layers 1111 and 1121 can be formed through a silicide, process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device including a semiconductor circuit having a plurality of insulated gate transistors such as a thin film transistor using a semiconductor thin film, and a method of manufacturing the same. The semiconductor device of the present invention includes an electronic device having a semiconductor circuit including an insulated gate transistor, such as an active matrix liquid crystal display device and an image sensor.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display in which a pixel matrix circuit and a driving circuit are constituted by thin film transistors (hereinafter abbreviated as TFTs) formed on an insulating substrate has been receiving attention. Liquid crystal displays include those for projectors of about 0.5 to 2 inches and those for notebook computers of about 10 to 20 inches, and are mainly used as small to medium display displays.

In recent years, the area of a liquid crystal display has been required to be increased. However, when the area is increased, the area of a pixel matrix circuit serving as an image display section is also increased, and accordingly, source lines and gates arranged in a matrix are arranged. Since the wiring and the like become longer, the wiring resistance increases. Further, it is necessary to make the wiring thinner for the demand for miniaturization, and the increase in the wiring resistance becomes more apparent. In addition, the source wiring and the gate wiring include:
Since a TFT is connected to each pixel and the number of pixels increases, an increase in parasitic capacitance also poses a problem. In a liquid crystal display, generally, a gate wiring and a gate electrode are integrally formed, and a delay of a gate signal becomes conspicuous as the area of the panel increases.

Therefore, a material mainly composed of aluminum having a low specific resistance is used for the gate wiring. When the gate wiring and the gate electrode are formed using a material containing aluminum as a main component, a gate delay time can be reduced and high-speed operation can be performed.

Further, for high-speed operation, it is necessary to reduce the sheet resistance between the source / drain regions and the source / drain wiring connected to these regions. In order to reduce the resistance of the source / drain region, a silicide layer with a high melting point metal such as Ta or Ti is formed on the surface of the source / drain region.

[0006]

SUMMARY OF THE INVENTION Aluminum materials are:
While having the advantage of low resistance, it has the disadvantage of low heat resistance. Therefore, when the gate electrode and the gate wiring are formed of a material containing aluminum as a main component, it is difficult to use a salicide (salicide, self-aligned silicide) process to silicide the surface of the source / drain region. It is.

Since hillocks and whiskers are liable to be generated when aluminum is subjected to heat treatment, the upper limit of the process temperature is limited to the range of 300 to 450 ° C. in the steps after the formation of the gate electrode and the gate wiring. ,

However, in the case of a TFT using an aluminum wiring, protrusions such as hillocks and whiskers generated at the gate electrode penetrate the gate insulating film and reach the channel formation region even at a heating temperature in the range of 300 to 450 ° C. In addition, a malfunction of the thin film transistor due to a short circuit between the gate electrode and the channel, which is considered to be caused by aluminum atoms diffusing into the gate insulating film, was confirmed.

On the other hand, silicidation of the source / drain regions requires a heat treatment at a temperature exceeding 400 ° C. L
In the field of SI, titanium silicide is mainly used for the purpose of reducing the sheet resistance of the source / drain regions. To form titanium silicide by reacting a titanium (Ti) film with silicon, 500 to Heat treatment at about 600 ° C. is required.

Conventionally, the heat resistance of aluminum wiring, T
From the viewpoint of the reliability of the FT, the silicidation process could not be performed after forming the gate electrode and wiring made of aluminum.

The present invention solves the above-mentioned problems by reducing the resistance of the gate electrode and wiring by using an aluminum material as the gate electrode and gate wiring material, and forming a silicide layer on the surface of the source / drain region. It is another object of the present invention to provide an insulated gate transistor capable of operating at high speed and simultaneously realizing a reduction in sheet resistance of source / drain regions, and a method for manufacturing the same.

In particular, it is an object of the present invention to provide a technique in which aluminum atoms are not diffused into a gate insulating film even if a heat treatment step is added after forming a wiring using an aluminum material, and an insulated gate transistor is manufactured with a high yield. To be able to

[0013]

According to another aspect of the present invention, there is provided a semiconductor device including a semiconductor circuit including a plurality of insulated gate transistors formed on a same substrate. A gate electrode is formed in close contact with the gate insulating film, and has a melting point higher than that of aluminum;
An anodic oxidation layer of the metal material formed on the side surface of the metal layer, an aluminum layer or a material layer containing aluminum as a main component formed on the metal layer, and the aluminum layer or aluminum as a main component. An aluminum layer formed by anodizing aluminum formed on the surface of the material layer to be formed, and a silicide layer is formed at least at a connection portion between the source region and the drain region at the source electrode and the drain electrode. It is characterized by having.

Another structure of the semiconductor device is a semiconductor device including a semiconductor circuit composed of a plurality of thin film transistors formed on the same substrate, wherein a gate electrode of the thin film transistor is in close contact with the gate insulating film. A formed tantalum layer, a tantalum oxide layer formed on a side surface of the tantalum layer, an aluminum layer or an aluminum-based material layer formed in close contact on the tantalum layer, and the aluminum layer or aluminum. An alumina layer formed on the surface of a material layer mainly containing
And a silicide layer is formed in the source region and the drain region at least at a connection portion with the source electrode and the drain electrode.

Further, according to the present invention, a method of manufacturing a semiconductor device including a semiconductor circuit including a plurality of thin film transistors formed on the same substrate includes an active layer made of a material containing silicon as a main component, A first step of forming a gate insulating film in close contact with the active layer, a second step of forming a tantalum layer in close contact with the gate insulating film, and a step of forming aluminum or aluminum in close contact with the tantalum layer. A third step of forming a material layer as a component and a first anodizing treatment selectively anodizing the aluminum or the material layer containing aluminum as a main component, and forming a porous alumina layer on a side surface thereof; And anodizing the aluminum layer or the material layer containing aluminum as a main component by a fourth anodic oxidation treatment to form a nonporous surface on the surface. A fifth step of anodizing the tantalum layer and forming a tantalum oxide layer on the side surface at the same time as forming the lumina layer; and patterning the gate insulating film to form a surface of the source and drain regions of the active layer. A sixth step of exposing the source and drain regions; a seventh step of removing the porous alumina layer; an eighth step of adding an impurity imparting conductivity to the source and drain regions; At least a ninth step of silicidizing the surface.

[0016]

Embodiment An embodiment of the present invention will be described with reference to FIG.

FIG. 13 is a schematic view for explaining the structure of the present invention, and shows a cross-sectional view of a thin film transistor. FIG.
Although only one thin film transistor is shown in FIG. 1, a plurality of thin film transistors are formed over a substrate 1000 to form a semiconductor circuit.

The thin film transistor includes an active layer 1100 containing silicon as a main component formed on a substrate 1000 having an insulating surface, a gate insulating film 1200, and a gate electrode 2.
000, source electrode 1410, and drain electrode 1420
And The gate electrode 2000 and the source / drain electrodes 1410 and 1420 are electrically insulated by an interlayer insulating film 1300.

The active layer 1100 includes a source region 1110,
The semiconductor device includes a drain region 1120 and a channel formation region 1130, and the surfaces of the source region 1110 and the drain region 1120 are silicided to form silicide layers 1111 and 112.
1 is formed.

The gate electrode 2000 includes a metal layer 2110 formed in contact with the gate insulating film 1300 and an aluminum layer 22 formed in contact with the metal layer 2110.
00 and a metal layer anodic oxide layer 2110 formed on the side surface of the metal layer 2110 and an alumina layer formed by anodizing the surface of the aluminum layer 2200. With this configuration, the laminated conductive film is covered with the respective anodic oxide films, so that the insulating property is improved and the heat resistance of the aluminum layer 2200 is also improved.

In the present invention, the metal layer 2110 can be anodized and formed of a metal material having a melting point higher than that of aluminum to function as a barrier layer for preventing aluminum from being diffused into the gate insulating film 1300. Therefore, heat treatment at 400 ° C. or more can be performed after the formation of the gate electrode 2000, and the heating temperature can be increased to about 500 to 600 ° C.

As such a metal layer 2210, a valve metal can be used, and Ta, Nb, Hf, Ti, Cr
Any one of metal elements or alloys thereof, or M
An alloy of o and Ta may be used. Aluminum layer 2
For 000, not only pure aluminum but also Si, Sc or the like may be added by several weight% to improve heat resistance.

In the present invention, since the heating can be performed at a temperature of 500 to 650 ° C. after the gate electrode 2000 is formed, the silicide layers 1111 and 1121 can be formed in the source / drain regions by a salicide process. .

Method 1 for manufacturing the thin film transistor of FIG.
An example is described below. An active layer 1100 containing silicon as a main component is formed over a substrate 1000 having an insulating surface.
As the active layer 1100, a polycrystalline silicon thin film obtained by crystallizing an amorphous silicon thin film may be used. For crystallization,
In consideration of the heat resistance of the substrate, a heat treatment, a method of irradiating a laser or a strong light equivalent thereto, or the like may be appropriately selected. Then, an insulating film constituting the gate insulating film 1200 is formed over the active layer 1100.

Next, a gate electrode 2000 is formed. A metal layer 2100 and an aluminum layer 2200 are formed and patterned into a predetermined shape. Anodizing is performed to form anodic oxide layers 2110 and 2120, respectively. Thus, the gate electrode 2000 is completed. In the present invention, since the aluminum layer 2200 is mainly used as a signal and current path in the gate electrode 2000, the thickness thereof is 400 to 6
It is about 50 nm. The metal layer may function as a barrier layer as described later, and has a thickness of 10 to 100.
nm.

Next, by using the gate electrode 2000 as a mask, the insulating film is patterned to form a gate insulating film 1300 in a self-aligned manner. Further, using the gate electrode 2000 as a mask, an impurity for imparting conductivity to the active layer 1100 is added to the source / drain regions 1110 and 112.
0 and a channel forming region 1130 are formed in a self-aligned manner.

Next, the source / drain regions 1100, 1
200, silicide layers 1111 and 1121 are formed.
First, a metal film which reacts with silicon with silicide is formed. The metal film may be a metal film that undergoes a silicide reaction at a heating temperature of about 500 to 600 ° C., and for example, any one of Ta, Cr, Mn, Nb, Mo, and Ti can be used. The metal film is an active layer 1100
Are in contact only with the source / drain regions 1110 and 1120, and are subjected to the heat treatment.
The silicide layers 1111 and 1121 are formed by the reaction between silicon and the metals 10 and 1120. Source /
The drain regions 1110 and 1120 may be completely silicided.

After silicidation, the unreacted metal film is removed by etching. At this time, since the metal layer 2100 and the aluminum layer 2200 of the gate electrode 2000 are covered with the respective anodic oxide layers 2110 and 2210, they are not removed by etching. Note that the heat treatment for silicidation may be performed by heating in an electric furnace or RTA using an infrared lamp.

Then, an interlayer insulating film 1300 is formed, a contact hole is formed therein, and the source / drain electrode 1300 is formed.
410 and 1420 are formed.

In the present invention, an aluminum layer 2200 is used for the gate electrode 2000, and a silicide layer 1111 is connected to the connection with the source / drain electrodes 1410 and 1420.
And 1121, the operation speed is improved and power consumption can be reduced. Although a thin film transistor is shown here as an example of an insulated gate transistor, the present invention relates to a transistor having a source / drain region in a silicon substrate.
The present invention can be applied to an OS transistor.

[0031]

Embodiment An embodiment of the present invention will be described in detail with reference to FIGS.

[Embodiment 1] In this embodiment, a method for manufacturing a TFT constituting a semiconductor circuit will be described. FIG. 1A shows a schematic cross-sectional configuration diagram of the TFT of this embodiment. FIG.
FIG. 1B is an enlarged view of a rectangular area indicated by 150 in FIG.

A base film 101 is formed on the surface of the substrate 100. The TFT has an active layer 103 formed on a base film 101, a gate insulating film 109, a gate electrode, an interlayer insulating film 103, and a source electrode 141 and a drain electrode 142 connected to source / drain regions.

The active layer 103 is made of a polycrystalline silicon thin film, and has a source region 104, a drain region 105, a channel forming region 106, and high resistance regions 107 and 108 formed thereon.
Silicide layers 104a and 105a are formed respectively.

The gate insulating film 109 is formed by a thermal oxide film 109b obtained by thermally oxidizing the surface of the active layer 103 and a deposited insulating film 109a deposited by a vapor phase method (CVD). In addition, a gate electrode includes a tantalum layer 110 and an aluminum layer 120.
In addition, the tantalum layer 110 and the aluminum layer 120 have an anodized tantalum oxide layer 111 and a nonporous alumina layer 121, respectively.

Hereinafter, a method of manufacturing a TFT will be described with reference to FIGS. First, a substrate 100 having high heat resistance (quartz substrate in this embodiment) is prepared. An insulating silicon film 102 having a thickness of 300 nm is formed as a base film 101 on the surface of a substrate 100. The insulating silicon film includes a silicon oxide film (SiO _x ),
Silicon nitride film (Si _x N _y), silicon oxynitride film (SiO _x
N _y ) or a laminated film thereof.

The heat-resistant temperature of the substrate 100 may be any temperature that can withstand the subsequent thermal oxidation step. If the strain point is 750 ° C. or higher, a glass substrate (typically, a material called crystallized glass, glass ceramics, or the like) can be used. In this case, it is effective to form the base film by a low-pressure thermal CVD method and surround the entire surface of the substrate with an insulating silicon film because diffusion of the component material from the glass substrate is suppressed.

As the underlayer 101, the substrate 100
It is also possible to use an insulating film whose entire surface is covered with an amorphous silicon film and which is completely transformed into a thermal oxide film. When a silicon substrate is used, the base film 101 is formed by thermally oxidizing the surface of the silicon substrate.

When a substrate having an insulating surface is thus prepared, an amorphous silicon film 201 is formed by a low pressure thermal CVD method. The thickness of the amorphous silicon film 201 is 20 to 100 nm
(Preferably 40 to 75 nm). In this embodiment, the film thickness is 65 nm. Note that a plasma CVD method may be used as long as film quality equivalent to that of an amorphous silicon film formed by a low-pressure thermal CVD method can be obtained. (Fig. 2 (A))

Next, a 120 nm film is formed on the amorphous silicon film 201.
A mask insulating film 201 made of a thick silicon oxide film is formed.
An opening 2 is formed in the mask insulating film 202 by patterning.
02a is provided.

Next, according to the technique described in JP-A-8-78329, a step of adding a catalytic element for promoting crystallization is performed. In this embodiment, nickel is selected as a catalyst element,
A solution prepared by dissolving nickel acetate containing 10 ppm by weight of nickel in an ethanol solution is applied by spin coating.

Of course, in addition to nickel, cobalt (C
o), iron (Fe), palladium (Pd), platinum (P
t), copper (Cu), gold (Au), germanium (G
e) and one or more selected from lead (Pb) may be used.

Thus, the nickel-containing layer 203 is formed on the surface of the mask insulating film 202. At this time, nickel comes into contact with the amorphous silicon film 201 at the opening 202a provided in the mask insulating film 202.
(FIG. 2 (B))

Next, after heating at 450 ° C. for about 1 hour to perform dehydration treatment, the atmosphere is heated to 500 to 700 ° C. (typically 550 to 700 ° C.) in an inert atmosphere, a hydrogen atmosphere or an oxygen atmosphere.
The amorphous silicon film 201 is crystallized by applying a heat treatment at a temperature of 650 ° C., preferably 570 ° C.) for 4 to 24 hours.
In this embodiment, heat treatment is performed at 570 ° C. for 14 hours to promote crystallization. (Fig. 2 (C))

The crystallization of the amorphous silicon film 201 proceeds preferentially from the nucleus generated in the nickel-added region (nickel-added region) 204 and grows substantially parallel to the substrate surface of the substrate 100. (Here we call it the lateral growth area)
205 and 206 are formed. Lateral growth areas 205, 20
6 has the advantage of excellent overall crystallinity since individual crystal grains are aggregated in a relatively uniform state.

After the crystallization step is completed, phosphorus (P) is added using the mask insulating film 202 as a mask to form a phosphorus-added region 207. Phosphorus is addition area 2
It is preferable to add so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ (about 10 times as large as nickel). (FIG. 2 (D))

In this embodiment, the gettering ability of phosphorus is used to remove nickel remaining in the lateral growth regions 205 and 206. In addition to phosphorus, other Group 15 elements such as arsenic and antimony can be used, but phosphorus has high gettering ability.

In this embodiment, the plasma doping method is used for the phosphorus addition step, but other ion implantation methods such as an ion implantation method or a plasma doping method,
Either a method using diffusion from a gas phase or a method using diffusion from a solid phase can be used. The mask insulating film 202 used as a mask in the step of adding phosphorus may be patterned again to provide a new opening, but by using the mask insulating film 202 as it is, the throughput can be improved.

Then, after forming the phosphorus-added region 207, 500 to 800 ° C. (preferably 600 to 650 ° C.)
Is performed for 2 to 24 hours (preferably 8 to 15 hours) to move the nickel in the lateral growth regions 205 and 206 to the phosphorus-added region 207 (the moving direction is indicated by an arrow). The lateral growth regions 205 ′ and 206 ′ can be obtained reduced to × 10 ¹⁷ atoms / cm ³ or less (preferably 2 × 10 ¹⁷ atoms / cm ³ or less). (Figure 2
(E))

[0050] Since at present it is the lower limit of detection is 2 × 10 ¹⁷ atoms / cm ³ order by SIMS (secondary ion mass spectroscopy), it is impossible to examine the less concentration. However, if the gettering step shown in this embodiment is performed,
It is estimated that the nickel concentration in the lateral growth regions 205 ′ and 206 ′ is reduced to at least about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm ³ .

After the nickel gettering step is completed, the mask insulating film 202 is removed, and
As shown in (F), the active layer 103 is formed using only the lateral growth regions 205 ′ and 206 ′. At this time, it is desirable that the region 207 where the nickel is gettered is completely removed. By doing so, it is possible to prevent nickel from being back-diffused into the active layer 103 again. Although only one active layer 103 is shown in the drawings for the sake of explanation, a plurality of active layers are simultaneously formed on the substrate 100 in accordance with the TFT constituting the semiconductor circuit.

Next, plasma CVD or reduced pressure heat C
The deposited insulating film 109a made of an insulating silicon film is formed by the VD method.
Is formed so as to cover the active layer 103. This insulating film 10
The thickness of 9a may be 50 to 150 nm. As an insulating silicon film, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film may be formed.

Then, after forming the deposited insulating film 109a as shown in FIG.
To 1100 ° C. (preferably 950 to 1050 ° C.) to oxidize the surface of the active layer 103 and
A thermal oxide film 109b is formed on the interface between the third insulating film 109a and the deposited insulating film 109a.

The oxidizing atmosphere is a dry O ₂ atmosphere,
The atmosphere may be a wet O ₂ atmosphere or an atmosphere containing a halogen element (typically, hydrogen chloride). When a halogen element is included, a nickel gettering effect by the halogen element can be expected if the insulating film 109a on the active layer 103 is thin.

The optimum temperature and time for the thermal oxidation step may be determined in consideration of the thickness of the thermal oxide film and the throughput. In this embodiment, the conditions (950 ° C., 30 minutes) for forming the thermal oxide film 109a of 50 nm are used. At the same time, the active layer of 25 nm is reduced, and finally the thickness of the active layer is 40 nm.
nm.

The structure in which the deposited insulating film 109a is formed and then thermally oxidized has an effect of preventing the diffusion of phosphorus from the gas phase. The phosphorus is phosphorus added before the gettering step (here, phosphorus contained in the underlying film), and diffuses into the atmosphere of the thermal oxidation step to form the active layer 1.
03 (also referred to as auto-doping of phosphorus) can be prevented.

Of course, the active layer 103 and the deposited insulating film 109a
The interface state is greatly reduced by thermally oxidizing the interface with
It also serves to dramatically improve the interface characteristics. Also, C
The film quality of the deposited insulating film 109a formed by the VD method can be improved, and the thinning of the active layer 103 can be expected to reduce the light leakage current, and the intracrystalline defects of the polycrystalline silicon constituting the active layer 103 can be expected. Is also reduced.

When the state shown in FIG. 3G is obtained,
50 nm thick tantalum layers 110 and 400 by sputtering
An aluminum layer 120 having a thickness of nm is sequentially formed. As the aluminum layer 120, an aluminum material containing 2 wt% of scandium was used. Tantalum layer 110
If the film has a thickness of 20 nm, it functions as a barrier layer, but if it is too thick, the unevenness of the TFT becomes large.
The thickness may be about 0 nm. (FIG. 3 (H))

Next, a photoresist mask 209 was formed, and the tantalum layer 110 and the aluminum layer 120 were etched by a dry etching method or a wet etching method, thereby forming a laminated pattern 210 serving as a prototype of a gate electrode later. In this embodiment, the gate electrode and the gate wiring for inputting a signal to the gate electrode are integrally formed. Although only the gate electrode crossing the active layer of the TFT is shown in the drawing, the pattern of the stacked layer 210 is formed in accordance with the pattern of the gate electrode and the gate wiring.

As an etching gas for dry etching, a chlorine-based gas can be used for etching the aluminum layer 120 and a fluorine-based gas can be used for etching the tantalum layer 110, so that continuous processing can be performed. It has been confirmed that when the tantalum layer 110 is as thin as about 50 nm, the aluminum layer 120 and the tantalum layer 110 can be collectively etched with a chlorine-based gas. (FIG. 3 (I))

Although the resist mask 209 is used for patterning the laminated pattern 210, before forming the resist mask 209, the surface of the aluminum layer 120 is anodized extremely thinly to form an alumina film, The adhesion of the mask 209 is improved.

Next, with the resist mask 209 left, anodic oxidation treatment is performed in a 3% oxalic acid aqueous solution at an ultimate voltage of 8 V to form a porous alumina layer 211 having a thickness of 600 to 800 nm. In this solution, the tantalum layer 110 is not anodized, and only the aluminum layer 120 is selectively anodized to form the porous alumina layer 211. (Fig. 3 (J))

After the resist mask 209 is removed, an anodic oxidation treatment is performed at an ultimate voltage of 80 V in an ethylene glycol solution containing 3% tartaric acid. In this process, both the aluminum layer 120 and the tantalum layer 110 are anodized. (Fig. 3 (K))

The tantalum layer 110 is a porous alumina layer 2
Only the portion in contact with 11 was anodized and transformed into tantalum oxide layer 111. This is because only that portion contacts the electrolytic solution that has permeated the inside of the porous alumina layer 211.

The aluminum layer 120 is also oxidized at the portion that has come into contact with the electrolytic solution that has permeated the inside of the porous alumina layer 211, and the surface thereof (the inside of the porous alumina layer 211) has a thickness of 100 to 120 nm. Porous alumina layer 1
21 are formed. The thickness of the non-porous alumina layer 121 is determined by the ultimate voltage.

Here, SE showing the state shown in FIG.
An M photograph is shown in FIG. FIG. 11A is an SEM photograph of a sample obtained by experimentally reproducing the structure of FIG.
The state of the vicinity is shown.

FIG. 11A is a schematic view of FIG.
(B). In FIG. 11B, reference numeral 10 denotes a base made of a silicon oxide film, 11 denotes a tantalum layer, 12 denotes an aluminum layer, 13 denotes a tantalum oxide layer, 14 denotes a nonporous alumina layer, and 15 denotes a porous alumina layer. .

As shown in FIG. 11 (B), the surface of the aluminum layer 12 is covered with a non-porous alumina layer 14, and a porous alumina layer 15 is formed outside thereof. Then, the end of the tantalum layer 11 (below the porous alumina layer)
Has a tantalum oxide layer 13 formed thereon.

Although the thickness of the tantalum layer 110 and the thickness of the tantalum oxide layer 111 are the same in FIG. 3, the tantalum layer is changed to the tantalum oxide layer by anodizing treatment as seen in the photograph shown in FIG. It seems that the volume expands about twice when denaturation occurs, and the film thickness increases to about 2 to 4 times (typically 3 times). Further, the tantalum oxide layer 13 protruded outside the end of the alumina layer 15. In addition, it is expected that the portion indicated by 15 completely contains not only tantalum oxide but also tantalum.

After the structure shown in FIG. 3K is obtained, the gate electrode portion (tantalum layer 110, tantalum oxide layer 111, aluminum layer 120, alumina layer 121) is obtained.
And a deposition insulating film 109a and a thermal oxide film 109 by dry etching using the porous alumina layer 211 as a mask.
b was etched to pattern the gate insulating film 109. 55 scc of CHF ₃ gas as etching gas
m and a pressure of 55 mtorr and a supply power of 800 W.

In this step, the deposited insulating film 109a and the thermal oxide film 109b were etched in a self-aligned manner, and the gate insulating film 109 was processed into an island pattern. At this time, as described with reference to FIG. 11, since the tantalum oxide layer 111 protrudes to the outermost side in the gate electrode, the end face of the gate insulating film is defined by the end face of the tantalum oxide layer 111. Further, in the active layer 103, a region to be a source / drain region later is exposed.
(FIG. 4 (L))

When the patterning step is completed, the porous alumina layer 211 used as a mask is heated to 45 ° C. and mixed with an aluminum mixed acid (phosphoric acid, acetic acid, nitric acid, and water by volume%).
At a ratio of 85: 5: 5: 5). Since the selectivity between the porous alumina layer 211 and the tantalum oxide layer 11 is large, the tantalum oxide layer 1
11 is not etched. This is shown in FIG.
It is clear from the EM photograph.

The SEM photograph shown in FIG. 12 is shown in FIG.
3 shows a state in which only the porous alumina layer 15 has been removed from the state shown in FIG. From this photograph, it can be confirmed that the tantalum oxide layer 11 remains in the shape of the eaves.

Next, a first impurity addition step was performed.
In this example, a plasma doping method was used. In order to manufacture an N-channel TFT (NTFT),
P (phosphorus) as an impurity ion for imparting mold conductivity
Or, select As (arsenic). Here, phosphorus was added.
First, the first time, the acceleration voltage was increased to 70 to 85 keV. At this time, since the tantalum oxide layer 111 is present on the surface of the gate insulating film 109, damage during ion implantation does not directly reach the gate insulating film, so that generation of trap levels in the gate insulating film 109 can be suppressed. .

Since the acceleration voltage is high, phosphorus ions pass through the tantalum oxide layer 111 and the gate insulating film 109,
It is added to the active layer 103. As a result, N-type impurity regions 212 and 213 are formed. Further, phosphorus ions were not added to a region of the active layer 103 where the aluminum layer 120 and the alumina layer 121 were present above.
(FIG. 4 (M))

In this step, the impurity concentration of the regions 212 and 213 will determine the resistance value of the high resistance region later. Therefore, the dose at the time of ion implantation is
It is necessary for the practitioner to set an optimum value so that 13 contains the desired concentration of impurities. In this embodiment, the impurity region 21
2, 213 phosphorus concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms /
It was set to cm ^3.

Next, a second impurity doping step was performed at an acceleration voltage as low as 5 to 10 keV. In this step, since the acceleration voltage is low, the gate insulating film 109 completely functions as a mask (the mask effect is improved as compared with the technique described in JP-A-7-135318 because the tantalum oxide layer 111 is also present). In this step, the N-type impurity regions 212 and 21
3, regions 104, 10 whose surfaces are exposed
Phosphorus ions are added to only 5. In this embodiment, 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm
Phosphorus was added at a concentration of ³ .

In the first and second impurity doping operations,
The regions 104 and 105 to which phosphorus has been added twice become a source region and a drain region, respectively. The region doped only in the first impurity doping step is the source / source region.
The high resistance regions 107 and 108 have higher resistance than the drain regions 104 and 105. Therefore, the junction between the source / drain regions 104 and 105 and the high-resistance regions 107 and 108 is connected to the gate insulating film 109 (the tantalum oxide layer 11).
1 end). In addition, the region 106 to which phosphorus is not added at all becomes an intrinsic or substantially intrinsic channel forming region which becomes a carrier movement path later.
(FIG. 4 (N))

The intrinsic region refers to a completely neutral region in which electrons and holes are perfectly balanced, and the substantially intrinsic region refers to a concentration range (1 × 10 ¹⁵ to 1 × 10 ^{15) in which} a threshold value can be controlled. 1x
10 ¹⁷ atoms / cm ³ ) indicates a region containing an impurity imparting N-type or P-type, or a region where conductivity type is offset by intentionally adding an impurity of opposite conductivity type.

Further, the high-resistance regions 107, 10
Numeral 8 has a lower phosphorus concentration than the source / drain regions 104 and 105, and corresponds to an LDD region or a low-concentration impurity region. Note that depending on the acceleration voltage in the impurity addition step and the thicknesses of the gate insulating film 109 and the tantalum oxide layer 111, phosphorus can be prevented from being added to the regions 107 and 108. In this case, the high resistance regions 107, 10
8 functions as an offset area.

When a P-channel TFT is also formed on the same substrate, the active layer of the N-channel TFT may be covered with a photoresist, and boron may be added to the remaining active layers. The concentration of boron to be added is adjusted so that the conductivity type of the source / drain regions 104 and 105 and the high-resistance regions 107 and 108 is inverted from N-type to P-type.

After the step of adding the impurity for imparting conductivity to the active layer 103 is completed as described above, next, heat treatment or excimer laser irradiation is performed in an inert gas atmosphere to add the impurity to the active layer. The activated impurities are activated. This step may be used also as the heat treatment for the subsequent silicidation.

Next, the source / drain regions 104, 10
5 is silicided. In this embodiment, a titanium silicide layer is formed. First, a titanium (Ti) film 215 was formed by a sputtering method. The film thickness is 10 to 100 nm, and the thickness is 50 nm here. In this state, the active layer 10
Reference numeral 3 denotes only the source / drain regions 104 and 105, which are in contact with the titanium film 215. Then, the titanium film 215 is heated to a temperature of 500 to 650 ° C, here 550 ° C,
The active layer 103 in contact with the titanium film 215 was reacted to be silicided. As a result, the source / drain region 1
04, 105, a titanium silicide layer 104
a and 105a are formed in a self-aligned manner. (FIG. 4
(O))

Conventionally, since the heat resistance of the aluminum material was low, the steps after forming the gate electrode
Although only a heat treatment of about 50 ° C. was performed, in this embodiment, the lower tantalum layer 111 was used as a blocking layer of the aluminum layer 120 having a low heat resistance. Heat treatment can be performed. Therefore, the salicide process using the gate electrode as a mask can form the silicide layers 104a and 105a.

In FIG. 4 (O), the silicide layer 10
4a and 105a, the source / drain region 1
Although only the surface layers 04 and 105 are silicided, the source / drain regions 104 and 105 can all be silicided depending on the thickness of the active layer 103 and the heating time. In addition, as described above, since the impurity added to the active layer can be activated by the heat treatment in the silicidation step, the activation step before the silicidation step can be omitted.

Next, the unreacted titanium film 215 in the silicidation process is removed. Here, only the titanium film 215 was selectively removed using an etchant in which a hydrogen peroxide solution and an ammonia solution were mixed. Then, an interlayer insulating film 130 is formed as shown in FIG. As the interlayer insulating film 130, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. Note that examples of the organic resin film include polyimide, polyamide, polyimide amide, and acrylic.

After forming the interlayer insulating film 130, a contact hole is formed to form the source electrode 141 and the drain electrode 1
42 is formed. In this embodiment, a laminated conductive layer made of titanium / aluminum / titanium is used as these electrode materials. Finally, hydrogenation is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to perform hydrogen termination on the entire TFT. Thus, a TFT having a structure as shown in FIG. 1 is completed.

In the TFT of this embodiment, since a tantalum layer exists between the aluminum layer that resists the gate electrode and the gate insulating film, diffusion of aluminum into the gate insulating film due to heat treatment during fabrication is prevented. it can. Therefore, the surface of the source / drain region can be silicided using the salicide process. Therefore, the gate electrode is formed of an aluminum material to reduce the resistance of the gate electrode, and the sheet resistance of the source / drain regions can be reduced, so that a TFT suitable for high-speed operation can be obtained.

Further, since a short circuit due to aluminum diffusion can be prevented, a TFT can be manufactured with a very high yield, and a high non-defective product rate can be ensured even in the manufacture of an AMLCD in which one million or more TFTs are manufactured on the same substrate. can do. Accordingly, it is possible to reduce the manufacturing cost of the liquid crystal module and a product (electronic device) equipped with the liquid crystal module. In this embodiment, an example of a TFT is shown. However, it is apparent that the gate electrode manufacturing process and the silicide process of this embodiment can be applied to a MOS transistor in which source / drain regions are formed in a silicon substrate. is there.

Embodiment 2 This embodiment will be described with reference to FIG. This embodiment is an example of an active matrix substrate which constitutes the present invention in an active matrix liquid crystal display (AMLCD). The active matrix substrate is composed of a driving circuit composed of a CMOS circuit and an NTF on the same substrate.
A pixel matrix circuit made of T is manufactured. An example of a manufacturing process and conditions of a P-channel TFT (PTFT) is briefly described below.

First, impurity ions (boron) for imparting P-type conductivity are implanted into the source and drain regions into which phosphorus ions have been implanted. 5% with hydrogen as doping gas
Use diborane diluted in water. Acceleration voltage is 60 to 90
kV and the dose amount are 1 × 10 ¹³ to 8 × 10 ¹⁹ atoms / cm ³ . The dose is adjusted so that the concentration obtained by subtracting the maximum value of the concentration of phosphorus from the maximum value of the concentration of boron implanted into the source and drain regions is 3 × 10 ^{19 to} 3 × 10 ²¹ atoms / cm ^3. This is very important. As a result, the conductivity type of the source and drain regions is inverted, so that a P-type impurity region can be formed. It should be noted that the conductivity type of the high resistance region may be reversed.

In FIG. 5, NTFT 301, PTFT
Reference numeral 302 denotes a CMOS circuit 303. As described above, if the known CMOS technology is used, it can be easily realized in substantially the same steps as in the first embodiment.

The pixel TFT (NTFT in this embodiment) 304 constituting the pixel matrix circuit can be realized by adding a few steps to the manufacturing steps described in the first embodiment.

First, according to the process of the first embodiment, the pixel TF
A plurality of T304s and CMOS circuits 303 are formed. Next, a first planarization film 310 is formed as shown in FIG.
In this embodiment, silicon nitride (50 nm) / silicon oxide (25 n
The laminated structure of m) / acryl (1 μm) is used as the first planarization film 310.

The organic resin film such as acrylic or polyimide is a solution-coated insulating film formed by spin coating, so that a thick film can be easily formed and a very flat surface can be obtained. Therefore, a film thickness of about 1 μm can be formed at a high throughput, and a good flat surface can be obtained.

Next, a black mask 311 made of a light-shielding conductive film is formed on the first flattening film 310. Prior to forming the black mask 311, the first flattening film 310 is etched to form a concave portion leaving only the lowermost silicon nitride film.

By doing so, the drain electrode of the pixel TFT 304 and the black mask 311 are close to each other via only the silicon nitride film in the portion where the concave portion is formed, and the auxiliary capacitance 312 is formed there. Since silicon nitride has a high relative dielectric constant and a small film thickness, it is easy to secure a large capacity.

After forming the auxiliary capacitance 312 at the same time as the formation of the black mask 311, the second flattening film 313 is formed of 1.5 μm thick acrylic. Although a large step is formed in the portion where the auxiliary capacitance 52 is formed, such a step can be sufficiently flattened.

Finally, a contact hole is formed in the first planarization film 310 and the second planarization film 313, and a pixel electrode 314 made of a transparent conductive film (typically, ITO) is formed. Thus, the active matrix substrate shown in FIG. 5 can be manufactured.

When a highly reflective conductive film, typically aluminum or a material containing aluminum as a main component, is used for the pixel electrode 314, an active matrix substrate for a reflective AMLCD can be manufactured.

In FIG. 5, the gate electrode of the pixel TFT has a double gate structure, but may have a single gate structure or a multi-gate structure such as a triple gate structure.

Further, the structure of the active matrix substrate is not limited to the structure of this embodiment. Since the features of the present invention reside in the configuration of the gate electrode and the silicidation of the source / drain regions, other configurations do not limit the present invention and may be determined as appropriate by the practitioner.

[Embodiment 3] This embodiment will be described with reference to FIG. This embodiment is an example in which a TFT is formed by a process different from that of the first embodiment, and is a modification of the anodic oxidation process of the first embodiment. Note that the configuration of this embodiment can be used for the configuration of another embodiment.

Here, since the steps up to the state of FIG. 3 (J) are the same as those of the first embodiment, their description is omitted. After FIG. 3J is obtained, the gate insulating film is patterned as shown in FIG. In FIG. 6A,
400 is a substrate, 401 is a base film, 403 is an active layer, 40
9a is a deposited insulating film, 409b is a thermal oxide film, 410 is a tantalum layer, 420 is an aluminum layer, and 41 is a porous alumina layer obtained by anodizing an aluminum layer. FIG.
When the state of (J) is obtained, the deposited insulating film 409a and the thermal oxide film 409b are etched using the aluminum layer 420 and the alumina layer 41 as a mask, and the gate insulating film 409 is formed.
Is patterned.

Next, an anodic oxidation treatment is performed in an ethylene glycol solution containing 3% of tartaric acid. In this treatment, both are anodized to form a thin anodic oxide layer. (FIG. 6 (B))

The tantalum layer 410 is a porous alumina layer 4
Only the part in contact with 1 is anodized and transformed into a thin tantalum oxide layer 43. The aluminum layer 420 has a thin nonporous alumina layer 42 formed on its surface (inside the porous alumina layer 41). Here, the ultimate voltage is set to about 1 to 20 V, and the nonporous alumina layer 42
Was made to have a thickness of 10 to 30 nm.

Then, the porous alumina layer 41 is selectively removed to obtain the state shown in FIG. In this state, the tantalum layer 410 is exposed.

Anodizing treatment is again performed at an ultimate voltage of 80 V in an ethylene glycol solution containing 3% tartaric acid. In this process, both the aluminum layer 420 and the tantalum layer 410 are anodized, and the thick alumina layer 42 is formed.
1. A thick tantalum oxide layer 411 is formed. The thin alumina layer 42 and the tantalum oxide layer 43 formed earlier in this process are
1. Integrated with the tantalum oxide layer 411. (FIG. 6 (D))

Unlike the step of FIG. 3 (K) in the first embodiment, in this embodiment, the tantalum layer 410 is exposed so that the tantalum layer 410 is exposed and the tantalum oxide layer 411 is easily transformed into the tantalum oxide layer 411. The thickness of the tantalum oxide layer 411 is set to be about 2 to 4 times (typically 3 times) the thickness of the tantalum layer 410. With such a structure, the tantalum layer existing above the high-resistance region later is completely transformed into the tantalum oxide layer 411, so that the TFT operates normally.

Next, impurity ions are added to the active layer 403. This step may be performed in the same manner as described in the first embodiment. As shown in FIG. 6E, a source region 404, a drain region 405, and a channel formation region 40 are formed in the active layer 403.
6, high resistance regions 407 and 408 are formed. After this, a silicidation process and the like are performed as in
T should be completed.

[Embodiment 4] This embodiment will be described with reference to FIG. In this embodiment, a method of connecting a two-layer gate electrode including a metal layer (tantalum layer 110) and an aluminum layer 120, a wiring, and another wiring in the TFT of the first embodiment will be described. The TFT shown in FIG. 7 has the same configuration as that of FIG.

In a conventional aluminum single-layer gate electrode structure, an aluminum mixed acid (phosphoric acid, acetic acid, nitric acid, and water in a volume percentage of 85: 5: 5: 5 by volume%) is used to remove the nonporous alumina layer.
(Mixed acid) and a chromic acid solution (herein referred to as chromium mixed acid). When a chromium mixed acid is used, the selectivity with respect to the silicon oxide film constituting the gate insulating film and the underlying film cannot be obtained, and the gate insulating film and the underlying film are etched. In addition, chromium mixed acid means 550 g of a chromic acid solution (a solution obtained by mixing 350 g of chromic acid and 150 g of water) with 10 · of the aluminum mixed acid.
Are mixed acids.

In this embodiment, as shown in FIG. 7, by forming tantalum having a selectivity with respect to chromium mixed acid below the gate electrode and the wiring, the tantalum layer 110 functions as an etching stopper. Lead wiring 160
An electrical connection can also be made. In FIG. 7, the lead wiring 16 is formed at the gate electrode where the gate wiring crosses the active layer.
Although the connection with 0 has been made, a contact between the gate wiring and the lead-out wiring 160 may be made in another portion.

Embodiment 5 This embodiment will be described with reference to FIG. This embodiment is a modified example of the first embodiment, and the source /
An example in which a contact pad is formed on a connection portion between a drain region and a source / drain electrode will be described.

As described in the third embodiment, the interlayer insulating film of the pixel TFT has a thickness of 800 nm to 1 nm in order to obtain a flat surface.
It is formed relatively thick, such as μm. Further, in the present invention, since the surface of the source / drain region is silicided, or the entire source / drain region is silicided, the contact with the source / drain electrode is made in contact with the thick interlayer insulating film as described above. Problems arise in forming holes.

When wet etching is performed with hydrofluoric acid to form a contact hole, the titanium silicide layer is etched. In addition, when dry etching is performed using a fluorine-based gas, a selective ratio cannot be obtained with a silicon oxide film or a silicon nitride film used for a base film or a gate insulating film. Therefore, there is a fear that the underlying film and the gate insulating film are etched.

This embodiment has solved the above-mentioned problem. Hereinafter, a process of forming a contact hole will be described with reference to FIG. First, the state shown in FIG. 4O is obtained according to the manufacturing method described in Embodiment 1. FIG. 8A is FIG.
(O), 500 is a substrate, and 501 is a base film. The active layer made of polycrystalline silicon includes a source region 504, a drain region 505, and a channel formation region 50.
6. High resistance regions 507 and 508 are formed in a self-aligned manner, and the source / drain regions 505 and 504 have silicide layers 504a and 504a by reaction with the titanium film 515.
5a are formed. Reference numeral 509 denotes a gate insulating film including a thermal oxide film and a deposited insulating film. The gate electrode has a conductive layer including a tantalum layer 110 and an aluminum layer 520, and is covered with a tantalum oxide layer 111 which is an anodic oxide of the conductive film and an alumina layer 121.

In this embodiment, the source / drain regions 50
After silicidation of the surfaces of the layers 4 and 505, an aluminum film 550 is formed to a thickness of 600 to 1000 nm by a sputtering method with the unreacted titanium film 515 remaining. (FIG. 8 (B))

Next, only the aluminum film 550 is patterned to form aluminum layers 551a forming contact pads 551 and 552 with source / drain electrodes.
552a is formed. Titanium film 515 for patterning
In order to obtain an etching selectivity with respect to the above, wet etching using an aluminum mixed acid shown in Example 1 is used. (FIG. 8 (C))

Next, the aluminum layers 551a, 552a
The titanium film 515 is patterned using the mask as a mask, and the titanium layer 551 forming the contact pads 551 and 552 is formed.
b, 552b are formed. Here, only the titanium film 515 was selectively patterned using an etchant in which a hydrogen peroxide solution and an ammonia solution were mixed. Through the above steps, the aluminum layer 551
a, 552a and titanium layers 551b, 552b are formed to form contact pads 551 and 552. (FIG. 8 (D))

Next, an interlayer insulating film 530 is formed. Here, a 900-nm-thick silicon oxide film was formed by a plasma CVD method using TEOS gas and oxygen gas as source gases. Then, contact holes for source / drain electrodes are formed in the interlayer insulating film 530. Here, wet etching with hydrofluoric acid was performed. In this embodiment, the contact pad 5 formed in the opening of the contact hole is formed.
Since 51 and 552 function as an etching stopper, the silicide layers 504a and 505a can be prevented from being etched. Then, a laminated film of titanium / aluminum / titanium is continuously formed by a sputtering method, and patterned to form a source electrode 541 and a drain electrode 542.
To form (FIG. 8 (E))

In this embodiment, the unreacted titanium film remaining in the silicide process is formed as the contact pads 551 and 552, so that the silicide layers 504a and 505a can be prevented from being etched when forming the contact holes. Also, the contact pad 55
By providing aluminum layers 551a and 552a having a lower resistance than titanium at the connection portions of the first and 552 with the source / drain electrodes, the connection resistance with the source / drain electrodes can be reduced. In this embodiment, a titanium silicide layer is formed. First, a titanium (Ti) film 215 was formed by a sputtering method. The film thickness is 10 to 100 nm, and the thickness is 50 nm here. In this state, the active layer 103 is in contact with the titanium film 215 only in the source / drain regions 104 and 105. And a temperature of 500-650 ° C., here 55
By heating to 0 ° C., the titanium film 215 and the active layer 103 in contact with the titanium film 215 were reacted to be silicided. As a result, titanium silicide layers 104a and 105a are formed on the surfaces of the source / drain regions 104 and 105 in a self-aligned manner. (FIG. 4 (O))

Embodiment 6 In Embodiments 1 to 5, in the gate electrode, the tantalum layer 111 provided below was used as a blocking layer of the aluminum layer 120 having low heat resistance. Alternatively, a silicon nitride film having a high blocking effect may be formed in the gate insulating film. In this case, since the silicon nitride film easily generates stress at the interface with the aluminum layer,
A silicon nitride oxide film is preferably formed at an interface between the gate insulating film and the aluminum layer.

In this embodiment, when the gate insulating film is formed (see FIG. 3G), the thickness of the deposited insulating film is 5 to 3 mm.
A stacked film including a silicon nitride film having a thickness of 0 nm and a silicon nitride oxide film having a thickness of 1 to 10 nm is continuously formed by a plasma CVD method, and the active layer is thermally oxidized to form a thermal oxide film on an interface with the silicon nitride film. It may be formed. Note that when the thermal oxidation step cannot be performed due to heat resistance of the substrate, a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film may be continuously formed by a plasma CVD method.

[Embodiment 7] An example in which an AMLCD is formed using an active matrix substrate (element formation side substrate) including the configuration shown in Embodiments 1 to 6 will be described. FIG. 9 shows the appearance of the AMLCD of this embodiment.

In FIG. 9A, reference numeral 801 denotes an active matrix substrate on which a pixel matrix circuit 802, a source side driving circuit 803, and a gate side driving circuit 804 are formed. It is preferable that the drive circuit be formed of a CMOS circuit in which an N-type TFT and a P-type TFT are complementarily combined. Reference numeral 805 denotes a counter substrate.

In the AMLCD shown in FIG. 9A, an active matrix substrate 801 and a counter substrate 805 are bonded together with their end faces aligned. However, only a part of the counter substrate 805 is removed, and an FPC (flexible print circuit) 806 is connected to the exposed active matrix substrate. The FPC 806 transmits an external signal to the inside of the circuit.

Further, IC chips 807 and 808 are mounted using the surface on which the FPC 806 is mounted.
These IC chips are configured by forming various circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 9A, two are attached, but one or more may be attached.

Further, a configuration as shown in FIG. 9B can be adopted.
In FIG. 9B, the same portions as those in FIG. 9A are denoted by the same reference numerals. Here, FIG. 9A illustrates an example in which signal processing performed by an IC chip is performed by a logic circuit 809 formed using TFTs over the same substrate.
In this case, the logic circuit 809 also includes the drive circuits 803 and 80
As in the case of No. 4, a CMOS circuit is basically used.

Further, the AMLCD of this embodiment is configured such that a black mask is provided on an active matrix substrate (BM0).
n TFT), but a black mask may be provided on the opposite side in addition to the TFT.

Further, color display may be performed using a color filter, or the liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like.
It is good also as composition not using a color filter.

Further, a configuration using a microlens array may be used as in the technique described in Japanese Patent Application Laid-Open No. 8-15686.

[Eighth Embodiment] The construction of the present invention is similar to that of the AMLC
In addition to D, the present invention can be applied to various other electro-optical devices and semiconductor circuits.

As an electro-optical device other than AMLCD, E
Examples include an L (electroluminescence) display device and an image sensor.

As the semiconductor circuit, an arithmetic processing circuit such as a microprocessor composed of an IC chip, a high-frequency module (MMIC) for handling input / output signals of portable equipment
Etc.).

As described above, the present invention can be applied to all semiconductor devices functioning with circuits constituted by insulated gate transistors.

Embodiment 9 The AMLCD shown in Embodiment 2
Are used as displays of various electronic devices.
Note that an electronic device described in this embodiment is defined as a product equipped with an active matrix liquid crystal display device.

Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head-mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, and the like). Is mentioned. One example of them is shown in FIG.

FIG. 10A shows a mobile phone, and the main body 30 is provided.
01, audio output unit 3002, audio input unit 3003, display device 3004, operation switch 2005, antenna 300
6. The present invention can be applied to the audio output unit 3002, the audio input unit 3003, the display device 3004, and the like.

FIG. 10B shows a video camera, which includes a main body 3101, a display device 3102, an audio input unit 3103, an operation switch 3104, a battery 3105, and an image receiving unit 31.
06. The present invention can be applied to the display device 3102, the audio input unit 3103, and the image receiving unit 3106.

FIG. 10C shows a mobile computer (mobile computer), which comprises a main body 3201, a camera section 3202, an image receiving section 3203, operation switches 3204, and a display device 3205. The present invention is applied to the image receiving section 320.
3. Applicable to the display device 3205 and the like.

FIG. 10D shows a head mounted display, which comprises a main body 3301, a display device 3302, and a band section 3303. The present invention can be applied to the display device 3302.

FIG. 10E shows a rear type projector, which includes a main body 3401, a light source 3402, a display device 3403,
Polarizing beam splitter 3404, reflector 340
5, 3406 and a screen 3407. The invention can be applied to the display device 3403.

FIG. 10F shows a front type projector, which includes a main body 3501, a light source 3502, and a display device 350.
3. It comprises an optical system 3504 and a screen 3505. The present invention can be applied to the display device 3503.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, the present invention can be used for an electronic bulletin board, a display for advertising, and the like.

[0146]

According to the present invention, even if aluminum or a material containing aluminum as a main component is used for a gate electrode in an insulated gate transistor, a short circuit between the gate electrode and the active layer due to heat treatment can be achieved. Can be prevented. Therefore, since the silicidation process can be used, the resistance of the gate electrode can be reduced and the sheet resistance of the source / drain regions can be reduced.

In addition, a highly reliable insulated gate transistor can be manufactured with a high yield, and the yield of an electro-optical device functioning as a semiconductor circuit including such a transistor and an electronic device equipped with the electro-optical device can be improved. Improvement can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional configuration diagram of a TFT according to a first embodiment.

FIG. 2 illustrates a manufacturing process of a TFT.

FIG. 3 illustrates a manufacturing process of a TFT.

FIG. 4 is a diagram showing a manufacturing process of a TFT.

FIG. 5 is a cross-sectional configuration diagram of an active matrix substrate according to a second embodiment.

FIG. 6 is a diagram showing a manufacturing process of a TFT of Example 3.

FIG. 7 is a cross-sectional configuration diagram of a TFT according to a fourth embodiment. .

FIG. 8 is a view showing a manufacturing process of a TFT of Example 5.

FIG. 9 is a diagram illustrating a configuration of an AMLCD according to a seventh embodiment.

FIG. 10 is a diagram illustrating a configuration of an electronic device according to a ninth embodiment.

FIG. 11 shows SE showing the structure near the gate electrode in Example 1.
M photograph and its schematic diagram.

FIG. 12 is a view showing S showing the structure near the gate electrode in Example 1;
EM photograph.

FIG. 13 is a cross-sectional configuration diagram of a TFT for describing a configuration of the present invention.

[Brief description of reference numerals]

 REFERENCE SIGNS LIST 100 substrate 103 active layer 104 source region 104a silicide layer 105 drain region 105a silicide layer 110 tantalum layer 111 tantalum oxide layer (anodic oxide layer) 120 aluminum layer 121 alumina layer (anodic oxide layer) 141 source electrode 142 drain electrode

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 617M

Claims (13)

[Claims] 1. A semiconductor device including a semiconductor circuit including a plurality of insulated gate transistors formed on the same substrate, wherein the insulated gate transistor has a channel formation region,
An active layer mainly containing silicon having a source region and a drain region, a gate insulating film, a gate electrode, a source electrode electrically connected to the source region, and electrically connected to the drain region. A drain electrode, wherein the gate electrode is formed in close contact with the gate insulating film, and has a melting point higher than aluminum and a metal layer mainly composed of an anodizable metal material; and a side surface of the metal layer. An anodized layer of the metal material formed on the metal layer; an aluminum layer or a material layer mainly containing aluminum formed on the metal layer; and a surface of the aluminum layer or the material layer mainly containing aluminum. And an alumina layer formed by anodizing aluminum formed on the source region and the drain region. Wherein a silicide layer is formed on the connecting portion between the drain electrode. 2. The metal layer is made of Ta, Nb, Hf, T
A semiconductor device formed of any one of metal elements i and Cr or an alloy thereof, or an alloy of Mo and Ta. 3. The silicide layer is made of Ta, Cr, M
A semiconductor device comprising a compound of silicon and any one of n, Nb, Mo, and Ti. 4. The semiconductor device according to claim 1, wherein said semiconductor layer is formed of a polycrystalline silicon thin film. 5. A semiconductor device including a semiconductor circuit including a plurality of thin film transistors formed on the same substrate, wherein the thin film transistor is mainly composed of silicon and has an active region having a channel formation region, a source region, and a drain region. A layer, a gate insulating film, a gate electrode, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. A tantalum layer formed closely on a gate insulating film; a tantalum oxide layer formed on a side surface of the tantalum layer; an aluminum layer formed on the tantalum layer or a material containing aluminum as a main component And an alumina layer formed on the surface of the aluminum layer or the material layer containing aluminum as a main component, A semiconductor device, wherein a silicide layer is formed in at least a connection part between the source region and the drain region with the source electrode and the drain electrode. 6. The semiconductor device according to claim 5, wherein said tantalum layer has a thickness of 5 to 200 nm. 7. The semiconductor device according to claim 5, wherein an end of the tantalum oxide layer protrudes outside the alumina layer. 8. The semiconductor device according to claim 5, wherein the thickness of the tantalum oxide layer is two to four times the thickness of the tantalum layer. 9. A method for manufacturing a semiconductor device including a semiconductor circuit including a plurality of thin film transistors formed on the same substrate, the method including forming an active layer and a gate insulating film closely contacting the active layer. A first step of forming a tantalum layer in close contact with the gate insulating film;
A step of forming an aluminum layer or a material layer containing aluminum as a main component in close contact with the tantalum layer; and a material containing the aluminum layer or aluminum as a main component by a first anodic oxidation treatment. A fourth step of selectively anodizing the layer to form a porous alumina layer on its side.
And anodizing the aluminum layer or the aluminum-based material layer by a second anodizing treatment,
A fifth step of forming a nonporous alumina layer on the surface and simultaneously anodizing the tantalum layer to form a tantalum oxide layer on the side thereof; and patterning the gate insulating film to form the active layer. A sixth step of exposing the surfaces of the source and drain regions, a seventh step of removing the porous alumina layer, and an eighth step of adding an impurity imparting conductivity to the source and drain regions. And a ninth step of silicidizing at least the surface of the source region and the drain region. 10. The method according to claim 9, wherein in the sixth step, the gate insulating film is patterned using the porous alumina layer as a mask. 11. The method for manufacturing a semiconductor device according to claim 9, wherein in the first anodizing treatment, a solution containing oxalic acid as a main component is used as an electrolytic solution. 12. The method for manufacturing a semiconductor device according to claim 9, wherein in the second anodizing treatment, a solution containing tartaric acid as a main component is used for an electrolytic solution. 13. A semiconductor device including a semiconductor circuit including a plurality of insulated gate transistors formed on the same substrate, wherein the insulated gate transistor has a channel formation region,
An active layer having a source region and a drain region, a gate insulating film, a gate electrode, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. The gate electrode includes an aluminum layer formed on the gate insulating film or a material layer mainly containing aluminum, and an aluminum layer formed on a surface of the aluminum layer or the material layer mainly containing aluminum. An anodized alumina layer, and the gate insulating film has a silicon nitride layer;
A semiconductor device, wherein a silicide layer is formed in at least a connection portion between the source region and the drain region with the source electrode and the drain region.