JPH11251360A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH11251360A
JPH11251360A JP5204898A JP5204898A JPH11251360A JP H11251360 A JPH11251360 A JP H11251360A JP 5204898 A JP5204898 A JP 5204898A JP 5204898 A JP5204898 A JP 5204898A JP H11251360 A JPH11251360 A JP H11251360A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
mold
semiconductor element
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP5204898A
Other languages
Japanese (ja)
Inventor
Shigeru Kataoka
茂 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5204898A priority Critical patent/JPH11251360A/en
Publication of JPH11251360A publication Critical patent/JPH11251360A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method which can facilitate the handling of a flip-chip junction and improve its quality and reliability, by improving the strength of a semiconductor element. SOLUTION: In this semiconductor device, a metallic heat radiating frame 12 is mounted on a non-electrode formation surface of a semiconductor chip 11, and a mold coated layer 13 of insulating resin is formed integrally on the electrode formation surface and the side peripheral faces of the chip 11 except for electrode terminals 11a. Pb/Sn-based solder bumps 14 are formed respectively on the respective terminals 11a by electroplating or the like with the use of the mold coated layer 13 as a mask. Such a chip 11 is arranged faced-down and jointed onto a Cu wiring layer 10 of a glass epoxy wiring board via the bumps 14. Furthermore, only the frame 12 is exposed on its one end face without being covered with the mold coated layer 13.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置および
その製造方法に係わり、特に良好な高周波特性を有する
CSP(Chip Scale pachage)タイプの半導体装置と、
そのような半導体装置を製造する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a CSP (Chip Scale Pachage) type semiconductor device having good high-frequency characteristics.
The present invention relates to a method for manufacturing such a semiconductor device.

【0002】[0002]

【従来の技術】従来から、半導体チップを基板等に直接
搭載・接続するベアチップ実装技術の一つとして、フリ
ップチップボンディングがある。フリップチップボンデ
ィングにより半導体チップが実装された半導体装置の一
例を、図7に示す。
2. Description of the Related Art Conventionally, as one of bare chip mounting techniques for directly mounting and connecting a semiconductor chip to a substrate or the like, there is flip chip bonding. FIG. 7 shows an example of a semiconductor device on which a semiconductor chip is mounted by flip chip bonding.

【0003】この半導体装置では、半導体チップ1の各
電極端子1a上に、フォトレジストのマスクを用いため
っき法などにより、それぞれはんだバンプ2が形成さ
れ、これらのはんだバンプ2が、プリント配線板等の配
線基板3の対応するCu配線層4上に当接され、加熱溶
融されて接合(フリップチップ接合)されている。ま
た、これらの接合部および半導体チップ1の外側には、
エポキシ樹脂のような絶縁性樹脂の封止層5が、ポッテ
ィング等により形成されている。なお、図中符号6は、
Cu配線層4上に積層形成されたNi−Au層、符号7
は、ソルダレジスト層をそれぞれ示している。
In this semiconductor device, solder bumps 2 are formed on each electrode terminal 1a of a semiconductor chip 1 by a plating method using a photoresist mask, and these solder bumps 2 are formed on a printed wiring board or the like. Of the wiring board 3 on the corresponding Cu wiring layer 4, and is heated and melted and bonded (flip chip bonding). In addition, these junctions and the outside of the semiconductor chip 1
A sealing layer 5 of an insulating resin such as an epoxy resin is formed by potting or the like. In addition, the code | symbol 6 in a figure is:
Ni—Au layer laminated on Cu wiring layer 4, reference numeral 7
Indicates a solder resist layer.

【0004】このように半導体チップ1がフリップチッ
プ接合された半導体装置は、ワイヤボンディングにより
実装された半導体装置と比較して、実装面積が小さい、
ボンディングワイヤを使用しないためインダクタンス成
分が少ない等の利点があり、高周波部品の高密度実装を
必要とする携帯電話のような移動体通信分野に必要不可
欠のものとなっている。
A semiconductor device in which the semiconductor chip 1 is flip-chip bonded as described above has a smaller mounting area than a semiconductor device mounted by wire bonding.
Since no bonding wire is used, there are advantages such as a small inductance component and the like, which is indispensable in a mobile communication field such as a mobile phone requiring high-density mounting of high-frequency components.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体装置においては、樹脂封止層5を形成
する最終工程まで、半導体チップ1がベアチップの状態
であるため、保管時、ダイソートテスト後のテスト時お
よび配線基板3への搭載時などに、半導体チップ1が破
損してしまうおそれがあった。特に、高周波回路に使用
されるGa−Asのような化合物半導体基板は、シリコ
ン基板と比較して機械的強度が弱い(剛性率が小さい)
ため、図8に示すように、半導体チップ1を両側から挟
持部材8により挟んで配線基板3上に搭載する際に、半
導体チップ1の側部に加わる挟持力により、クラックが
発生して破損しやすいため、高い品質並びに信頼性を維
持することが難しかった。
However, in such a conventional semiconductor device, the semiconductor chip 1 is in a bare chip state until the final step of forming the resin encapsulating layer 5, so that during storage, the die sort test is performed. There is a possibility that the semiconductor chip 1 may be damaged at the time of a later test or at the time of mounting on the wiring board 3. In particular, a compound semiconductor substrate such as Ga-As used for a high-frequency circuit has lower mechanical strength (lower rigidity) than a silicon substrate.
Therefore, as shown in FIG. 8, when the semiconductor chip 1 is mounted on the wiring board 3 by sandwiching the semiconductor chip 1 from both sides by the sandwiching members 8, cracks are generated due to the clamping force applied to the side portions of the semiconductor chip 1 and the semiconductor chip 1 is broken. Therefore, it was difficult to maintain high quality and reliability.

【0006】本発明は、これらの問題を解決するために
なされたもので、半導体素子の強度を向上させてフリッ
プチップ接合における取扱いを容易にし、品質並びに信
頼性を向上させた半導体装置と、そのような半導体装置
の製造方法を提供することを目的とする。
The present invention has been made in order to solve these problems. A semiconductor device having improved strength and improved ease of handling in flip chip bonding and improved quality and reliability has been developed. It is an object to provide a method for manufacturing such a semiconductor device.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
板状の絶縁基材の少なくとも一主面に配線層が配設され
た配線基板と、フェースダウンに配置され、電極端子上
にそれぞれ設けられたバンプを介して前記配線基板の配
線層に接合された半導体素子とを備え、前記半導体素子
の前記電極端子上を除いた電極形成面および側周面上
に、それぞれ絶縁性樹脂のモールド被覆層が形成されて
いることを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A wiring board having a wiring layer disposed on at least one main surface of a plate-shaped insulating base material, and a face-down disposed wiring board joined to the wiring layer of the wiring board via bumps provided on the electrode terminals, respectively; And a mold covering layer of an insulating resin is formed on each of the electrode forming surface and the side peripheral surface of the semiconductor device except for the electrode terminals.

【0008】また、本発明の半導体装置の製造方法は、
半導体基板上に所要の回路素子が形成された半導体素子
の電極端子上を除いた電極形成面および側周面上に、金
型を用いたモールド成形により絶縁性樹脂の被覆層を形
成するモールド工程と、前記モールド工程で形成された
樹脂被覆層をマスクとして、前記半導体素子の電極端子
上にバンプを形成する工程と、前記工程でバンプが形成
された半導体素子をフェースダウンに配置し、板状の絶
縁基材の少なくとも一主面に形成された配線層に、前記
バンプを介して接合する工程とを備えたことを特徴とす
る。
Further, a method of manufacturing a semiconductor device according to the present invention
A molding step of forming a covering layer of an insulating resin by molding using a mold on an electrode forming surface and a side peripheral surface of a semiconductor device in which a required circuit element is formed on a semiconductor substrate except for an electrode terminal. Forming a bump on the electrode terminal of the semiconductor element by using the resin coating layer formed in the molding step as a mask, and disposing the semiconductor element on which the bump is formed in the step face-down, Bonding via a bump to the wiring layer formed on at least one main surface of the insulating base material.

【0009】本発明の半導体装置およびその製造方法に
おいて、半導体素子としては、シリコン半導体素子の他
に、例えばGa−As、In−Pのような周期律表の I
II族元素とV族元素の化合物半導体の基板上に電極等の
所要の回路素子が形成された素子を使用することができ
る。このような化合物半導体素子が実装された半導体装
置は、化合物半導体の高い電子移動度により、光デバイ
スや超高速デバイスとしての使用が可能である。
In the semiconductor device and the method of manufacturing the same according to the present invention, as the semiconductor element, in addition to the silicon semiconductor element, for example, I of the periodic table such as Ga-As or In-P may be used.
An element in which required circuit elements such as electrodes are formed on a substrate of a compound semiconductor of a group II element and a group V element can be used. A semiconductor device on which such a compound semiconductor element is mounted can be used as an optical device or an ultra-high-speed device due to the high electron mobility of the compound semiconductor.

【0010】また、このような半導体素子の電極端子上
を除いた電極形成面等の上に設けられる絶縁性樹脂の被
覆封止層としては、例えばエポキシ樹脂から成る被覆層
が挙げられる。この被覆層の形成は、所定のキャビティ
形状を有する金型を用い、エポキシ樹脂をトランスファ
モールドすることにより行なうことが望ましい。
[0010] Further, as a coating sealing layer of an insulating resin provided on an electrode forming surface other than the electrode terminals of such a semiconductor element, for example, a coating layer made of an epoxy resin can be mentioned. This coating layer is preferably formed by transfer molding an epoxy resin using a mold having a predetermined cavity shape.

【0011】さらに、このように絶縁性樹脂のモールド
被覆層が形成された半導体素子の各電極端子上に設けら
れるバンプとしては、Pb/Sn系のはんだ等のバンプ
が挙げられる。バンプの形成は、電極端子上へのはんだ
の電解めっきにより行なうことが望ましく、電極端子上
を除いて半導体素子の外周に形成された樹脂モールド被
覆層をマスクとしてめっきを行なうことで、フォトレジ
スト層の形成や露光、現像、剥離という一連のフォトプ
ロセスを用いたマスキングの工程を省略することがで
き、バンプ形成工程が簡素化される。
Further, as a bump provided on each electrode terminal of the semiconductor element on which the mold covering layer of the insulating resin is formed, a bump of Pb / Sn based solder or the like can be given. The bumps are preferably formed by electrolytic plating of solder on the electrode terminals, and the photoresist layer is formed by plating using the resin mold coating layer formed on the outer periphery of the semiconductor element except on the electrode terminals as a mask. And a masking process using a series of photo processes of exposing, developing, and peeling can be omitted, and the bump forming process is simplified.

【0012】本発明において、このような半導体素子が
フリップチップ接合により実装される配線基板として
は、例えば、ガラスクロスにエポキシ樹脂のような絶縁
性樹脂を含浸させたプリプレグを1層でまたは積層して
成形したガラスクロス−樹脂含浸基板を基材とし、その
少なくとも一主面に銅箔のエッチング等により配線層が
形成されたガラス−エポキシ配線基板が使用される。こ
のような配線基板以外に、セラミック基板やガラス基板
を絶縁基材とする配線基板の使用も可能である。
In the present invention, as a wiring board on which such a semiconductor element is mounted by flip-chip bonding, for example, a prepreg obtained by impregnating an insulating resin such as an epoxy resin into a glass cloth is used as a single layer or a laminate. A glass-epoxy wiring board having a glass cloth-resin impregnated board formed as a base material and having a wiring layer formed on at least one main surface thereof by etching of a copper foil or the like is used. In addition to such a wiring board, a wiring board using a ceramic substrate or a glass substrate as an insulating base material can be used.

【0013】本発明において、金属製の放熱部材として
は、銅またはアルミニウムから成る板状部材が挙げられ
る。このような放熱部材は、一方の主面が半導体素子の
電極形成面と反対側の面(以下、非電極形成面と示
す。)に接し、かつその少なくとも一部が絶縁性樹脂の
モールド被覆層から露出するように配置されることで、
半導体素子からの熱を効率的に外部に放出し、熱抵抗を
低減させる。なお、このような板状の放熱部材として、
半導体素子の非電極形成面全体を覆う大きさの一枚の板
を使用しても良いが、幅の狭い銅板またはアルミニウム
板の複数枚を、平行に配列して使用しても良い。
In the present invention, examples of the metal heat radiating member include a plate-shaped member made of copper or aluminum. In such a heat dissipation member, one main surface is in contact with a surface (hereinafter, referred to as a non-electrode formation surface) opposite to the electrode formation surface of the semiconductor element, and at least a part thereof is a mold coating layer of an insulating resin. By being arranged to be exposed from
The heat from the semiconductor element is efficiently released to the outside, and the thermal resistance is reduced. In addition, as such a plate-shaped heat radiation member,
A single plate large enough to cover the entire non-electrode formation surface of the semiconductor element may be used, or a plurality of narrow copper plates or aluminum plates may be used in parallel.

【0014】さらに、このような金属製の放熱部材をモ
ールド被覆層の外側に長く延出させるとともに、端部を
配線基板の配線層に電気的に接続することにより、グラ
ンド層として接地を確保し、電磁波を遮蔽することがで
きる。
Further, by extending such a metal heat radiating member long outside the mold coating layer and electrically connecting its end to the wiring layer of the wiring board, grounding is secured as a ground layer. , Can shield electromagnetic waves.

【0015】本発明では、電極端子上に設けられたはん
だ等のバンプを介して、配線基板の配線層にフリップチ
ップ接合された半導体素子において、バンプ形成部であ
る電極端子上を除いた電極形成面および側周面上等に、
絶縁性樹脂のモールド被覆層が形成されているので、半
導体素子の機械的強度が向上して取扱いが容易になって
おり、配線基板への実装時などの半導体素子の破損が防
止され、信頼性の高い半導体装置が得られる。また、絶
縁性樹脂のモールド被覆層をマスクとして、効率的にバ
ンプの形成を行なうことができ、バンプ形成工程が簡素
化される。
According to the present invention, in a semiconductor device which is flip-chip bonded to a wiring layer of a wiring board via a bump made of solder or the like provided on an electrode terminal, the electrode formation except for the electrode terminal which is a bump forming portion is formed. On the surface and side peripheral surfaces, etc.
Since the mold coating layer of insulating resin is formed, the mechanical strength of the semiconductor element is improved and handling is easy, preventing damage to the semiconductor element when mounting it on a wiring board and improving reliability. Semiconductor device with high reliability can be obtained. Further, the bumps can be efficiently formed using the mold covering layer of the insulating resin as a mask, and the bump forming process is simplified.

【0016】[0016]

【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0017】図1は、本発明の半導体装置の第1の実施
例を断面的に示したものである。図において、符号9
は、ガラスクロス−エポキシ樹脂含浸基板(ガラスエポ
キシ基板)を示し、この基板の一方の主面に銅箔のエッ
チング等によりCu配線層10が設けられ、ガラスエポ
キシ配線板が構成されている。また符号11は、シリコ
ンやGaAsの半導体基板上に電極端子11a等の回路
素子が形成され、必要とされる機能単位ごとに分割され
た半導体チップを示し、この半導体チップ11の非電極
形成面上に、銅等の金属製の放熱フレーム12が取付け
られている。また、半導体チップ11の電極端子11a
上を除く電極形成面上と側周面上、および非電極形成面
側の放熱フレーム12上には、エポキシ樹脂のような絶
縁性樹脂のモールド被覆層13が一体に形成されてお
り、放熱フレーム12の一方の端面のみが、モールド被
覆層13により覆われることなく露出している。さら
に、半導体チップ11の電極端子11a上には、Cr−
Cu−Au等の中間金属層(図示を省略。)を介して、
Pb/Sn系のはんだから成るボール状のバンプ14が
設けられている。そして、このような半導体チップ11
がフェースダウンに配置され、前記したガラスエポキシ
配線板のCu配線層10(配線パッド)上に積層形成さ
れたNi−Au層15上に、はんだバンプ14を介して
接合されている。なお、図中符号16は、ガラスエポキ
シ配線板上に配線間の短絡防止とはんだバンプ14のダ
ムのために設けられたソルダレジスト層をそれぞれ示し
ている。
FIG. 1 is a sectional view showing a first embodiment of the semiconductor device of the present invention. In FIG.
Denotes a glass cloth-epoxy resin impregnated substrate (glass epoxy substrate), and a Cu wiring layer 10 is provided on one main surface of the substrate by etching of a copper foil or the like, thereby forming a glass epoxy wiring board. Reference numeral 11 denotes a semiconductor chip in which circuit elements such as electrode terminals 11a are formed on a silicon or GaAs semiconductor substrate and divided for each required functional unit. A heat radiation frame 12 made of metal such as copper is attached to the heat radiation frame 12. Also, the electrode terminals 11a of the semiconductor chip 11
A mold coating layer 13 of an insulating resin such as an epoxy resin is integrally formed on the heat-radiating frame 12 on the electrode forming surface and the side peripheral surface except for the upper side, and on the non-electrode forming surface side. 12 is exposed without being covered by the mold coating layer 13. Further, on the electrode terminals 11a of the semiconductor chip 11, Cr-
Via an intermediate metal layer such as Cu-Au (not shown),
A ball-shaped bump 14 made of Pb / Sn-based solder is provided. And such a semiconductor chip 11
Are arranged face-down, and are joined via solder bumps 14 to a Ni-Au layer 15 laminated on the Cu wiring layer 10 (wiring pad) of the glass epoxy wiring board. Reference numeral 16 in the drawing indicates a solder resist layer provided on the glass epoxy wiring board for preventing short circuit between wirings and for damping the solder bumps 14, respectively.

【0018】このような構造を有する第1の実施例の半
導体装置は、以下に示すようにして製造される。すなわ
ち、まず図2(a)に示すように、半導体チップ11の
非電極形成面を、金属製の放熱フレーム12上に、金属
共晶マウント法または接着性ペーストを用いたペースト
マウント法により接着固定する。次いで、この半導体チ
ップ11を、図2(b)に示すように、電極端子11a
部にモールド樹脂が付着しないように設計された金型1
7内に、位置合わせしてセットした後、金型キャビティ
内にエポキシ樹脂のようなモールド用絶縁性樹脂を圧入
し、モールド被覆層13を一体に成形する。なおこのと
き、後述する工程でバンプが形成される電極端子11a
部の周りにおいては、モールド被覆層13の端面がテー
パー形状を呈するように、金型17の対応する部分の形
状を整形しておくことが望ましい。
The semiconductor device of the first embodiment having such a structure is manufactured as described below. That is, first, as shown in FIG. 2A, the non-electrode forming surface of the semiconductor chip 11 is bonded and fixed to the metal heat dissipation frame 12 by a metal eutectic mounting method or a paste mounting method using an adhesive paste. I do. Next, as shown in FIG. 2B, the semiconductor chip 11 is
Mold 1 designed to prevent mold resin from adhering to the part
After the mold 7 is positioned and set, a mold insulating resin such as an epoxy resin is press-fitted into the mold cavity, and the mold coating layer 13 is integrally formed. At this time, an electrode terminal 11a on which a bump is formed in a step described later.
Around the part, it is desirable to shape the shape of the corresponding part of the mold 17 so that the end face of the mold coating layer 13 has a tapered shape.

【0019】次に、図2(c)に示すように、こうして
形成されたモールド被覆層13をマスクとして、半導体
チップ11の電極端子11a上にCr−Cu−Au等の
中間金属層を介してはんだを電解めっきした後、リフロ
ーさせることによりはんだバンプ14を形成する。ま
た、半導体チップ11の非電極形成面に固着された放熱
フレーム12のモールド被覆層13から外側に突出した
部分を、切断除去する。次いで、こうして放熱フレーム
12等が取付けられ、外周にモールド被覆層13が形成
された半導体チップ11を、図2(d)に示すように、
フェースダウンに配置してガラスエポキシ配線板上に搭
載し、はんだバンプ14をCu配線パッドのNi−Au
層15に当接させた後、はんだを加熱溶融させて、半導
体チップ11の電極端子11aとCu配線層10とを接
合する。
Next, as shown in FIG. 2C, using the mold coating layer 13 thus formed as a mask, an intermediate metal layer such as Cr-Cu-Au is formed on the electrode terminals 11a of the semiconductor chip 11. After the solder is electrolytically plated, the solder bumps 14 are formed by reflow. Further, a portion of the heat dissipation frame 12 fixed to the non-electrode forming surface of the semiconductor chip 11 and protruding outward from the mold coating layer 13 is cut and removed. Next, as shown in FIG. 2D, the semiconductor chip 11 on which the heat radiation frame 12 and the like are attached and the mold coating layer 13 is formed on the outer periphery is
It is arranged face down and mounted on a glass epoxy wiring board, and solder bumps 14 are Ni-Au of Cu wiring pads.
After being brought into contact with the layer 15, the solder is heated and melted to join the electrode terminals 11 a of the semiconductor chip 11 and the Cu wiring layer 10.

【0020】このように製造される第1の実施例の半導
体装置では、各電極端子11a上に形成されたはんだバ
ンプ14を介して、ガラスエポキシ配線板のCu配線層
10に接合された半導体チップ11において、はんだバ
ンプ14形成部を除いた電極形成面と側周面上および非
電極形成面側の放熱フレーム12上に、絶縁性樹脂のモ
ールド被覆層13が設けられているので、半導体チップ
11の機械的強度が向上し、配線板への実装時などの半
導体チップ11の破損が防止される。また、絶縁性樹脂
のモールド被覆層13をマスクとして、電解等のめっき
によりはんだバンプ14の形成を行なうことができるの
で、バンプ形成工程が簡素化され、効率的なバンプ形成
が可能である。さらに、半導体チップ11の非電極形成
面に金属製の放熱フレーム12が取着され、かつこの放
熱フレーム12の一方の端面がモールド被覆層13の外
側に露出されているので、放熱性が高められ、信頼性の
向上が達成される。
In the semiconductor device of the first embodiment manufactured as described above, the semiconductor chip bonded to the Cu wiring layer 10 of the glass epoxy wiring board via the solder bumps 14 formed on the respective electrode terminals 11a. In FIG. 11, since the mold coating layer 13 of an insulating resin is provided on the heat radiation frame 12 on the electrode forming surface and the side peripheral surface excluding the solder bump 14 forming portion and on the non-electrode forming surface side, the semiconductor chip 11 The mechanical strength of the semiconductor chip 11 is improved, and damage to the semiconductor chip 11 during mounting on a wiring board or the like is prevented. Further, since the solder bumps 14 can be formed by plating such as electrolysis using the insulating resin mold coating layer 13 as a mask, the bump forming process is simplified, and efficient bump formation is possible. Further, since a metal heat dissipation frame 12 is attached to the non-electrode formation surface of the semiconductor chip 11 and one end surface of the heat dissipation frame 12 is exposed outside the mold coating layer 13, heat dissipation is enhanced. Thus, an improvement in reliability is achieved.

【0021】次に、本発明の半導体装置の別の実施例
を、図3乃至図6に基づいてそれぞれ説明する。なお、
これらの図において、図1と同一の部分には同一の符号
を付して説明を省略する。
Next, another embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. In addition,
In these drawings, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

【0022】本発明の第2の実施例においては、図3に
示すように、金属製の放熱フレーム12の左右両側の端
面と、半導体チップ11への非取着側の主面(図では上
面)が、それぞれ絶縁性樹脂のモールド被覆層13によ
り覆われることなく、露出した構造となっており、絶縁
性樹脂のモールド工程で、図4に示すように、放熱フレ
ーム12の非取着側の主面にモールド樹脂が付着しない
ように、キャビティの形状が設計された金型17を用い
てモールド成形を行なうことにより、製造することがで
きる。
In the second embodiment of the present invention, as shown in FIG. 3, the left and right end surfaces of the metal heat radiating frame 12 and the main surface of the non-attached side to the semiconductor chip 11 (the upper surface in FIG. 3). ) Are exposed without being covered by the insulating resin mold coating layer 13, respectively. In the insulating resin molding step, as shown in FIG. It can be manufactured by performing molding using a mold 17 having a cavity shape designed so that the molding resin does not adhere to the main surface.

【0023】この実施例の半導体装置では、半導体チッ
プ11のはんだバンプ14形成部を除いた電極形成面と
側周面上に、絶縁性樹脂のモールド被覆層13が設けら
れているので、半導体チップ11の機械的強度が向上し
破損が防止されるうえに、はんだバンプ14の形成工程
が簡素化される。また、放熱フレーム12の両側の端面
だけでなく非接着側の主面が、モールド被覆層13の外
側に露出しているので、放熱性がより高められ、信頼性
が向上する。
In the semiconductor device of this embodiment, the mold covering layer 13 made of an insulating resin is provided on the electrode forming surface and the side peripheral surface of the semiconductor chip 11 excluding the solder bump 14 forming portion. In addition to improving the mechanical strength of 11 and preventing breakage, the process of forming the solder bumps 14 is simplified. Further, since not only the end surfaces on both sides of the heat dissipation frame 12 but also the main surface on the non-adhesive side are exposed outside the mold coating layer 13, the heat dissipation is further improved, and the reliability is improved.

【0024】本発明の第3の実施例においては、図5に
示すように、金属製の放熱フレーム12の左右両側の端
部が、絶縁性樹脂のモールド被覆層13の外側にそれぞ
れ延出されるとともに、延出部12aが下方に折り曲げ
られており、折り曲げられた両端部が、それぞれガラス
エポキシ配線板のCu配線層10とNi−Au層15を
介して接合されている、このような構造の第3の実施例
の半導体装置においては、半導体チップ11の非電極形
成面に接して配設された金属製の放熱フレーム12が、
モールド被覆層13の外側に延出され、かつ両側の延出
部12aの端部がそれぞれCu配線層10と電気的に接
続されているので、この放熱フレーム12をグランド層
として接地を確保することができ、電磁波を遮蔽する効
果が高い。
In the third embodiment of the present invention, as shown in FIG. 5, the left and right ends of the metal heat radiating frame 12 extend to the outside of the mold covering layer 13 made of an insulating resin. At the same time, the extending portion 12a is bent downward, and the bent both ends are respectively joined via the Cu wiring layer 10 and the Ni-Au layer 15 of the glass epoxy wiring board. In the semiconductor device according to the third embodiment, a metal heat dissipation frame 12 disposed in contact with the non-electrode forming surface of the semiconductor chip 11 includes:
Since the end portions of the extending portions 12a on both sides are extended outside the mold coating layer 13 and are electrically connected to the Cu wiring layer 10, respectively, the grounding is secured by using the heat dissipation frame 12 as a ground layer. The effect of shielding electromagnetic waves is high.

【0025】なお、このような両側に延出された放熱フ
レーム12を有する半導体装置においても、図6に示す
ように、放熱フレーム12の非接着側の主面(上面)
を、モールド被覆層13により覆うことなく露出するこ
とで、放熱性をより高め信頼性の向上を図ることが可能
である。
In the semiconductor device having the heat dissipation frame 12 extending on both sides, as shown in FIG. 6, the main surface (upper surface) of the heat dissipation frame 12 on the non-adhesive side is also provided.
Is exposed without being covered by the mold covering layer 13, it is possible to further enhance the heat dissipation and improve the reliability.

【0026】[0026]

【発明の効果】以上の説明から明らかなように、本発明
においては、配線基板の配線層にフリップチップ接合さ
れる半導体素子の、電極端子上を除いた電極形成面や側
周面上などに、絶縁性樹脂のモールド被覆層が金型を用
いたモールド成形等により形成されているので、半導体
素子の機械的強度が向上し、配線基板への実装時などの
半導体素子の破損が防止される。また、半導体素子の電
極端子上へのバンプの形成を、絶縁性樹脂のモールド被
覆層をマスクとして行なうことができるので、工程が簡
素化され、バンプ形成を効率的に行なうことができる。
As is apparent from the above description, according to the present invention, the semiconductor element to be flip-chip bonded to the wiring layer of the wiring board is formed on the electrode forming surface or the side peripheral surface excluding the electrode terminals. Since the mold coating layer of the insulating resin is formed by molding using a mold or the like, the mechanical strength of the semiconductor element is improved, and damage to the semiconductor element during mounting on a wiring board is prevented. . Further, since bumps can be formed on the electrode terminals of the semiconductor element using the mold coating layer of the insulating resin as a mask, the process can be simplified and the bumps can be formed efficiently.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の第1の実施例を示す断面
図。
FIG. 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention.

【図2】第1の実施例の半導体装置を製造するための各
工程を順に示す断面図。
FIGS. 2A and 2B are cross-sectional views sequentially showing each process for manufacturing the semiconductor device of the first embodiment.

【図3】本発明の半導体装置の第2の実施例を示す断面
図。
FIG. 3 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

【図4】第2の実施例の半導体装置を製造するための樹
脂モールド工程を示す断面図。
FIG. 4 is a sectional view showing a resin molding step for manufacturing the semiconductor device of the second embodiment.

【図5】本発明の半導体装置の第3の実施例を示す断面
図。
FIG. 5 is a sectional view showing a third embodiment of the semiconductor device of the present invention.

【図6】本発明の半導体装置の第4の実施例を示す断面
図。
FIG. 6 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention.

【図7】従来からのフリップチップ接合された半導体装
置の一例を示す断面図。
FIG. 7 is a cross-sectional view showing an example of a conventional flip-chip bonded semiconductor device.

【図8】従来の半導体装置における問題点を説明するた
めの断面図。
FIG. 8 is a cross-sectional view illustrating a problem in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

9………ガラスエポキシ基板 10………Cu配線層 11………半導体チップ 11a………電極端子 12………放熱フレーム 12a………延出部 13………絶縁性樹脂のモールド被覆層 14………はんだバンプ 16………ソルダレジスト層 17………金型 9 Glass epoxy substrate 10 Cu wiring layer 11 Semiconductor chip 11a Electrode terminal 12 Heat dissipation frame 12a Extension 13 Mold coating layer of insulating resin 14 solder bump 16 solder resist layer 17 mold

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 板状の絶縁基材の少なくとも一主面に配
線層が配設された配線基板と、フェースダウンに配置さ
れ、電極端子上にそれぞれ設けられたバンプを介して前
記配線基板の配線層に接合された半導体素子とを備え、
前記半導体素子の前記電極端子上を除いた電極形成面お
よび側周面上に、それぞれ絶縁性樹脂のモールド被覆層
が形成されていることを特徴とする半導体装置。
1. A wiring board having a wiring layer disposed on at least one main surface of a plate-shaped insulating base material, and a wiring board disposed face down and via bumps provided on electrode terminals, respectively. A semiconductor element joined to the wiring layer,
A semiconductor device, wherein a mold coating layer of an insulating resin is formed on each of an electrode forming surface and a side peripheral surface of the semiconductor element except on the electrode terminals.
【請求項2】 前記半導体素子が、 III−V族化合物半
導体の基板上に、所要の回路素子が形成されたものであ
ることを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said semiconductor element is formed by forming a required circuit element on a III-V compound semiconductor substrate.
【請求項3】 前記半導体素子の電極形成面と反対側の
面に接するように、金属製の放熱部材が設けられてお
り、かつこの放熱部材の少なくとも一部が、前記モール
ド被覆層の外側に露出されていることを特徴とする請求
項1または2記載の半導体装置。
3. A metal heat radiating member is provided so as to be in contact with the surface of the semiconductor element opposite to the electrode forming surface, and at least a part of the heat radiating member is provided outside the mold coating layer. The semiconductor device according to claim 1, wherein the semiconductor device is exposed.
【請求項4】 前記金属製の放熱部材の端部が、前記配
線基板の配線層に接続されていることを特徴とする請求
項3記載の半導体装置。
4. The semiconductor device according to claim 3, wherein an end of said metal heat radiating member is connected to a wiring layer of said wiring board.
【請求項5】 半導体基板上に所要の回路素子が形成さ
れた半導体素子の電極端子上を除いた電極形成面および
側周面上に、金型を用いたモールド成形により絶縁性樹
脂の被覆層を形成するモールド工程と、前記モールド工
程で形成された樹脂被覆層をマスクとして、前記半導体
素子の電極端子上にバンプを形成する工程と、前記工程
でバンプが形成された半導体素子をフェースダウンに配
置し、板状の絶縁基材の少なくとも一主面に形成された
配線層に、前記バンプを介して接合する工程とを備えた
ことを特徴とする半導体装置の製造方法。
5. A coating layer of an insulating resin by molding using a mold on an electrode forming surface and a side peripheral surface of a semiconductor element on which a required circuit element is formed on a semiconductor substrate except for an electrode terminal. Forming a bump on the electrode terminal of the semiconductor element using the resin coating layer formed in the molding step as a mask, and face down the semiconductor element on which the bump is formed in the step. Arranging and bonding via a bump to a wiring layer formed on at least one main surface of a plate-shaped insulating base material.
【請求項6】 前記モールド工程において、金属製の放
熱部材を、その一方の主面を前記半導体素子の電極形成
面と反対側の面に当接させ、かつ一部を金型の外側に突
出させて金型内に配置することを特徴とする請求項5記
載の半導体装置の製造方法。
6. In the molding step, a metal heat radiating member has one main surface abutted on a surface opposite to the electrode forming surface of the semiconductor element, and a part thereof projects outside the mold. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is disposed in a mold.
JP5204898A 1998-03-04 1998-03-04 Semiconductor device and manufacture thereof Abandoned JPH11251360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5204898A JPH11251360A (en) 1998-03-04 1998-03-04 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5204898A JPH11251360A (en) 1998-03-04 1998-03-04 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH11251360A true JPH11251360A (en) 1999-09-17

Family

ID=12903944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5204898A Abandoned JPH11251360A (en) 1998-03-04 1998-03-04 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH11251360A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127186A (en) * 1999-10-25 2001-05-11 Oki Electric Ind Co Ltd Ball grid array package, method of manufacturing the same, and semiconductor device
WO2003088355A1 (en) * 2002-04-17 2003-10-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
DE10214210A1 (en) * 2002-03-28 2003-11-06 Osram Opto Semiconductors Gmbh Lumineszenzdiodenchip for flip-chip mounting on a soldered carrier and method for its preparation
JP2004158825A (en) * 2003-07-17 2004-06-03 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
US7199455B2 (en) 2002-07-02 2007-04-03 Nec Electronics Corporation Molded resin semiconductor device having exposed semiconductor chip electrodes

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127186A (en) * 1999-10-25 2001-05-11 Oki Electric Ind Co Ltd Ball grid array package, method of manufacturing the same, and semiconductor device
DE10214210A1 (en) * 2002-03-28 2003-11-06 Osram Opto Semiconductors Gmbh Lumineszenzdiodenchip for flip-chip mounting on a soldered carrier and method for its preparation
US6927425B2 (en) 2002-03-28 2005-08-09 Osram Opto Semiconductors Gmbh Luminescent diode chip that is flip-chip mounted on a carrier, and method for production thereof
US7663155B2 (en) 2002-03-28 2010-02-16 Osram Opto Semiconductors Gmbh Luminescent diode chip that is flip-chip mounted on a carrier, and method for production thereof
DE10214210B4 (en) * 2002-03-28 2011-02-10 Osram Opto Semiconductors Gmbh Lumineszenzdiodenchip for flip-chip mounting on a soldered carrier and method for its preparation
WO2003088355A1 (en) * 2002-04-17 2003-10-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US7446423B2 (en) 2002-04-17 2008-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US7199455B2 (en) 2002-07-02 2007-04-03 Nec Electronics Corporation Molded resin semiconductor device having exposed semiconductor chip electrodes
US7534661B2 (en) 2002-07-02 2009-05-19 Nec Electronics Corporation Method of forming molded resin semiconductor device
JP2004158825A (en) * 2003-07-17 2004-06-03 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device

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