JPH11223839A - Projection type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the leak current and to obtain a clean picture having no cross talk by making the gate length of a first conductive type transistor to be longer than the gate length of a first transistor of a sampling means. SOLUTION: An active matrix panel 11 is provided with the pixel matrix having plural gate lines 24 and 25 and plural source lines 26 to 28, a first conductible type first transistor 29 connected to the lines 24 and 25 and the lines 26 to 28, and a source line driver circuit 12 which supplies signals to the lines 26 to 28 on a substrate. The circuit 12 is controlled by a shift register 13 and its output and plural sampling means which sample data signals and supply the sampled signals to the lines 26 to 28. Then, the gate length of a first transistor 29 is made longer than the gate length of a second transistor and the gate length of the second transistor is set longer than the gate length of a fourth transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel formed by using a thin film transistor.

[0002]

2. Description of the Related Art A conventional active matrix liquid crystal panel is described in the document "S.I.D. 83 Digest 156 page 157, B / W and Color LC Video Displays Address Bi-Polysilicon TFTs".
As shown in (Morozumi et al.), A pixel matrix using a thin film transistor is formed on a transparent substrate, and a gate line driver circuit and a source line driver circuit are MOS integrated circuits made of single crystal silicon. It was formed and externally attached to the active matrix panel as shown in FIG. In FIG. 19, reference numeral 1 denotes an active matrix panel, and the active matrix panel 1 includes a pixel matrix 2. Reference numeral 3 denotes a flexible substrate on which a driver integrated circuit 4 made of single crystal silicon is mounted. The active matrix panel 1 and the flexible substrate 3 are connected at a pad 5.
The mounting substrate 6 not only electrically connects the driver integrated circuit 4 and an external circuit, but also mechanically holds the flexible substrate 3 and the active matrix panel 1.

[0003]

The conventional active matrix panel has the following problems.

(1) Conventionally, high definition has been hindered. Conventionally, as shown in FIG. 19, a flexible substrate 3 and a source line or a gate line of the active matrix panel 1 are connected at a pad 5. In addition, the pixel pitch has been limited by the connectable pad spacing due to mounting technology.
For this reason, it has conventionally been very difficult to mass-produce an active matrix panel having a pixel pitch of 100 μm or less, and high definition has been hindered.

(2) The conventional active matrix panel as shown in FIG. 19, which hinders the miniaturization of the display device, has a reduced external dimension of the mounting substrate 6 because the driver integrated circuit is externally mounted. Pixel matrix part 2 of 4
About 5 times or more was required. For this reason, the size of the display device using the conventional active matrix panel is inevitably large compared to the area of the pixel matrix portion contributing to the display. This has been a factor limiting the application to ultra-small monitors such as viewfinders.

(3) Manufacturing costs are high When manufacturing a display device, the active matrix panel 1
Connecting the driver integrated circuit 4 to the flexible substrate 3, connecting the driver integrated circuit 4 to the flexible substrate 3,
A step of mounting the flexible substrate 3 and the mounting substrate 6 is required, and the manufacturing cost must be increased.

(4) Poor reliability The active matrix panel 1 and the flexible substrate 3 are connected to each other, and the driver integrated circuit 4 and the flexible substrate 3 are connected to a large number of connection points. In addition, the connection strength at the connection point was not sufficient, and the reliability of the entire display device was low. Or, a great deal of expense was required to ensure sufficient reliability.

An object of the present invention is to solve the above problems and to provide an inexpensive active matrix panel with high definition, compactness and excellent reliability. Also,
The active matrix panel of the present invention is intended to be applied to an electronic viewfinder of a video camera, a monitor of a portable VTR, and the like. Further, it is intended to be used as a light valve of a projection display device.

[0009]

In order to solve the above problems, the present invention provides the following means.

A first transparent substrate on which a pixel matrix having a plurality of gate lines, a plurality of source lines and a thin film transistor is formed, a second transparent substrate opposed to the first transparent substrate, and An active matrix panel comprising liquid crystal interposed between first and second transparent substrates, wherein a gate line driver circuit comprising a complementary thin film transistor comprising a silicon thin film and a silicon thin film are provided on the first transparent substrate. The pixel matrix includes at least one of a source line driver circuit composed of a complementary thin film transistor, and the thin film transistor constituting the pixel matrix is a P-type transistor constituting the gate line driver circuit or the source line driver circuit.
The present invention provides an active mat tas panel characterized in that it has the same cross-sectional structure as one of a type thin film transistor and an N type thin film transistor.

An active matrix panel wherein the gate line driver circuit and the source line driver circuit include a static shift register having a complementary MOS structure.

The gate line driver circuit and the source line driver circuit are composed of P-type and N-type thin film transistors. The P-type thin film transistor includes acceptor impurities in a source region and a drain region. An active matrix panel characterized in that a source region and a drain region contain an acceptor impurity and a donor impurity having a higher concentration than the acceptor impurity.

The gate line driver circuit and the source line driver circuit are composed of P-type and N-type thin film transistors. The P-type thin film transistor includes acceptor impurities in a source region and a drain region. An active matrix panel is characterized in that a source region and a drain region contain an acceptor impurity and a donor impurity having a higher concentration than the acceptor impurity.

The gate line driver circuit and the source line driver circuit include P-type and N-type thin film transistors. The N-type thin film transistor includes donor impurities in a source region and a drain region, and the P-type thin film transistor includes a source region and a source region. An active matrix panel characterized in that a drain region contains a donor impurity and an acceptor impurity having a higher concentration than the donor impurity.

The gate lengths of the P-type and N-type thin film transistors constituting the gate line driver circuit and the source line driver circuit are formed to be shorter than the gate lengths of the thin film transistors constituting the pixel matrix. An active matrix panel is provided.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The figure shows a complementary metal oxide semiconductor structure (Compleme
ntary Metal oxide Semiconductor; hereinafter abbreviated as CMOS structure. 2) is a block diagram showing the structure of an active matrix panel 11 in which a source line driver circuit 12, a gate line driver circuit 21, and a pixel matrix 22 are formed on the same transparent substrate. The source line driver circuit 12 includes a shift register 13 and sample-and-hold circuits 17, 18, and 1 each including a thin film transistor (hereinafter abbreviated as TFT).
9 and video signal buses 14, 15 and 16, and the gate line driver circuit 21 includes a shift register 20 and a buffer 23 as necessary. The pixel matrix 22 includes a plurality of source lines 26, 27, 28 connected to the source line driver circuit 12, a plurality of gate lines 24, 25 connected to the gate line driver circuit 21, and a source line. And a plurality of pixels 32 formed at the intersection of the gate line
33. The pixel includes a TFT 29 and a liquid crystal cell 30. The liquid crystal cell 30 includes a pixel electrode, a counter electrode 31, and liquid crystal. Note that the shift registers 13 and 20 are other circuits having a function of sequentially selecting a source line and a gate line,
For example, a counter and a decoder may be substituted. Input terminals 34, 35, 3 of the source line driver circuit
6, a clock signal CLX, a start signal DX, and video signals V ₁ , V ₂ , V ₃ are respectively input to the input terminals 37, 38 of the gate line driver circuit. The set signal DY is input.

The shift register 13 and the shift register 20 shown in FIG. 1 are complementary T-type TFTs composed of a P-type TFT and an N-type TFT.
It may be configured as a static or dynamic circuit using FT, or a dynamic or static circuit using unipolar TFT. Of these, TFT
Considering the device performance, a static circuit using complementary TFTs is optimal. The reason is explained as follows. In general, a TFT used in an active matrix panel is formed of a polycrystalline or amorphous silicon thin film on an insulating substrate, so that a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET) made of single crystal silicon.
Abbreviated. ), Its on-current is small and its off-current is large. The reason is that the trap density existing in the silicon thin film is much higher than that in the single crystal silicon, so that the carrier mobility becomes small, and the recombination of carriers frequently occurs in the reverse-biased PN junction. by. In view of the characteristics of such a TFT device, the present invention provides a complementary TFT for the following reasons.
Employs a static shift register.

(1) Since a TFT has a large off-state current, T
The dynamic circuit constituted by the FT has a narrow operating voltage range, operating frequency range, and operating temperature range.

(2) In order to make use of the low power consumption of the active matrix type liquid crystal panel, the driver circuit needs to be formed with a low power consumption CMOS structure.

(3) The required on-current value is smaller than that of the unipolar MOS dynamic shift register.

FIG. 2A shows the shift register 13 shown in FIG.
20 and 20 show circuit configuration examples. In FIG. 2A, inverters 41 and 42 are P-type TFs as shown in FIG.
It is composed of T47 and N-type TFT. The clocked inverters 43 and 46 are composed of P-type TFTs 49 and 50 and N-type TPTs 51 and 52, as shown in FIG.
The clock signal CL is applied to the gate of the N-type TFT 52 and the P-type T
The inverted clock signal CL # is input to the gate of the FT 49. Similarly, clocked inverters 44 and 45
Type TFTs 53 and 54 and N-type TFTs 55 and 56, and a gate of the N-type TFT 56 is supplied with an inverted clock signal CL #.
However, the clock signal CL is input to the gate of the P-type TPT 53. In FIG. 2A, the clocked inverter 4
A circuit composed of an inverter 57 shown in FIG. 2E and an analog switch composed of an N-type TFT 58 and a P-type TFT 59 is used in place of 3 and 46, and FIG. ), An analog switch composed of an N-type TFT 61 and a P-type TFT 62 may be used.

As described above, it is very useful to form the driver circuit in the active matrix panel with a TFT having a CMOS structure. However, complementary TFTs obtained by simply applying the prior art to TFTs
Integrated circuits have the following disadvantages.

(1) The manufacturing method for integrating both the P-type TFT and the N-type TFT on the same substrate is complicated, and the manufacturing cost is increased.

(2) P-type TFT and N-type TFT having uniform characteristics, which are important elements for forming a complementary TFT integrated circuit.
It is difficult to form FT.

(3) The P-type TFT and the N-type TFT do not have sufficient driving capability to realize a driver circuit.

The present invention overcomes the above-mentioned problems by modifying the manufacturing method, device structure, device dimensions, materials, and the like. Hereinafter, they will be described step by step.

FIG. 3A shows an example of a sectional structure of a complementary TFT constituting the source line driver circuit 12 and the gate line driver circuit 21 of FIG. 1, and FIG. 3B shows the pixel matrix of FIG. 2 shows an example of a cross-sectional structure of a TFT and a pixel constituting the pixel 22. In FIG. 3A, reference numeral 71 denotes an insulating substrate such as a glass or quartz substrate, on which a P-type TFT 99 and an N-type TFT 100 are formed. 73, 76 are silicon thin films serving as channel regions, 72, 74, 75, 77
Is a silicon thin film serving as a source region or a drain region, and 72 and 74 are P-type doped with impurities.
5, 77 are N-type doped with impurities. 78, 79
Is a gate insulating film of SiO ₂ , silicon nitride or the like; 80 and 81 are gate electrodes of polycrystalline silicon, metal, metal silicide, etc .; 82 is an interlayer insulating film of SiO ₂ or the like; 83 is a wiring layer of metal or the like. , 84 denotes an insulating film formed by SiO ₂ or the like, 85 a passivation film. On the other hand, in FIG. 3B showing the cross-sectional structure of the pixel matrix,
Reference numeral 86 denotes the same insulating substrate as 71 in FIG. 9A, on which the pixel TFT 101 and ITO (isodium tin
And a pixel electrode 94 made of a transparent conductive film such as oxide. Reference numerals 87, 88, and 89 indicate 7 in FIG.
2, 73, 74, 75, 76, and 77 are formed of the same silicon thin film layer, 88 is a channel region, and 87 and 89 are source or drain regions. Area 87
And 89 are P-type or N-type doped with impurities,
The configuration of the impurities contained in those regions is determined by regions 72 and 7
4 or the configuration of the impurities contained in the regions 75 and 77. 90 is a gate insulating film made of the same layer as 78 and 79; 91 is a gate electrode made of the same layer as 80 and 81; 92 is an interlayer insulating film made of the same layer as 82; Reference numeral 95 denotes an insulating film made of the same layer as 84; 96, a liquid crystal; 97, a counter electrode including a transparent conductive film layer; and 98, a transparent substrate. Here, the TFTs 99 and 100 and the pixel TFT 10 forming the driver circuit
Reference numeral 1 indicates that the source / drain region, the channel region, the gate insulating film, the gate electrode, and the interlayer insulating film are each formed of the same thin film layer. The connection between the TFTs in one source line driver circuit and the gate line driver circuit is made via a wiring layer 83 having a low sheet resistance made of metal such as aluminum, and the source line in the pixel matrix is connected to 83. The pixel electrode 94 is formed of a transparent conductive film layer such as ITO, and is formed of the wiring layer 93 formed of the same layer. In the case where the wiring layer (93) is formed of aluminum or aluminum silicide and the transparent conductive film layer (94) is formed of ITO, if the structure is such that no interlayer insulating film is provided between the two layers, the same process is performed. The opened through-holes (102, 103) are respectively formed in two different layers (93,
94) and the silicon thin film layers (87, 89) can be used, thereby simplifying the manufacturing process. Here, aluminum and ITO are processed by different etchants, and ITO is formed in a process before aluminum to form a pattern by utilizing the property that ITO is not immersed in the aluminum etchant. FIG.
In (b), the insulating film 95 is a capacitor for preventing a DC voltage from being applied to the liquid crystal 96, and its capacitance value must be sufficiently larger than the value of the pixel capacitance. The thickness must be less than a certain value (for example, about 3000 Å). On the other hand, in order to ensure moisture resistance, it is necessary to cover the driver circuit portion with a passivation film 85 having a thickness equal to or more than a certain value (for example, about 1 μm) as shown in FIG. It is most effective to form the passivation film 85 by forming a film over the entire surface of the active matrix substrate and then removing it while leaving the driver portion.
Is made of a material processed with an etchant that does not immerse the insulating films 84 and 95, for example, polyimide.

The structure of the manufacturing method of the present invention and the complementary TFT obtained by the method will be described below. According to the conventional method of manufacturing a CMOS integrated circuit using single crystal silicon, at least four photo steps (low concentration P well forming step, P type Upper layer forming step, P-type MOSFET source / drain forming step, N-type MOS
An FET source / drain formation step) is additionally required. On the other hand, according to the present invention, a complementary TFT integrated circuit can be realized by adding at least one photo process as compared with the manufacturing process of the unipolar TFT integrated circuit.

FIGS. 4A to 4D show an example of a main part of a manufacturing process of the active matrix panel of the present invention.
First, as shown in FIG. 4A, a silicon thin film is deposited on a transparent insulating substrate 110, and then a desired pattern is formed.
A channel region 111 of the P-type TFT and channel regions 112 and 113 of the N-type TFT are formed. Thereafter, the gate insulating films 114, 115, 1 are formed by using a thermal oxidation method or a vapor growth method.
16, and further, gate electrodes 117, 118, 119
To form Next, as shown in FIG. 4B, an acceptor impurity 120 such as boron is implanted over the entire surface by ion implantation. The implanted acceptor impurities are activated by a later heat treatment and become an acceptor to form a P-type semiconductor. Thereby, the source / drain region 1 of the P-type TFT is
21 and 122 are formed. At this time, the regions 123, 124, 12 to be the source / drain regions of the N-type TFT
Acceptors 5 and 126 are also added. Next, FIG.
As shown in (C), a P-type TFT is formed by, for example, photoresist 12
8, and a donor impurity 127 such as phosphorus or arsenic is implanted at a higher concentration than the acceptor impurity 120. The implanted donor impurities are activated by a later heat treatment to become donors. If the dose of the ion-implanted acceptor impurity is 1 × 10 ¹⁵ cm
^-2 , the dose amount of the donor impurity is 3 × 10 ¹⁵ cm ⁻²
Then, the regions 123, 124, 125, and 126 are almost equivalent to including only the donor corresponding to the dose of 2 × 10 ¹⁵ cm ⁻² . With the above, the source of the N-type TFT
Drain regions 123, 124, 125, 126 are formed.

Next, as shown in FIG.
After removing 28, an interlayer insulating film 129 is deposited, a through hole is opened, a pixel electrode 131 made of a transparent conductive film is formed, and a wiring 130 made of metal or the like is formed. As described above, the P-type TFT 132 and the N-type TFT 13
3. N-type TFT 1 that constitutes the pixel TFT in the pixel matrix section
34 is completed. Incidentally, it is of course possible to form the TFT in the pixel matrix portion into a P-type. In the TFT thus obtained, a P-type TFT contains an acceptor impurity in a source / drain region, and an N-type TFT has a source / drain region.
The drain region contains an acceptor impurity and a donor impurity having a higher concentration than the acceptor impurity.

In the above manufacturing process, the acceptor impurity 120 shown in FIG. 4B is used as the donor impurity 120 and the donor impurity 127 shown in FIG.
(D) in FIG.
32 and P-type TFTs 133 and 134 are obtained. The N-type TFT thus obtained contains a donor impurity in the source / drain region, and the P-type TFT contains a donor impurity in the source / drain region and an accessor impurity having a higher concentration than the donor impurity.

According to the above-described manufacturing method, the complementary TFT integration is performed by adding only one hot step required for forming the mask pattern 128 shown in FIG. A circuit is formed. This makes it possible to realize an active matrix panel with a built-in driver circuit. From an economic point of view, the above-described manufacturing method is of course the best, but a method of forming a mask pattern in each step of ion-implanting acceptor impurities and donor impurities may be employed. Further, the complementary TF manufactured by the method described above
In a T integrated circuit, each TFT is isolated in an island shape on an insulating substrate, and does not require a special element isolation step. Further, unlike an integrated circuit made of single crystal silicon, no parasitic MOSFET is generated, and there is no need to form a channel stopper.

Next, means for realizing a P-type TFT and an N-type TFT having uniform characteristics required for forming a complementary integrated circuit will be described. Conventionally, TFTs using II-VI compound semiconductors have been known for a long time. However, there are the following two reasons: (1) It is practically impossible to control and realize both P-type and N-type conductivity types in a compound semiconductor.

(2) It is extremely difficult to control the interface between the compound semiconductor and the insulating film, and a MOS structure has not been realized.

Thus, the complementary T
FT cannot be realized. Therefore, in the present invention, the source / drain region and the channel region are formed of a silicon thin film. Table 1 shows the carrier mobilities of the amorphous silicon thin film and the polycrystalline silicon thin film among the silicon thin films by conduction type.

As shown in the table, when a TFT is constructed, a P-type, N-type
Since it is easy to make the characteristics uniform in both molds and the current supply capability of the TFT can be increased, it can be said that a polycrystalline silicon thin film is optimal for realizing a complementary TFT integrated circuit.

[0038]

[Table 1]

Next, the means employed by the present invention to increase the current supply capability of TFTs, especially P-type and N-type TFTs constituting a driver circuit, will be described. As described above, a TFT made of a non-single-crystal silicon thin film has a high trap density, and thus has a characteristic of a smaller on-current and a larger off-current than a single-crystal silicon MOSFET. FIG.
The gate length, gate width, and source / drain voltage V
Single crystal silicon MOSFET measured with the same _DS
Characteristics 140 and TFT characteristics 141 using a silicon thin film
Are shown in comparison. In the figure, the horizontal axis represents the gate voltage V _GS with respect to the source, and the vertical axis represents the source-drain current I.
It is a relative value of _DS . As can be seen from the figure, since the TFT has a low on / off ratio, the TFT for pixel matrix shown in FIG.
TF constituting FT 29 and driver circuits 12 and 21
Each of the T must be formed to an optimum element size. For example, when an intention is to display an NTSC signal, the pixel matrix TFT must satisfy the following expression within the operating temperature range.

[0040]

(Equation 1)

Here, C ₁ is the total pixel capacity of one pixel, R
_{ON1, R OFF1} on-resistance of each TFT, is off resistance. Equation (1) is a holding condition for an arbitrary pixel. If this condition is satisfied, 90% or more of the written charge is held over one field.

Equation (2) is a writing condition for an arbitrary pixel. If this condition is satisfied, 99% or more of a desired display signal is written to the pixel. On the other hand, the TFT constituting one driver circuit must satisfy the following expression within the operating temperature range.

[0043]

(Equation 2)

Here, C ₂ and C ₃ are respectively shown in FIG.
, The capacity to be added to the nodes 142 and 143,
R _ON2 and R _ON3 are the output resistances of the clocked inverter 43 and the inverter 41, f is the clock frequency of the shift register, and k is a constant. (The value of k is empirically about 1.0 to 2.0.) According to the applicant's actual measurement and simulation, for example, the clock frequency f = 2
To achieve the shift Bok register about MH _Z is, _{R ON2} and _{R ON3} of TFT forming the driver circuit must be lessヽ, the _{R ON1} pixel TFT.
In order to realize such a low output resistance, the present invention forms the gate length of the TFT constituting the driver circuit as short as possible within the limit allowed by the withstand voltage. Further, TFTs forming the sample and hold circuits 17, 18, and 19 in FIG.
In this case, the gate length may be shorter than that of the TFT forming the shift register 13 since the withstand voltage may be lower than that of the TFT forming the shift register 13. FIG. 6 shows the definition of the gate length L, and Table 2 shows an example of the gate length of each of the TFTs employed in the present invention. In FIG. 6, 142 is a gate electrode,
143 is a silicon thin film forming a channel region,
144 indicates the gate length and 145 indicates the gate width.

[0045]

[Table 2]

In order to increase the current supply capability of the P-type TFT and the N-type TFT, the TFT is formed such that the thickness of the silicon thin film forming the channel region becomes smaller than the maximum value of the width of the depletion layer which can spread on the surface of the silicon thin film. It is more effective to use the means of configuring. Maximum value of depletion layer width X _{P max} in P-type TFT using silicon thin film, N-type T
The maximum value X _{N max} of the depletion layer width in FT is given by the following equations.

[0047]

(Equation 3)

Here, q is the unit charge, ε is the dielectric constant of the silicon thin film, φ _fp and φ _fn are P-type and N-type TF, respectively.
T Fermi energy, N _D, N _A is equivalent donor density in the channel region, respectively, is an acceptor density. The equivalent donor density and acceptor density are
It is determined from the density of donor and acceptor impurities present in the region and the trap density acting as donor and acceptor. In the present invention, it constitutes less than either of the values of P-type and the thickness of the silicon thin film of the channel region in the N-type TFT _{X Pmax} and _{X N max.} FIG. 7 shows a cross-sectional structure of a TFT in which a depletion layer is formed. In the figure, 146 is an insulating substrate, 147 is a silicon thin film forming a channel region, 148 and 149 are silicon thin films forming source / drain regions, 150 is a gate insulating film, 1
Reference numeral 51 denotes a gate electrode, and t _si and X indicate the thickness of the silicon thin film and the width of the depletion layer formed on the surface of the silicon thin film, respectively.

Each of the means described above, that is, (1) The circuit type of the driver circuit is a static type using complementary TFTs.

(2) To devise a manufacturing method and a structure of a complementary TFT integrated circuit.

(3) To make the characteristics of the P-type and N-type TFT uniform.

(4) To enhance the load driving capability of the TFT.

As a result, a basic technique for incorporating a driver circuit in an active matrix panel is established.

Next, some means for making the present invention more effective will be described based on the basic technology described above.

First, a description will be given of a device for pattern layout in an active matrix panel used in the present invention. FIG. 8 is a plan view of the active matrix panel for explaining the layout of each functional block. Looking at the active matrix panel 160 so that an image is formed as a normal image, the source line driver circuit 161 (16
2) is formed, and a shift register 163, a buffer 164, a video signal bus 165, and a sample-and-hold circuit 166 are sequentially arranged from the periphery to the center in the source line driver circuit. A gate line driver circuit 167 (170) is formed in the left and / or right peripheral portion, and a shift register 168 and a buffer 169 are arranged in this gate line driver in order from the periphery to the center. I do. A pixel matrix 171 is formed at the center of the active matrix panel 160 so as to be in contact with the source line driver circuit 161 (162) and the gate line driver circuit 167 (170).
2, 173, 174, and 175 are arranged. Signal transmission is performed in the directions of arrows 176-180. By laying out each functional block as described above, it is possible to use the limited space most effectively.

In the source line driver circuit and / or the gate line driver circuit, a unit cell of the driver circuit is formed within a limited pitch equal to (or twice as large as) the pixel pitch. To
A pattern layout as shown in FIG. 9 is used. In FIG. 9, reference numerals 181 to 183 denote one pixel (or two pixels).
And the length is D. By employing the layout as shown in FIG. 8 and repeatedly arranging the cells of the driver circuit with D as a cycle, more effective use of space becomes possible. FIG. 9 shows an example of a pattern layout of some thin film layers constituting a driver circuit. In the same drawing, 184 and 185 are wirings for positive power supply and wiring for negative power supply, respectively, and 186 to 191 are silicon thin films forming source / drain and channel portions of P-type TFT.
Reference numerals 92 to 195 denote silicon thin films forming source / drain and channel portions of the N-type TFT, and unit cells of a driver circuit are formed in regions 196, 197, and 198 surrounded by broken lines. Since the element isolation of each TFT is performed by etching the silicon thin film into islands irrespective of the same polarity or different polarity, for example, the island 192 of the N-type TFT silicon thin film and the P-type TFT silicon thin film Island 187
And two islands 1 of silicon thin film for P-type TFT
It is possible to make the distance b between 87 and 188 substantially equal. The present invention positively utilizes this property to provide P-type TF
By arranging T islands and N-type TFT islands differently, the degree of integration in the direction in which unit cells are repeated is increased.

In the present invention, in order to further increase the degree of integration, the following means are used in combination. FIGS. 10A and 10B show an example in which an inverter using a complementary TFT is formed between a positive power supply wiring 199 and a negative power supply wiring 200. In the figure, reference numerals 201 and 202 denote through holes for forming contacts in a source portion, and reference numeral 203 denotes a gate electrode. First, FIG.
As in 0 (a), a P-type region 204 and an N-type region 205 are provided on one silicon thin film island with the boundary 208.
Next, as shown in FIG. 10B, a contact of the drain portion is formed by the through hole 206, and the output of the inverter is extracted by the wiring 207.

The second method for making the present invention more effective is
The present invention relates to reduction of clock noise in a source line driver circuit. As shown in FIG. 1, the source line driver circuit 12 includes video signal buses 14 to 16 and at least a pair of dual clocks CL for driving the shift register 13 and CL which is an inverted signal of the clocks CL.
B for transmitting B. Here, if there is a difference between the stray capacitance formed between a certain video signal bus and the CL wiring and the stray capacitance formed between the video signal bus and the CLB wiring, the video signal is As a result of superimposition of spike noise synchronized with the clock signal, line-shaped display unevenness occurs on the screen of the active matrix panel.

According to the present invention, as shown in FIG.
The above-described clock noise is reduced by twisting the wiring for CLB and the wiring for CLB. FIG. 11A shows a source line driver circuit, wherein 210 to 213 are unit cells of a shift register, 214 and 215 are sample and hold circuits, 216 is a pixel matrix, and 217 is a video signal bus. Reference numerals 218 and 219 denote a CL wiring and a CLB wiring, respectively, which are twisted substantially at the center of the wiring. By doing so, the average distance between the CL wiring and the video signal bus becomes substantially equal to the average distance between the CLB wiring and the video signal bus. a stray capacitance _(C S1 ₊ C _S3),浮避capacitance _(C S2 ₊ C _S4) to be added to the question of the wiring and the video signal bus for CLB and are substantially equal. As shown in FIG. 11B, the rising timing of one of CL and CLB substantially coincides with the falling timing of the other. As a result, clock noise superimposed on the video signal is greatly reduced, and a clear display is obtained on the screen. Note that CL and C
The number of twists with the LB may be plural.

The third method for making the present invention more effective is
The present invention relates to the equalization of a resistor added in series to a sample and hold circuit. FIG. 12 shows a part of FIG.

In FIG. 12, 230 is a shift register included in the source line driver circuit, 231 to 233 are video signal buses, 234 to 236 are sample and hold circuits, and 240 is a pixel matrix. Image signals corresponding to, for example, the three primary colors red (R), green (G), and blue (B) are transmitted to the three video signal buses 231 to 233, and the combination thereof is changed every horizontal scanning. Since a low resistance is required for the three video signal buses, a metal layer such as aluminum is used as a wiring material. On the other hand, when the structure shown in FIGS. 3A and 3B, which is considered to be most effective from an economic point of view, is adopted, the material of the wirings 237 to 239 from the video signal bus to the sample and hold circuit includes The same material as described above, for example, a polycrystalline silicon thin film or the like is used. In this case, since the sheet resistance of the polycrystalline silicon thin film is considerably higher than that of the metal layer, and the lengths of the wirings 237, 238, and 239 are not equal if they are simply connected in a straight line, the wiring 237 239 are not equal, and this difference in wiring resistance causes line-shaped display unevenness. Therefore, the present invention provides the wiring 237,
The wiring pattern is devised so that the resistances of 238 and 239 are all equal. Specifically, the wiring width W is made constant and the wiring length L is made equal, or each of the wirings 237 to 239 is changed.

The fourth measure for making the present invention more effective is:
The present invention relates to a driving method for compensating for a low operation speed of a driver circuit using a TFT. As shown in FIG.
Is inferior to that of a single-crystal silicon MOSFET, so that the operation speed of the shift register using the TFT is not sufficient to drive the active matrix panel. In order to compensate for this slow operation speed, the present invention uses FIG.
The circuit structure illustrated in (a) and the driving method illustrated in FIG. In FIG. 13A, reference numeral 250 denotes a first shift register included in the source line driver circuit, which receives a start signal DX and clocks CLx1 and CLx1B and outputs output signals 252, 254,. I do. Reference numeral 251 denotes a second shift register included in the source line driving circuit, which includes a start signal DX and a clock C.
Lx2 and CLx2B are provided, and output signals 253, 25
5, etc. are output. Reference numeral 265 denotes a video signal bus to which a video signal V is supplied, 256 to 259 denote sample and hold circuits, 261 to 264 denote source lines, and 260 denotes a pixel matrix. Signals V, DX, CLx1, CLx1B, CLx2, CLx2B input to one source line driver circuit and signal 2 output from shift registers 250 and 251
52 to 255 are shown in FIG. The source line driver circuit shown in FIG.
0, 251 and shift registers 250, 2
51 is a clock CLx1 having a phase difference of about 90 °
(CLx1B) and CLx2 (CLx2B). When the source line driver circuit includes N series shift registers, each shift register is driven by N clocks whose phases are shifted by approximately 180 ° / N and their inverted clocks. Assuming that the frequencies of CLx1 and CLx2 are f, the output signals 252 to 255 are sequentially output at a time interval of ｆf,
The video signal V is sampled at each of the edges 266 to 269 and held on the source lines 261 to 264.
As a result, sampling at a frequency of 4f can be realized using a shift register driven by a clock of a frequency f, which is an effective means for compensating for the slow operation speed of the shift register by the TFT. When the source line driver circuit includes an N-series shift register, a shift register driven by a clock of frequency f is used.
It is possible to realize sampling at a frequency of 2Nf.

The fifth measure for making the present invention more effective is:
Test means is provided for each output of the source line and gate line driver circuits. FIG. 14 shows a specific example. In the figure, 280 is a shift register included in one circuit of the source line driver, 281 is a video signal bus terminal, 282
Is a sample hold circuit, 283 is a source line driver test circuit, 284 and 285 are test circuits 28, respectively.
A control terminal 3 and a test signal output terminal 286 are source lines. A test circuit such as 283 is added to all source lines. 287 is a shift register included in the gate line driver circuit, 288 is a gate line driver test circuit, 289 and 290 are test signal input terminals and test signal output terminals, 291 is a gate line, 292
Is the pixel matrix. A test circuit like 288 is added to all gate lines. The test circuit operates as follows. During the test operation of the source line driver circuit, the test circuit 283 is turned on under the control of the terminal 284. In this state, after inputting a predetermined test signal to the video signal bus terminal 281, the shift register 28
Scan 0. At this time, if a signal within the standard is output in time series to the test output terminal 285, the source line driver circuit is determined to be “good”, otherwise, it is determined to be “bad”. Terminal 2 when testing the gate line driver circuit
The shift register 287 is scanned while a predetermined test signal is input to 89. At this time, the test output terminal 290
If the signal within the standard is output in time series, the gate line driver circuit is determined to be “good”, otherwise, it is determined to be “bad”. In this manner, the inspection of the active matrix panel, which was conventionally performed visually after displaying the test pattern, can be performed electrically and automatically.

The sixth measure for making the present invention more effective is:
This is to create a storage capacitor in a pixel without adding a manufacturing process. FIGS. 15A and 15B show specific examples of the pixel structure of the present invention. FIG. 1A shows an equivalent circuit, and FIG. 1B shows a cross-sectional structure.

In FIG. 9A, reference numerals 300 and 301 denote a source line and a gate line, respectively, 302 denotes a pixel TFT, and 30 denotes a pixel TFT.
Reference numeral 3 denotes a liquid crystal cell; 304, a counter electrode terminal; 305, a metal oxide semiconductor capacitor (hereinafter abbreviated as MOS capacitor), which is a feature of the present invention; and 306, the MO.
This is the gate electrode of the S-cabacitor 305. In FIG. 2B, reference numerals 310 and 324 denote transparent insulating substrates,
311 to 315 are silicon thin film layers, 316 and 317 are gate insulating films, 318 and 319 are gate electrodes, 320 is an interlayer insulating film, 321 is a wiring layer forming a source line, and 322 is a transparent conductive layer forming a pixel electrode. Reference numeral 323 denotes a counter electrode including a transparent conductive film layer, and reference numeral 325 denotes a liquid crystal. The pixel TFT 302 is formed in a portion indicated by 326, and the regions 311 and 31 are formed.
Reference numeral 3 denotes a source / drain portion, and the region 312 forms a channel portion. The portion indicated by 327 is the MOS capacitor 3
Regions 313 and 315 form source / drain portions, and region 314 forms a channel portion. FIG. 15 (b)
As is apparent from FIG.
It has exactly the same cross-sectional structure as T302,
No special manufacturing process needs to be added to form the capacitor 305. However, the MOS capacitor 30
In order to use 5 as a storage capacitor, it is necessary to keep a state in which a channel, that is, an inversion layer is formed in the region 314.

In order to maintain this state, a predetermined potential is applied to the gate electrode 306 of the MOS capacitor 305 so that the MOS capacitor is turned on. The predetermined potential is, for example, a positive power supply potential when the MOS capacitor is N-type, and a negative power supply potential when the MOS capacitor is P-type. Since the gate insulating film is usually formed to be very thin, by forming the storage capacitor using the gate insulating film as described above, compared with the conventional one using the interlayer insulating film,
It is possible to obtain 5 to 10 times the storage capacity per unit area, which is very effective in saving the area for forming the storage capacity.

Therefore, the aperture ratio of the active matrix panel can be made extremely high.

The last step of making the present invention more effective relates to the mounting of an active matrix panel incorporating a driver circuit. FIGS. 16A and 16B show specific examples. FIG. 3A is a diagram showing a cross-sectional structure.
Reference numeral 330 denotes a transparent substrate on which a pixel matrix formed by a TFT and a driver circuit are formed, 331 denotes a transparent substrate on which a counter electrode is formed, 334 denotes a sealing material, 333 denotes a sealed liquid crystal, 335 denotes a mounting substrate, and 340 denotes a mounting substrate. The openings 338 in the substrate 335 are wires 339 made of metal such as gold or aluminum.
Is a protection member. In the mounting substrate 335, providing the concave portion 336 in the portion where the transparent substrate 330 is disposed
This is very effective in securing the connection strength of the wire 338. Further, a light shielding member 3 is provided on a part or all of the mounting substrate.
The provision of the light-shielding member 332 in a band shape so as to surround the periphery of the pixel matrix portion on the transparent substrate 331 or the transparent substrate 330 means that the appearance of the active matrix panel as a display device is improved. It is very effective. FIG. 16B is a plan view showing the active matrix panel of FIG. 16A and its mounting structure. Reference numeral 341 denotes a pixel matrix portion, and a dotted line 342 denotes an opening of the mounting substrate 335. The following effects are produced by the above-described operations. First, the metal wire 338
Since the stress applied to the wire becomes uniform, the connection strength is improved.
Second, in the case where the active matrix panel of the present invention is used as a transmissive display device and a light source is installed on the back surface, according to the above-described structure of the present invention, unnecessary light from the periphery of the pixel matrix section is generated. Leakage is prevented, and the appearance of the display device is improved.

At the end of the embodiment, two application examples of the present invention will be described.

One of the application examples is an electronic view finder (Electric View Finder; hereinafter, referred to as a video camera) constituted by using the active matrix panel of the present invention.
EVF). By taking many measures as described above, the complementary TF can be placed around the pixel matrix.
Technology to integrate driver circuits with T has been established,
As an active matrix panel having a small size, high definition, low power consumption and high reliability can be obtained at a low cost, an EVF having a structure as illustrated in FIG. 17 can be realized. In FIG. 17, reference numeral 350 denotes an imaging device;
2 is a recording device; 351 is a video signal processing circuit;
2, a composite video signal is obtained. Reference numeral 353 denotes an EVF. The EVF 353 includes a drive circuit unit 354 including a chroma circuit, a synchronization control circuit, a liquid crystal panel drive signal forming circuit, a power supply circuit, a backlight drive circuit, and a backlight light source 3.
56, a reflection plate 335, a diffusion plate 357, and a polarizing plate 35
8 and 360, an active matrix panel 359 of the present invention, and a lens 361. By doing as described above, the following effects not provided by the conventional EVF using a CRT (Cathode Ray Tube) can be obtained.

(1) By using an active matrix panel having a color filter, an extremely high-definition color EVF having a pixel pitch of 50 μm or less can be realized. In addition, lower power consumption is promoted.

(2) An extremely small, space-saving and extremely lightweight EVF is realized.

(3) The degree of freedom of the shape of the EVF is increased, and a novel design such as a flat EVF becomes possible.

Another application is a projection type color display device using the active matrix panel of the present invention as a liquid crystal light valve.

FIG. 18 is a plan view of the projection type color display device. White light emitted from a projection light source 370 such as a halogen lamp is condensed by a parabolic mirror 371, a heat ray in an infrared region is cut by a heat ray cut filter 372, and only visible light enters the dichroic mirror system.
First, the blue reflecting dichroic mirror 373 reflects blue light (light having a wavelength of approximately 500 nm or less) and transmits other light (yellow light). The reflected blue light changes its direction by a reflection mirror 374 and enters a blue modulation liquid crystal light valve 378.

The light transmitted through the blue reflecting dichroic mirror 373 is incident on the green reflecting dichroic mirror 375 and is converted from green light (generally 500 [nm] to 600 [n].
m], and transmits other red light (light having a wavelength of at least 600 [nm]). The reflected green light is applied to a green modulation liquid crystal light valve 37.
9 is incident.

The red light transmitted through the green reflecting dichroic mirror 375 changes its direction by the reflecting mirrors 376 and 377 and enters the red modulation liquid crystal valve 380.

The blue light, green light and red light are respectively
The liquid crystal light valves 378, 3 of the active matrix panel of the present invention driven by the blue, green, and red primary color signals
After being modulated by 79 and 380, they are combined by a dichroic prism 383. The dichroic prism 383 is configured such that the blue reflection surface 381 and the red reflection surface 382 are orthogonal to each other. The color image thus synthesized is enlarged and projected on a screen by the projection lens 384 and displayed. With the above arrangement, the following effects, which are not provided by the conventional projection type color display device using a CRT projection tube, can be obtained.

(1) Since the liquid crystal light valve can be formed much smaller and more precise than a CRT, it is permitted to use a small-diameter projection lens 384. Therefore, the size, weight, and cost of the projection type color display device can be reduced.

(2) Since the active matrix panel of the present invention has a high aperture ratio, a bright display can be obtained even if a small-diameter projection lens is used.

(3) Unlike the projection tube using a CRT, the dichroic mirror and the dichroic prism allow the optical axes of the red, green and blue light valves to be completely coincident with each other, so that the three-color registration is very good. Becomes

The description of the embodiment of the present invention has been completed.

[0083]

The effects of the present invention will be described with reference to means for solving the above-mentioned problems and embodiments.

First, the effects provided by the four basic techniques that make the present invention effective will be described.

First, by integrating a driver circuit for a gate line or a source line using complementary TFTs on the same transparent substrate as the pixel matrix portion, the following effects can be obtained.

(1) The fineness of the panel is not limited by the connection pitch when mounting the external driver integrated circuit. As a result, by using the present invention, a liquid crystal panel having a pixel pitch of 50 μm can be realized.

(2) The external dimensions of the mounting substrate on which the panel is mounted are greatly reduced, and the reduction in size, thickness, and weight of the display device using the liquid crystal panel of the present invention is promoted.

(3) Since the step of externally attaching a driver integrated circuit is not required, cost reduction of a display device using the liquid crystal panel of the present invention is promoted.

(4) Since no external driver integrated circuit is required, the reliability of the display device using the liquid crystal panel of the present invention is improved.

(5) By forming the driver circuit using complementary TFTs, a synergistic effect with the low power property inherent in the liquid crystal panel is exhibited, and the power consumption of the entire display device is reduced. This is an important factor for enabling application to an EVF of a video camera and a portable image monitor.

Second, the use of complementary TFTs and the shift register having a static circuit configuration not only reduces power consumption, but also has the effect of expanding the operating voltage range and operating frequency range. The TFT has a high off-current characteristic as shown in FIG. 5, and further has a large off-current temperature characteristic. Such a disadvantage of the TFT is compensated for by providing the shift register with a static configuration, and the operating voltage range and the operating frequency range are expanded.

Third, in the structure of the complementary TFT, the source / drain region of the TFT of the first polarity contains the impurity of the first polarity, and the source / drain region of the TFT of the second polarity has the first polarity. By adopting a structure including a polar impurity and a higher concentration of a second polar impurity, a simple single hot process is added to the conventional unipolar TFT manufacturing process. A complementary TFT integrated circuit including the pixel matrix is obtained. Furthermore, P with uniform characteristics
And N-type TFTs are obtained.

Fourth, TFT constituting a driver circuit
By making the gate length shorter than that of the TFTs that make up the pixel matrix, the operating speed of the driver circuit is improved, and the writing and holding operations in each pixel are maintained in an optimal state. Becomes possible.

Next, the effects provided by the seven means for making the present invention more effective will be described.

First, by making the pattern layout of each functional block as shown in FIGS. 8, 9, 10A and 10B, the integration degree of the driver circuit portion is particularly increased, and The unit cell of the driver circuit can be formed within a limited pitch called a pitch.

Second, by arranging the clock wiring of the source line driver circuit as shown in FIG. 11A, the clock noise mixed in the video signal is removed, and the linear display unevenness generated on the screen is not visually recognized. It is possible to suppress to a possible level.

Third, by making the resistance connected to the sample and hold circuit shown in FIG. 12 uniform over all the source lines, the write level of the display signal to all the source lines is made completely uniform. This makes it possible to remove line-shaped display unevenness.

Fourth, the source line driver circuit shown in FIG.
By driving as shown in FIG. 3B, a video signal is sampled at a frequency of 2Nf using an N-series shift register driven by a clock of a frequency f. It becomes possible. by this,
A high-definition active matrix panel with a driver and a single circuit is realized by using TFTs whose ON current is not always sufficient.

Fifth, by providing a test circuit at each output of the driver circuit as shown in FIG. 14, the inspection of the active matrix panel, which was conventionally performed visually with the test pattern displayed, can be performed. This can be performed electrically and automatically.

Sixth, by forming a storage capacitor having a structure as shown in FIGS. 15A and 15B in each pixel, there is no increase in manufacturing cost and almost no decrease in aperture ratio. In addition, it is possible to more reliably hold the charge in each pixel.

Seventh, the mounting structure is shown in FIG.
By adopting the configuration as shown in (b), not only the connection strength and reliability can be improved, but also a case where a transmission type display device is constructed by using a backlight device together with the active matrix panel of the present invention. Unnecessary light can be prevented from leaking from around the pixel matrix portion.

Finally, the effects obtained by applying the present invention to a specific display system will be described.

First, by applying the present invention to an EVF of a video camera, the following effects not provided by the conventional EVF using a CRT can be obtained.

(1) By using an active matrix panel having a color filter, a very high-definition color EVF having a pixel pitch of 50 μm or less can be realized. In addition, lower power consumption is promoted.

(2) An extremely small, space-saving and extremely lightweight EVF is realized.

(3) The degree of freedom of the shape of the EVF is increased, and a novel design such as a flat EVF becomes possible.

Second, by applying the present invention to a projection type color display device, the following effects not provided by a conventional CRT can be obtained.

(1) Since the liquid crystal light valve can be formed much smaller and higher definition than the CRT, it is permissible to use a projection lens having a smaller diameter as the projection lens.

Therefore, the size, weight and cost of the projection type color display device can be reduced.

(2) Since the active matrix panel of the present invention has a high aperture ratio, a bright display can be obtained even if a small-diameter projection lens is used.

(3) Unlike the projection tube using a CRT, the optical axes of the red, green and blue light valves can be completely matched by the dichroic mirror and the dichroic prism, so that the three-color registration is very good. Becomes

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, that is, an active matrix panel in which a driver circuit is integrated in the periphery.

FIGS. 2A to 2F are diagrams illustrating a detailed configuration example of a driver circuit in FIG. 1;

FIGS. 3A and 3B are diagrams illustrating a cross-sectional structure of an active matrix panel of the present invention.

FIGS. 4A to 4D are diagrams illustrating a method for manufacturing an active matrix panel of the present invention.

FIG. 5 is a diagram showing a characteristic example of a TFT according to the present invention in comparison with that of a single-crystal silicon MOSFET.

FIG. 6 is a diagram showing definitions of a gate length and a gate width in this specification.

FIG. 7 is a diagram showing definitions of a depletion layer width and a thickness of a silicon thin film in this specification.

FIGS. 8A and 8B are diagrams for explaining a first means for making the present invention more effective.

FIGS. 9A and 9B are diagrams for explaining a first means for making the present invention more effective.

FIGS. 10A and 10B are diagrams for explaining a first means for making the present invention more effective.

FIGS. 11A and 11B are diagrams for explaining a second means for making the present invention more effective.

FIG. 12 is a diagram for explaining a third means for making the present invention more effective.

FIGS. 13A and 13B are diagrams for explaining a fourth means for making the present invention more effective.

FIG. 14 is a view for explaining a fifth means for making the present invention more effective.

FIGS. 15A and 15B are views for explaining a sixth means for making the present invention more effective.

FIGS. 16A and 16B are views for explaining a seventh means for making the present invention more effective.

FIG. 17 is a diagram showing a first application example of the present invention.

FIG. 18 is a diagram showing a second application example of the present invention.

FIG. 19 is a diagram for explaining a conventional technique.

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[Procedure amendment]

[Submission date] December 24, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

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[Title of the Invention] Projection display device

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[Correction target item name] Claims

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[Claims]

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[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a projection display device having an active matrix panel.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

According to the present invention, in a projection display apparatus having an active matrix panel and projection optical means for projecting light modulated by the active matrix panel, the active matrix panel has a plurality of gate lines and a plurality of gate lines on a substrate. , A pixel matrix having a first transistor of a first conductivity type connected to each of the gate lines and each of the source lines, and a source line driver circuit for supplying a signal to the source lines. The source line driver circuit includes a shift register;
A plurality of sampling means controlled by an output of the shift register to sample a data signal and supply the sampled data signal to the plurality of source lines, wherein the shift register includes a second transistor of a first conductivity type and a second conductivity type. And the sampling means has a fourth transistor of the first conductivity type, the gate length of the first transistor is longer than the gate length of the second transistor, and the gate of the second transistor is The length is longer than the gate length of the fourth transistor.

[Procedure amendment 5]

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The respective effects will be described according to the means for solving the above-mentioned problem and the embodiment.

[Procedure amendment 11]

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(3) Unlike the CRT projection tube, the optical axes of the red, green and blue light valves can be completely matched by the dichroic mirror and dichroic prism, which is very good for registration of three colors. .

As described above, according to the present invention, the gate length of the transistor of the first conductivity type in the pixel matrix is reduced.
By increasing the gate length of the first conductivity type transistor of the sampling means, the leak current of the first conductivity type transistor of the pixel matrix is suppressed, a clear image without crosstalk is realized, and the speed of the sampling means is increased. Can be realized. Further, since the transistor of the first conductivity type of the sampling means may have a lower breakdown voltage than the transistor of the first conductivity type of the shift register, the transistor of the sampling means can be formed to have a shorter gate length than the transistor of the shift register.

Claims (5)

[Claims] A first transparent substrate on which a pixel matrix including a plurality of gate lines, a plurality of source lines, and a thin film transistor is formed, and a second transparent substrate disposed opposite to the first transparent substrate; An active matrix panel comprising a transparent substrate and a liquid crystal interposed between the first and second transparent substrates, wherein a gate comprising a complementary thin film transistor made of a silicon thin film is formed on the first transparent substrate. A thin film transistor constituting the pixel matrix is provided with at least one of a line driver circuit and a source line driver circuit comprising a complementary thin film transistor formed of a silicon thin film; P that constitutes
An active matrix panel having the same cross-sectional structure as one of a thin film transistor and an N-type thin film transistor. 2. The active matrix panel according to claim 1, wherein said gate line driver circuit and said source line driver circuit include a static shift register using a complementary thin film transistor. 3. The gate line driver circuit and the source line driver circuit are composed of P-type and N-type thin film transistors. The P-type thin film transistor includes an aceptor impurity in a source region and a drain region. 3. The active matrix panel according to claim 1, wherein the thin film transistor includes an acceptor impurity and a donor impurity having a higher concentration than the acceptor impurity in the source region and the drain region. 4. The gate line driver circuit and the source line driver circuit include P-type and N-type thin film transistors, wherein the N-type thin film transistor includes donor impurities in a source region and a drain region, and includes a P-type thin film transistor. 3. The active matrix panel according to claim 1, wherein the thin film transistor includes a source region and a drain region each containing a donor impurity and an acceptor impurity having a higher concentration than the donor impurity. 5. The gate length of the P-type and N-type thin film transistors constituting the gate line driver circuit and the source line driver circuit is longer than the gate length of the thin film transistor constituting the pixel matrix. 3. The active matrix panel according to claim 1, wherein the active matrix panel is formed short.