JPH11186447A - Resin sealing semiconductor device and its manufacture and its manufacturing device - Google Patents
Resin sealing semiconductor device and its manufacture and its manufacturing deviceInfo
- Publication number
- JPH11186447A JPH11186447A JP9355933A JP35593397A JPH11186447A JP H11186447 A JPH11186447 A JP H11186447A JP 9355933 A JP9355933 A JP 9355933A JP 35593397 A JP35593397 A JP 35593397A JP H11186447 A JPH11186447 A JP H11186447A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- encapsulated
- manufacturing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂封止半導体装
置の構造、その製造方法及びその製造装置に関するもの
である。The present invention relates to a structure of a resin-encapsulated semiconductor device, a method of manufacturing the same, and an apparatus for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、このような分野の樹脂封止半導体
装置としては、以下に示すようなものがあった。図９は
かかる従来の樹脂封止半導体装置の断面図である。この
図に示すように、従来の樹脂封止半導体装置は、ダイパ
ット１上に導電性、及び絶縁性のペースト剤２により接
着された半導体素子３上の電極パッド４と外部電極５を
金属細線６により電気的に接続したものを樹脂７で封止
した構造であった。2. Description of the Related Art Conventionally, there have been the following resin-sealed semiconductor devices in such a field. FIG. 9 is a sectional view of such a conventional resin-sealed semiconductor device. As shown in this figure, the conventional resin-encapsulated semiconductor device is configured such that an electrode pad 4 on a semiconductor element 3 and an external electrode 5 bonded to a die pad 1 with a conductive and insulating paste material 2 are connected to a thin metal wire 6. The structure electrically sealed with the resin 7 was used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記し
た従来の樹脂封止半導体装置の構造では、半導体素子上
の電極パッドと外部電極を金属細線により接続するた
め、樹脂封止サイズが大きくなってしまう。また、リー
ドフレームにより外部電極を設けるため半導体装置の製
造コストが高くなってしまうという問題があった。However, in the above-described structure of the conventional resin-sealed semiconductor device, the electrode pad on the semiconductor element and the external electrode are connected by a thin metal wire, so that the resin-sealed size becomes large. . In addition, there is a problem that the manufacturing cost of the semiconductor device is increased because the external electrodes are provided by the lead frame.
【０００４】本発明は、上記問題点を除去し、樹脂封止
サイズを小さくし、外部電極を低コストで形成すること
ができる樹脂封止半導体装置、その製造方法及びその製
造装置を提供することを目的とする。An object of the present invention is to provide a resin-encapsulated semiconductor device capable of reducing the above-mentioned problems, reducing the size of the resin encapsulation, and forming an external electrode at low cost, a method of manufacturing the same, and an apparatus for manufacturing the same. With the goal.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 〔１〕樹脂封止半導体装置において、半導体素子上の電
極パッドに接合された金属細線を樹脂封止部の端面に露
出させ、この露出した金属細線を外部電極とするように
したものである。According to the present invention, in order to achieve the above object, [1] In a resin-sealed semiconductor device, a thin metal wire bonded to an electrode pad on a semiconductor element is formed on an end face of a resin-sealed portion. And the exposed thin metal wires are used as external electrodes.
【０００６】〔２〕樹脂封止半導体装置の製造方法にお
いて、半導体ウエハ状態で、隣り合う半導体素子の電極
パッド同志を金属細線で接合する工程と、半導体ウエハ
状態で樹脂封止し、樹脂封止部を形成する工程と、ダイ
シングブレードで個々の半導体素子に分割し、前記金属
細線を分割された樹脂封止部の表面に露出させ、前記金
属細線の露出部を外部電極として形成する工程とを施す
ようにしたものである。[2] In a method of manufacturing a resin-encapsulated semiconductor device, a step of bonding adjacent electrode pads of a semiconductor element with a thin metal wire in a semiconductor wafer state; Forming a portion, and dividing the individual metal element into individual semiconductor elements with a dicing blade, exposing the fine metal wires to the surfaces of the divided resin sealing portions, and forming the exposed portions of the fine metal wires as external electrodes. It is intended to be applied.
【０００７】〔３〕上記〔２〕記載の樹脂封止半導体装
置の製造方法において、半導体ウエハ状態で樹脂封止さ
れた半導体ウエハを個々の半導体素子に分割する際のア
ライメントを決めるためのグリットラインを前記半導体
ウエハの樹脂封止領域外に延長して残して樹脂封止する
ようにしたものである。 〔４〕上記〔２〕記載の樹脂封止半導体装置の製造方法
において、前記ダイシングブレードで個々の半導体素子
に分割する際に、前記金属細線が表面実装可能な位置に
露出するように前記ダイシングブレードの両側にテーパ
を備えたダイシングブレードで分割し、個々の半導体素
子の前記金属細線をテーパ部に露出させるようにしたも
のである。[3] In the method of manufacturing a resin-encapsulated semiconductor device according to the above [2], a grid line for determining alignment when dividing a semiconductor wafer resin-encapsulated in a semiconductor wafer state into individual semiconductor elements. Is extended outside the resin-sealed region of the semiconductor wafer to be sealed with the resin. [4] In the method for manufacturing a resin-encapsulated semiconductor device according to the above [2], the dicing blade is divided into individual semiconductor elements by the dicing blade so that the thin metal wire is exposed at a surface mountable position. Is divided by a dicing blade having a taper on both sides thereof, so that the thin metal wire of each semiconductor element is exposed to a tapered portion.
【０００８】〔５〕樹脂封止半導体装置の製造装置にお
いて、半導体ウエハ状態で樹脂封止するためのモールド
金型に半導体ウエハをクランプする際に半導体ウエハの
破損を防止するウエハ割れ防止ブロックを具備するよう
にしたものである。[5] The apparatus for manufacturing a resin-sealed semiconductor device is provided with a wafer crack prevention block for preventing breakage of the semiconductor wafer when the semiconductor wafer is clamped to a mold for resin sealing in a semiconductor wafer state. It is something to do.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態につい
て詳細に説明する。図１は本発明の実施例を示す樹脂封
止半導体装置の断面図である。この図において、１１は
半導体素子、１２は電極パッド、１３は金属細線、１４
は樹脂封止部（パッケージ）、１５は半田ボール（又は
半田バンプ）である。Embodiments of the present invention will be described below in detail. FIG. 1 is a sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention. In this figure, 11 is a semiconductor element, 12 is an electrode pad, 13 is a thin metal wire, 14
Denotes a resin sealing portion (package), and 15 denotes a solder ball (or solder bump).
【００１０】このように、半導体素子１１上の電極パッ
ド１２に接続された金属細線１３が樹脂封止部１４の表
面に露出している。その露出した金属細線１３に、半田
ボール１５が接合されている。なお、１１Ａは半導体素
子１１のテーパ部である。ここでは、樹脂封止部１４の
表面に露出した金属細線１３を直接外部電極としてい
る。樹脂封止部１４の表面に露出した金属細線１３に
は、接合性を良くするための半田ボール１５を設ける。As described above, the fine metal wires 13 connected to the electrode pads 12 on the semiconductor element 11 are exposed on the surface of the resin sealing portion 14. The solder balls 15 are joined to the exposed thin metal wires 13. Note that 11A is a tapered portion of the semiconductor element 11. Here, the thin metal wires 13 exposed on the surface of the resin sealing portion 14 are directly used as external electrodes. Solder balls 15 are provided on the fine metal wires 13 exposed on the surface of the resin sealing portion 14 to improve the bonding property.
【００１１】以下、この実施例の樹脂封止半導体装置の
製造方法について説明する。 （１）まず、図２（ａ）〜図２（ｃ）に示すように、半
導体ウエハ１０上の隣り合う半導体素子１１の電極パッ
ド１２同志を金属細線１３にて接続する。このときのワ
イヤボンディング方法は、低ループ及びループ形状を左
右対象にするためにウェッジボンドであることが望まし
い。なお、１０Ａはグリッドラインを示している。Hereinafter, a method of manufacturing the resin-sealed semiconductor device of this embodiment will be described. (1) First, as shown in FIGS. 2A to 2C, electrode pads 12 of adjacent semiconductor elements 11 on a semiconductor wafer 10 are connected by thin metal wires 13. The wire bonding method at this time is desirably wedge bonding to make the low loop and the loop shape symmetrical. 10A indicates a grid line.
【００１２】（２）次に、図３（ａ）に示すように、半
導体ウエハ１０の全体に樹脂封止部１４を形成する。そ
の断面を示すと、図３（ｂ）のようになる。 （３）次いで、図４に示すように、樹脂封止後、ダイシ
ングブレード（図示なし）により、個々の半導体素子１
１に分割し、その半導体素子のテーパ部１１Ａに金属細
線１３の先端を露出させる。(2) Next, as shown in FIG. 3A, a resin sealing portion 14 is formed on the entire semiconductor wafer 10. FIG. 3B shows the cross section. (3) Next, as shown in FIG. 4, after sealing with resin, individual semiconductor elements 1 are cut with a dicing blade (not shown).
The semiconductor device is divided into 1 and the tip of the thin metal wire 13 is exposed at the tapered portion 11A of the semiconductor element.
【００１３】（４）最後に、図５に示すように、金属細
線１３が露出した部分に半田ボール１５を形成する。 以下、上記した各製造工程を詳細に説明する。図６は本
発明の実施例の金属細線を接合済の半導体ウエハをモー
ルド上金型、モールド下金型でクランプした状態を示す
図である。(4) Finally, as shown in FIG. 5, a solder ball 15 is formed on a portion where the fine metal wire 13 is exposed. Hereinafter, each of the above manufacturing steps will be described in detail. FIG. 6 is a view showing a state in which the semiconductor wafer to which the thin metal wires of the embodiment of the present invention have been joined is clamped by the upper mold and the lower mold.
【００１４】この図に示すように、モールド上金型２
１、モールド下金型２２には、ウエハ割れ防止ブロック
２６が設けられている。なお、２３は樹脂注入ランナ
ー、２４は上部キャビティ、２５は下部キャビティ、２
７は樹脂洩れ防止部材である。そこで、まず、モールド
下金型２２に半導体ウエハ１０をセットし、モールド上
金型２１とモールド下金型２２で半導体ウエハ１０をク
ランプする。クランプ位置については、ウエハ割れ防止
ブロック２６にて決定する。As shown in FIG.
1. A wafer crack prevention block 26 is provided in the lower mold 22. 23 is a resin injection runner, 24 is an upper cavity, 25 is a lower cavity, 2
Reference numeral 7 denotes a resin leakage prevention member. Therefore, first, the semiconductor wafer 10 is set on the lower mold 22, and the semiconductor wafer 10 is clamped by the upper mold 21 and the lower mold 22. The clamp position is determined by the wafer crack prevention block 26.
【００１５】このように、モールド上金型２１とモール
ド下金型２２にまず当接するウエハ割れ防止ブロック２
６を設けることにより、半導体ウエハ１０をクランプす
る際に、半導体ウエハ１０を過度に押さえ付けることが
なくなり、半導体ウエハ１０が破損することを防ぐこと
ができる。ウエハ割れ防止ブロック２６のサイズについ
ては、半導体ウエハ１０の厚さ、反り量等を考慮し決定
する。As described above, the wafer crack preventing block 2 which first comes into contact with the upper mold 21 and the lower mold 22.
By providing 6, the semiconductor wafer 10 can be prevented from being excessively pressed down when the semiconductor wafer 10 is clamped, and the semiconductor wafer 10 can be prevented from being damaged. The size of the wafer crack prevention block 26 is determined in consideration of the thickness of the semiconductor wafer 10, the amount of warpage, and the like.
【００１６】ここで、図７に示すように、半導体ウエハ
１０の樹脂封止領域端面からは、グリットライン１０Ａ
が適当にはみ出すようにしている。したがって、半導体
ウエハ１０を、樹脂封止する際に用いるモールド上金型
２１、モールド下金型２２は、各グリットライン１０Ａ
の両端が適当にはみ出すように上部キャビティ２４、下
部キャビティ２５のサイズが決められており、樹脂封止
部１４からはみ出したグリットライン１０Ａをアライメ
ントマークとすることにより、個々の半導体素子１１に
分割する際のアライメントが容易になる。Here, as shown in FIG. 7, a grit line 10A is
But it protrudes appropriately. Therefore, the upper mold 21 and the lower mold 22 used for sealing the semiconductor wafer 10 with the resin are formed in each grit line 10A.
The size of the upper cavity 24 and the lower cavity 25 is determined so that both ends protrude appropriately, and the grid line 10A protruding from the resin sealing portion 14 is used as an alignment mark to divide the semiconductor element 11 into individual semiconductor elements 11. Alignment becomes easier.
【００１７】図８は本発明の実施例を示す金属細線を接
合済の半導体ウエハを樹脂封止したもののダイシング工
程を示す断面図である。まず、図８（ａ）に示すよう
に、金属細線１３を接合済の半導体ウエハ１０が樹脂封
止された樹脂封止部１４が形成されている。その裏面に
ダイシングテープ３１を貼り付け、半導体ウエハ１０を
ダイシングテープ３１で固定する。FIG. 8 is a cross-sectional view showing a dicing step of a semiconductor wafer to which thin metal wires have been bonded and which has been resin-sealed according to an embodiment of the present invention. First, as shown in FIG. 8A, a resin sealing portion 14 in which the semiconductor wafer 10 to which the thin metal wires 13 have been bonded is resin-sealed is formed. A dicing tape 31 is attached to the back surface, and the semiconductor wafer 10 is fixed with the dicing tape 31.
【００１８】次に、図８（ｂ）に示すように、ダイシン
グブレード４１を用いて、個々の半導体素子１１に分割
する。ここで、ダイシングブレード４１には、その両肩
にテーパ４２を形成するようにすることが望ましい。こ
のダイシングブレード４１により、樹脂封止済の半導体
ウエハ１０を個々の半導体素子１１に分割することによ
り、その半導体素子１１の切断面にテーパ部１１Ａが形
成され、このテーパ部１１Ａから金属細線１３が露出す
る。Next, as shown in FIG. 8B, the semiconductor device 11 is divided into individual semiconductor elements 11 using a dicing blade 41. Here, it is desirable that the dicing blade 41 is formed with a taper 42 at both shoulders. By dividing the resin-sealed semiconductor wafer 10 into individual semiconductor elements 11 by the dicing blade 41, a tapered portion 11A is formed on a cut surface of the semiconductor element 11, and a thin metal wire 13 is formed from the tapered portion 11A. Exposed.
【００１９】このように、ダイシングブレード４１のテ
ーパ４２により、個々の半導体素子１１の切断面にテー
パ部１１Ａを設けることができ、このテーパ部１１Ａが
実装面となるため、露出した金属細線１３に半田ボール
１５を設けて、容易に実装することができる。そのテー
パ部１１Ａの角度については、用途により適当に決める
ことができる。As described above, the taper 42 of the dicing blade 41 allows the tapered portion 11A to be provided on the cut surface of each semiconductor element 11, and the tapered portion 11A becomes the mounting surface. Providing the solder balls 15 allows easy mounting. The angle of the tapered portion 11A can be appropriately determined depending on the application.
【００２０】したがって、この実施例の樹脂封止半導体
装置は、半導体素子１１上の電極パッド１２に接続した
金属細線１３部が外部電極となるため、従来のように、
リードフレームにより外部電極を設ける必要がなくな
り、樹脂封止部（パッケージ）のサイズが小さくなるた
め、リードフレーム・樹脂等の材料費を大幅に省くこと
ができる。よって、個々の半導体素子の製造コストを低
減することができる。Therefore, in the resin-encapsulated semiconductor device of this embodiment, the thin metal wire 13 connected to the electrode pad 12 on the semiconductor element 11 becomes the external electrode.
The lead frame eliminates the need for providing external electrodes, and the size of the resin sealing portion (package) is reduced, so that material costs for the lead frame, resin, and the like can be significantly reduced. Therefore, the manufacturing cost of each semiconductor element can be reduced.
【００２１】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００２２】[0022]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （Ａ）請求項１又は２記載の発明によれば、樹脂封止サ
イズを小さくし、外部電極を低いコストで形成すること
ができる。As described above, according to the present invention, the following effects can be obtained. (A) According to the first or second aspect of the present invention, the size of the resin sealing can be reduced, and the external electrodes can be formed at low cost.
【００２３】（Ｂ）請求項３記載の発明によれば、半導
体ウエハを、樹脂封止する際に用いるモールド上金型、
モールド下金型は、各グリットライン１０Ａの両端が適
当にはみ出すように上部キャビティ、下部キャビティの
サイズが決められており、樹脂封止部からはみ出したグ
リットラインをアライメントマークとすることにより、
個々の半導体素子に分割する際のアライメントが容易に
なる。(B) According to the third aspect of the present invention, an upper mold used for sealing a semiconductor wafer with a resin,
In the lower mold, the size of the upper cavity and the lower cavity is determined so that both ends of each grit line 10A appropriately protrude, and the grit line protruding from the resin sealing portion is used as an alignment mark,
Alignment when dividing into individual semiconductor elements is facilitated.
【００２４】（Ｃ）請求項４記載の発明によれば、ダイ
シングブレードのテーパにより、個々の半導体素子の切
断面にテーパ部を設けることができ、このテーパ部が実
装面となるため、露出した金属細線に半田ボールを設け
て、容易に実装することができる。 （Ｄ）請求項５記載の発明によれば、モールド上金型と
モールド下金型にまず当接するウエハ割れ防止ブロック
を設けることにより、半導体ウエハをクランプする際
に、半導体ウエハを過度に押さえ付けることがなくな
り、半導体ウエハが破損することを防ぐことができる。(C) According to the fourth aspect of the present invention, the taper of the dicing blade can provide a tapered portion on the cut surface of each semiconductor element, and the tapered portion becomes a mounting surface and is exposed. A solder ball can be provided on a thin metal wire to facilitate mounting. (D) According to the fifth aspect of the present invention, by providing the wafer crack preventing block that first comes into contact with the upper mold and the lower mold, the semiconductor wafer is excessively pressed when clamping the semiconductor wafer. And the semiconductor wafer can be prevented from being damaged.
【図１】本発明の実施例を示す樹脂封止半導体装置の断
面図である。FIG. 1 is a sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention.
【図２】本発明の実施例を示す樹脂封止半導体装置の第
１製造工程の説明図である。FIG. 2 is an explanatory diagram of a first manufacturing process of the resin-sealed semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施例を示す樹脂封止半導体装置の第
２製造工程の説明図である。FIG. 3 is an explanatory diagram of a second manufacturing step of the resin-sealed semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施例を示す樹脂封止半導体装置の第
３製造工程の説明図である。FIG. 4 is an explanatory view of a third manufacturing step of the resin-sealed semiconductor device according to the embodiment of the present invention.
【図５】本発明の実施例を示す樹脂封止半導体装置の最
終工程の説明図である。FIG. 5 is an explanatory diagram of a final step of the resin-sealed semiconductor device according to the embodiment of the present invention.
【図６】本発明の実施例の金属細線を接合済の半導体ウ
エハをモールド上金型、モールド下金型でクランプした
状態を示す図である。FIG. 6 is a view showing a state in which the semiconductor wafer to which the thin metal wires according to the embodiment of the present invention have been joined is clamped by an upper mold and a lower mold.
【図７】本発明の実施例を示す半導体ウエハの斜視図で
ある。FIG. 7 is a perspective view of a semiconductor wafer showing an embodiment of the present invention.
【図８】本発明の実施例を示す金属細線を接合済の半導
体ウエハを樹脂封止したもののダイシング工程を示す断
面図である。FIG. 8 is a cross-sectional view showing a dicing step in which a semiconductor wafer to which metal thin wires have been bonded is sealed with a resin according to the embodiment of the present invention.
【図９】従来の樹脂封止半導体装置の断面図である。FIG. 9 is a cross-sectional view of a conventional resin-sealed semiconductor device.
１０ 半導体ウエハ １０Ａ グリッドライン １１ 半導体素子 １１Ａ テーパ部 １２ 電極パッド １３ 金属細線 １４ 樹脂封止部（パッケージ） １５ 半田ボール（又は半田バンプ） ２１ モールド上金型 ２２ モールド下金型 ２３ 樹脂注入ランナー ２４ 上部キャビティ ２５ 下部キャビティ ２６ ウエハ割れ防止ブロック ２７ 樹脂洩れ防止部材 ３１ ダイシングテープ ４１ ダイシングブレード ４２ テーパ DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 10A Grid line 11 Semiconductor element 11A Tapered part 12 Electrode pad 13 Fine metal wire 14 Resin sealing part (package) 15 Solder ball (or solder bump) 21 Mold upper mold 22 Mold lower mold 23 Resin injection runner 24 Upper part Cavity 25 Lower cavity 26 Wafer crack prevention block 27 Resin leakage prevention member 31 Dicing tape 41 Dicing blade 42 Taper
Claims (5)
封止部の端面に露出させ、該露出した金属細線を外部電
極とすることを特徴とする樹脂封止半導体装置。In a resin-encapsulated semiconductor device, a thin metal wire bonded to an electrode pad on a semiconductor element is exposed at an end face of a resin sealing portion, and the exposed thin metal wire is used as an external electrode. Resin-sealed semiconductor device.
て、（ａ）半導体ウエハ状態で、隣り合う半導体素子の
電極パッド同志を金属細線で接合する工程と、（ｂ）半
導体ウエハ状態で樹脂封止し、樹脂封止部を形成する工
程と、（ｃ）ダイシングブレードで個々の半導体素子に
分割し、前記金属細線を分割された樹脂封止部の表面に
露出させ、前記金属細線の露出部を外部電極として形成
する工程とを施すことを特徴とする樹脂封止半導体装置
の製造方法。2. A method of manufacturing a resin-encapsulated semiconductor device, comprising: (a) bonding electrode pads of adjacent semiconductor elements with a thin metal wire in a semiconductor wafer state; and (b) resin encapsulation in a semiconductor wafer state. Forming a resin-sealed portion; and (c) dividing into individual semiconductor elements with a dicing blade, exposing the fine metal wires to the surfaces of the divided resin-sealed portions, and exposing the exposed portions of the fine metal wires. Forming a resin-encapsulated semiconductor device.
造方法において、半導体ウエハ状態で樹脂封止された半
導体ウエハを個々の半導体素子に分割する際のアライメ
ントを決めるためのグリットラインを前記半導体ウエハ
の樹脂封止領域外に延長して残して樹脂封止することを
特徴とする樹脂封止半導体装置の製造方法。3. The method of manufacturing a resin-encapsulated semiconductor device according to claim 2, wherein the grid line for determining alignment when dividing the semiconductor wafer resin-encapsulated in a semiconductor wafer state into individual semiconductor elements is formed. A method of manufacturing a resin-encapsulated semiconductor device, wherein a resin is encapsulated while being extended outside a resin-encapsulated region of a semiconductor wafer.
造方法において、前記ダイシングブレードで個々の半導
体素子に分割する際に、前記金属細線が表面実装可能な
位置に露出するように前記ダイシングブレードの両側に
テーパを備えたダイシングブレードで分割し、個々の半
導体素子の前記金属細線をテーパ部に露出させることを
特徴とする樹脂封止半導体装置の製造方法。4. The method for manufacturing a resin-encapsulated semiconductor device according to claim 2, wherein, when the dicing blade is divided into individual semiconductor elements, the dicing is performed such that the thin metal wires are exposed at positions where surface mounting is possible. A method for manufacturing a resin-encapsulated semiconductor device, comprising: dividing a semiconductor device by a dicing blade having a taper on both sides of the blade;
て、 半導体ウエハ状態で樹脂封止するためのモールド金型に
半導体ウエハをクランプする際の半導体ウエハの破損を
防止するウエハ割れ防止ブロックを具備することを特徴
とする樹脂封止半導体装置の製造装置。5. An apparatus for manufacturing a resin-encapsulated semiconductor device, comprising: a wafer crack preventing block for preventing damage to the semiconductor wafer when clamping the semiconductor wafer to a mold for resin-sealing in a semiconductor wafer state. An apparatus for manufacturing a resin-encapsulated semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35593397A JP3847432B2 (en) | 1997-12-25 | 1997-12-25 | Resin-encapsulated semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35593397A JP3847432B2 (en) | 1997-12-25 | 1997-12-25 | Resin-encapsulated semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11186447A true JPH11186447A (en) | 1999-07-09 |
| JP3847432B2 JP3847432B2 (en) | 2006-11-22 |
Family
ID=18446487
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35593397A Expired - Fee Related JP3847432B2 (en) | 1997-12-25 | 1997-12-25 | Resin-encapsulated semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3847432B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147096A (en) * | 2008-12-16 | 2010-07-01 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2010182904A (en) * | 2009-02-06 | 2010-08-19 | Fujitsu Ltd | Method of manufacturing semiconductor device |
| JP2011029581A (en) * | 2008-11-28 | 2011-02-10 | Shinko Electric Ind Co Ltd | Semiconductor device, and method of manufacturing semiconductor device |
-
1997
- 1997-12-25 JP JP35593397A patent/JP3847432B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011029581A (en) * | 2008-11-28 | 2011-02-10 | Shinko Electric Ind Co Ltd | Semiconductor device, and method of manufacturing semiconductor device |
| JP2010147096A (en) * | 2008-12-16 | 2010-07-01 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2010182904A (en) * | 2009-02-06 | 2010-08-19 | Fujitsu Ltd | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3847432B2 (en) | 2006-11-22 |
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