JPH11167794A - Semiconductor memory and its backup method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and its backup method which can perform write and read at a high speed, has the long life and high reliability. SOLUTION: When Drop of a power source voltage is detected by a power source voltage detecting circuit 7, a control circuit 9 stops external access for a semiconductor memory 3 for main memory being volatile, transfers data stored in the semiconductor memory 3 for main memory to a semiconductor memory 5 for backup being non-volatile and stores it. Thereby, normally, write and read of data are performed for the semiconductor memory 3 for main memory being accessible at a high speed, at the time of backup, backup of data is performed for the semiconductor memory 5 for backup requiring no backup power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for backing up contents to be stored by detecting a power supply voltage, and a backup method thereof.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor memory device is installed in a system and operates, power supply may be interrupted due to a power failure or the like. Then, the contents stored in the semiconductor device may be lost, and eventually, the function of the system may be stopped. For this reason, in many cases, a backup function is provided in advance in the semiconductor memory device in consideration of interruption of the supply of the power supply voltage.

The following are examples of semiconductor storage devices having such a backup function. FIG.
1 is a block diagram showing a configuration example of a conventional semiconductor memory device having a backup function.

The semiconductor storage device 101 has a semiconductor storage memory 103, a power supply voltage detection circuit 105, a control circuit 107, and a backup power supply 109.

The semiconductor memory 103 is, for example, a dynamic random access memory (DRAM).
ry for short, DRAM), static RAM (Stat
A volatile memory such as an ic random access memory (SRAM) is used. These volatile memories are
Without the supply of the power supply voltage, the stored contents cannot be held, but writing and reading can be performed at high speed. Therefore, by using these as the semiconductor memory 103, the speed of the semiconductor memory device 101 can be increased. Normally, the semiconductor memory 103 has a power supply voltage 111
And the contents to be stored are held.

[0006] The power supply voltage detection circuit 105 has a power supply voltage 11
Monitor 1 When the voltage value of the power supply voltage 111 drops abnormally, the power supply voltage detection circuit 105 outputs the detection signal 11
3 is output.

The control circuit 107 includes a power supply voltage detecting circuit 10
5, the control signal 115 is input.
Power supply from the power supply voltage 111 of the semiconductor memory 103 is prohibited. Then, instead, the power supply from the backup power supply 109 is permitted.

The backup power supply 109 is provided between the semiconductor memory 103 and the ground voltage 117. For example, it is composed of a battery and a capacitor.

Such a semiconductor memory device 101 has a central processing unit (Ce) for performing various controls of a system to be incorporated.
Address information is sent from an ntal processing unit (CPU, abbreviated as CPU) via an address bus 119, and an address in the semiconductor memory 103 to be written and read is specified. Further, data of various processes is read from the semiconductor memory 103 via the data bus 121 or written into the semiconductor memory 103.
Usually, the power supply voltage 1
Power is supplied from the power supply 11, and when an abnormality occurs in the power supply voltage 111, the power supply is instantaneously switched from the power supply voltage 111 to the backup power supply 117. By doing so, stable power is supplied to the semiconductor memory 103.

However, the conventional semiconductor memory device 101
Uses a battery, a capacitor, or the like as the backup power supply 109 for the semiconductor memory 103, so that there is a problem that the time during which power can be supplied to the semiconductor memory 103, that is, the time during which backup can be performed, is limited. Was. In order to make the backup time as long as possible in all situations, the number of batteries and capacitors must be increased, which may result in an increase in cost.

In order to solve this problem, a semiconductor memory device using a nonvolatile memory that does not require the backup power supply 109 as the semiconductor memory 103 is conceivable. A non-volatile memory is a memory that can hold contents to be stored without power supply, unlike the volatile memory. As this nonvolatile memory, for example, an EEPROM (Electrically Erasable and Progra
mmable Read Only Memory), Flash Memory (Flush
Memory) can be used. EEPROMs and flash memories have floating gates that are electrically insulated from the surroundings. By injecting or discharging charges therefrom, data of "1" or "0" level can be stored. Is what you do. The injection of charges into the floating gate and the discharge of charges from the floating gate are performed using a tunnel current flowing through a thin oxide film (generally called a “tunnel oxide film”). These non-volatile memories can retain the contents to be stored without power supply, so that a backup power supply is not required and a sufficient backup time can be provided. Since the contents held in the EEPROM and the flash memory can be electrically erased, the contents can be changed while being mounted on the semiconductor memory device 101.

However, the following problem has occurred even in a semiconductor memory device using a nonvolatile memory as the semiconductor memory 103. As described above, in the EEPROM and the flash memory, the data is rewritten by injecting and extracting the electric charge to and from the floating gate through the tunnel oxide film, so that the data is rewritten as compared with the case where the volatile memory is used. That is, the time required for rewriting data becomes longer. Further, the tunnel oxide film is damaged by passing the electric charge, and eventually causes dielectric breakdown.
Therefore, there is a limit to the number of times data can be rewritten, and the period of use of the semiconductor memory device is shorter than the case where the volatile memory is used.

[0013]

As described above, the conventional semiconductor memory device has a DRA as a semiconductor memory.
When a volatile memory such as M or SRAM is used, the time during which the memory can be backed up is finite, and the number of batteries and capacitors must be increased in order to maximize the time during which the memory can be backed up. However, there is a problem that the cost is increased as a result.

Further, EEPRO is used as a semiconductor memory.
In the case of using a nonvolatile memory such as an M or flash memory, the data rewriting time becomes longer, so that the speed of the semiconductor memory device cannot be increased. Also, EEP
There is a limit to the number of times data can be rewritten in a ROM or a flash memory, and as a result, the useful life of a semiconductor memory device is shortened.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable high-speed writing and reading.
An object of the present invention is to provide a semiconductor memory device having a long service life and high reliability, and a backup method thereof.

[0016]

In order to achieve the above object, the present invention relates to a power supply voltage detecting circuit for detecting a power supply voltage and a control circuit for performing various controls in a semiconductor memory device for storing various data. And a main memory semiconductor memory for exchanging data with the outside, and at least a backup semiconductor memory for exchanging data with the main memory semiconductor memory, when the power supply voltage drops below a predetermined value. Wherein the power supply voltage detection circuit outputs a signal to the control circuit, and the control circuit that has received the signal transfers data stored in the main storage semiconductor memory to the backup semiconductor storage memory. I do.

In this case, the main memory semiconductor memory is an SRAM or DRA which can write and read at high speed.
It is preferable to use a volatile memory such as M from the viewpoint of realizing high-speed access of the semiconductor device. In addition, an EEPROM, a flash memory, or the like that can store data without power supply is preferable as the semiconductor memory for backup.

The present invention having such a structure is usually provided with:
Performs high-speed access by writing / reading from / to volatile memory that can be accessed at high speed and backing up the data to a non-volatile memory that can store data without power supply when the power supply voltage drops And a semiconductor memory device which does not require a backup power supply can be realized. Also, there is no increase in cost.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. The semiconductor storage device 1 includes a main storage semiconductor storage memory 3, a backup semiconductor storage memory 5, a power supply voltage detection circuit 7,
Control circuit 9, address value supply circuit 11, selection circuit 1
And 3.

The main storage semiconductor memory 3 is directly accessed from the outside and stores data during normal operation, that is, when stable power supply from the power supply voltage 15 is performed. Access functions are more important than storage functions, and high speed is required. Specifically, a volatile memory such as a DRAM or an SRAM described in the conventional example is used. This is because these memories can write and read at high speed as described above.

The backup semiconductor storage memory 5 stores data stored in the main storage semiconductor storage memory 3 during a backup operation, that is, when the power supply voltage 15 drops. Further, at the time of the setup operation, that is, when the power supply voltage 15 is turned on, the data is transferred to the main memory 3. The storage function is more important than the access function, and data preservation is required. Specifically, a nonvolatile memory such as an EEPROM or a flash memory described in the conventional example is used. This is because these memories can hold the contents to be stored without power supply as described above.

The power supply voltage detection circuit 7 monitors the power supply voltage 15 as in the conventional example. When the voltage value of the power supply voltage 15 drops abnormally, and when the power supply voltage 15 is turned on again, the power supply voltage detection circuit 7 outputs a detection signal 17.

When the control circuit 9 receives the detection signal 17 from the power supply voltage detection circuit 7, the control signal 19 directly accesses the main storage semiconductor memory 3, while the control signal 25 directly accesses the backup semiconductor storage memory 5. I do. Then, control of data transfer between the semiconductor memory for main storage 3 and the semiconductor memory for backup 5 is performed. Further, at the same time, the selection signal 23 is supplied to the selection circuit 13 by the address value supply circuit 11.
Output a control signal 25.

When a control signal 25 is input from the control circuit 9, the address value supply circuit 11 outputs predetermined address information to the main storage semiconductor memory 3 and the backup semiconductor storage memory 5 via the address bus 27. I do. The address value supply circuit 11 specifies an address in the semiconductor memory for main storage 3 and the semiconductor memory for backup 5 to be written and read. As the address value supply circuit 11, for example, a general counter can be used.

The selection circuit 13 accesses the main memory 3 by the control circuit 9 or accesses the external C memory.
Whether to perform by PU or the like (not shown) is selected. Specifically, during normal operation, the selection circuit 13 selects the control signal 29 from the control signal 19 from the control circuit 9 and the control signal 29 from an external CPU or the like. Then, the control signal 29 is input to the semiconductor memory for main storage 3 via the selection circuit 13, and an external CPU or the like makes access. On the other hand, during the backup operation and the setup operation, the selection circuit 13 receives the selection signal 23 from the control circuit 9 and selects the control signal 19 from the control circuit 9. And control signal 1
9 is a semiconductor memory for main storage 3 via a selection circuit 13
And the control circuit 9 makes an access.

Next, the operation of the semiconductor memory device according to the present embodiment (ie, the backup method) will be described with reference to the drawings. FIG. 2 is a timing chart showing an example of a change in the voltage value of the power supply voltage 15 in FIG.
The period indicated by corresponds to the setup, the period indicated by B corresponds to the normal operation, and the period indicated by C corresponds to the backup. Here, a case where an SRAM is used as the semiconductor memory for main storage 3 and an EEPROM is used as the semiconductor memory for backup 5 will be described.

(1) Normal operation (period B in FIG. 2) During this period, data is input / output between the outside of the semiconductor memory device and the SRAM.

That is, first, when the voltage value of the power supply voltage 15 is equal to or higher than a predetermined value, the power supply voltage detection circuit 7 outputs a detection signal 17 to the control circuit 9 to notify that there is no change in the power supply voltage 15. To the control circuit 9.

Next, the control circuit 9 receiving the detection signal 17
The control signal 21 disables the EEPROM (backup semiconductor memory) 5 and the control signal 25 disables the address value supply circuit 11.

On the other hand, at the same time, the selection signal 23 is supplied to the selection circuit 1
Output to 3. The selection circuit 13 having received the selection signal 23 selects the control signal 29 from the control signal 19 from the control circuit 9 and the control signal 29 from the external CPU or the like. Therefore, an external CPU or the like can directly access the SRAM (semiconductor storage memory for main storage) 3.

Then, address information is output via the address bus 27, and data is input / output between the outside and the SRAM 3 via the data bus 31.

In this normal operation, it is desirable to delete the data stored in the EEPROM 5 immediately after the setup described later is completed. I mean,
This is because it is usually necessary to perform writing after erasing data in the EEPROM 5 once.

FIG. 3 is a timing chart showing the operation of the semiconductor memory device according to the present embodiment in the normal operation described above. From time t1 to time t2, the SRA
Data is written to M3, and from time t1 to time t1.
In 2, data is read from the SRAM 3. The CE bar (SRAM) signal and the R / W bar (SRAM) signal are external control signals 29, the CE bar (EEPROM) signal and the WE bar (EEPROM) signal are control signals 21 from the control circuit 9, and ADDRESS is External address information and DATA are external and SRAM3
And the data exchanged between them.

(2) At the time of backup operation (period indicated by C in FIG. 2) In this period, when the voltage drops, the data stored in the SRAM is transferred to the EEPROM.

That is, first, when the voltage value of the power supply voltage 15 is equal to or less than the predetermined value, the power supply voltage detection circuit 7 notifies the control circuit 9 of the detection signal 17 indicating that the power supply voltage 15 has dropped.
To the control circuit 9.

Next, the control circuit 9 receiving the detection signal 17
Outputs a selection signal 23 to the selection circuit 13. Selection signal 2
The selection circuit 13 to which 3 has been input selects the control signal 19 from the control signal 19 from the control circuit 9 and the control signal 29 from the external CPU or the like. Therefore, the control circuit 9 controls the SRAM 3
Can be accessed directly.

On the other hand, at the same time, the control signal 21
The ROM 5 is stored in the address value supply circuit 1 by the control signal 25.
1 are both usable.

Next, the control circuit 9 sends S
The RAM 3 is set in a usable state.

Next, according to the address supplied from the address value supply circuit 11 via the address bus 27, the SRA
The data stored in M3 is transferred to EEPROM5.

When the address reaches a preset address, the address value supply circuit 11 outputs an address value supply end signal 33 to the control circuit 9. The control circuit 9 that has received the address value supply end signal 33 ends the transfer operation.

The address area set in the address value supply circuit 11 is set in advance by the user. Therefore, the user can freely determine in which area of the SRAM 3 the data stored in the SRAM 3 is backed up by the EEPROM 5 at the time of backup.

FIG. 4 is a timing chart showing the operation of the semiconductor memory device according to the present embodiment in the above-described backup operation. In each of the period from time t11 to time t12 and from time t12 to time t13, for example, data is transferred from the SRAM 3 to the EEPROM 5 every byte.
Has been transferred to. The CE bar (SRAM) signal and the R / W bar (SRAM) signal are the control signal 19 from the control circuit 9, and the CE bar (EEPROM) signal and the WE bar (EEPROM) signal are the control signal 2 from the control circuit 9.
1, ADDRESS is address information from the address value supply circuit 11, and DATA is from the SRAM 3 to the EEPROM 5.
Are respectively shown.

(3) During Setup (Period A in FIG. 2) In this period, the data backed up in the EEPROM is transferred to the SRAM when the voltage is turned on.

That is, first, when the voltage value of the power supply voltage 15 is equal to or higher than the predetermined value, the power supply voltage detection circuit 7 outputs a detection signal 17 to the control circuit 9 to notify that the power supply voltage 15 is turned on. To the control circuit 9.

Next, the control circuit 9 to which the detection signal 17 is input
Outputs a selection signal 23 to the selection circuit 13. Selection signal 2
The selection circuit 13 to which 3 has been input selects the control signal 19 from the control signal 19 from the control circuit 9 and the control signal 29 from the external CPU or the like. Therefore, the control circuit 9 controls the SRAM 3
Can be accessed directly.

On the other hand, at the same time, the control signal 21
The ROM 5 stores the address value supply circuit 1
1 are both usable.

Next, the control circuit 9 outputs S
The RAM 3 is set in a usable state.

Next, according to the address supplied from the address value supply circuit 11 via the address bus 27, the EEP
The data stored in the ROM 5 is transferred to the SRAM 3.

When the address reaches a preset address, the address value supply circuit 11 outputs an address value supply end signal 33 to the control circuit 9. The control circuit 9 that has received the address value supply end signal 33 ends the transfer operation.

FIG. 5 is a timing chart showing the operation of the semiconductor memory device according to the present embodiment in the set-up operation described above. Time t101 to time t10
2, and during each of the time periods t102 to t103, data is transferred from the EEPROM 5 to the SRAM 3 for each byte, for example. The CE bar (SRA
M) signal and R / W bar (SRAM) signal
, A CE bar (EEPROM) signal and a WE bar (EEPROM) signal are a control signal 21 from the control circuit 9, and ADDRESS is an address value supply circuit 11.
Address information and DATA from EEPROM5 to S
The data transferred to the RAM 3 is shown.

[0052]

As described above, according to the present invention, a volatile memory such as an SRAM is used as a semiconductor memory for main storage, and a nonvolatile memory such as an EEPROM is used as a semiconductor memory for backup. It is possible to provide a semiconductor memory device having both excellent characteristics of a volatile memory and a nonvolatile memory. That is, a volatile memory that can be written and read at high speed is used for the main storage semiconductor memory that exchanges data with the outside, and a semi-permanent backup semiconductor memory that backs up data when the power supply voltage drops. By using a non-volatile memory that can store data without power supply to
It is possible to provide a semiconductor memory device which can be written and read at high speed, has a long service life, and has high reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of a change in a voltage value of a power supply voltage 15 in FIG.

FIG. 3 is a timing chart showing an operation of the semiconductor memory device according to the present embodiment in a normal operation.

FIG. 4 is a timing chart showing an operation of the semiconductor memory device according to the present embodiment in a backup operation.

FIG. 5 is a timing chart showing an operation of the semiconductor memory device according to the present embodiment in a setup operation.

FIG. 6 is a block diagram showing a configuration example of a conventional semiconductor memory device having a backup function.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 101 Semiconductor storage device 3 Main storage semiconductor storage memory 5 Backup semiconductor storage memory 7, 105 Power supply voltage detection circuit 9, 107 Control circuit 11 Address value supply circuit 13 Selection circuit 15, 111 Power supply voltage 17, 113 Detection signal 19 , 21, 25, 29, 115 control signal 23 selection signal 27 address bus 31 data bus 33 address supply end signal 103 semiconductor memory 109 backup power supply 117 ground voltage 119 address bus 121 data bus

Claims (7)

[Claims] 1. A semiconductor memory device for storing various data, comprising: a first semiconductor memory for exchanging data with the outside; a second semiconductor memory for exchanging data with the first semiconductor memory. Wherein the data stored in the first semiconductor memory is transferred to the second semiconductor memory when the power supply voltage falls below a predetermined value. 2. A semiconductor memory device for storing various data, a power supply voltage detection circuit for detecting a power supply voltage, a control circuit for performing various controls, a main memory semiconductor memory for exchanging data with the outside, A backup semiconductor storage memory that exchanges data with the main storage semiconductor memory, and when the power supply voltage drops below a predetermined value, the power supply voltage detection circuit outputs a signal to the control circuit. And a control circuit to which the signal is inputted transfers data stored in the semiconductor memory for main storage to the semiconductor memory for backup. 3. The semiconductor memory device according to claim 2, further comprising an address value supply circuit for supplying address information for transferring data stored in said main storage semiconductor memory to said backup semiconductor storage memory. 3. The semiconductor memory device according to claim 2, wherein: 4. The semiconductor memory device according to claim 2, further comprising a selection circuit for selecting whether to access the semiconductor memory for main storage from outside or by the control circuit. Semiconductor storage device. 5. The semiconductor memory device according to claim 2, wherein said main memory semiconductor memory is a volatile memory. 6. The backup semiconductor memory is a non-volatile memory.
The semiconductor memory device according to claim 1. 7. A backup method of a semiconductor memory device for storing various data, wherein when a power supply voltage falls below a predetermined value, external access to the semiconductor memory for main memory is stopped. A method for backing up a semiconductor storage device, comprising transferring data stored in a backup semiconductor storage memory to a backup semiconductor storage memory and storing the data.