JPH11163118A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH11163118A
JPH11163118A JP32120397A JP32120397A JPH11163118A JP H11163118 A JPH11163118 A JP H11163118A JP 32120397 A JP32120397 A JP 32120397A JP 32120397 A JP32120397 A JP 32120397A JP H11163118 A JPH11163118 A JP H11163118A
Authority
JP
Japan
Prior art keywords
film
insulating film
silicon oxide
trench
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32120397A
Other languages
Japanese (ja)
Inventor
Kunihiro Kasai
邦弘 笠井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP32120397A priority Critical patent/JPH11163118A/en
Publication of JPH11163118A publication Critical patent/JPH11163118A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To form such an STI structure such that a plurality of insulating films are embedded in a trench and the trench section has no step in it. SOLUTION: After a trench has been formed into a semiconductor substrate 10, a first silicon oxide film 12 is formed halfway in the trench. Then a silicon nitride film 14 is formed on the surface of the silicon oxide film 12 and the remaining internal surface of the trench, and a second silicon oxide film 15 is formed so that the film 15 is embedded in the recessed section of the silicon nitride film 14. After the second silicon oxide film 15 has been formed, the surface of the substrate 10 is exposed by etching the silicon nitride film 14 by the use of the film 15 as a mask, and then the second silicon oxide film 15 is removed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、素子領域を分離す
るためのSTI(Shallow Trench Isolation)構造を具
備した半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device having an STI (Shallow Trench Isolation) structure for isolating an element region.

【0002】[0002]

【従来の技術】半導体に形成される素子を分離するため
にLOCOS構造の素子分離が用いられているが、その
素子分離領域の面積はチップの半分以上を占めている。
素子分離領域の面積を減らすために、専有面積の小さい
STI構造の採用が検討されている。
2. Description of the Related Art LOCOS element isolation is used to isolate elements formed in a semiconductor, and the area of the element isolation region occupies more than half of a chip.
In order to reduce the area of the element isolation region, adoption of an STI structure having a small occupied area has been studied.

【0003】STI構造は、基板の素子分離領域に形成
されたトレンチに絶縁膜を埋め込んで形成する。トレン
チ内に埋め込む絶縁膜としてシリコン酸化膜を用いる
が、通常の製造工程では保護膜としてシリコン酸化膜を
基板表面に形成しエッチングする工程が何度も行われる
ため、トレンチ内のシリコン酸化膜も同時にエッチング
されてしまい、膜減りが生じるという問題があった。
The STI structure is formed by embedding an insulating film in a trench formed in an element isolation region of a substrate. A silicon oxide film is used as an insulating film to be embedded in the trench. However, in a normal manufacturing process, a process of forming a silicon oxide film as a protective film on the substrate surface and etching the silicon oxide film many times is performed. There is a problem that the film is etched and the film is reduced.

【0004】トレンチ内のシリコン酸化膜の膜減りを防
ぐため、トレンチ内に複数層の絶縁膜を形成するSTI
構造の製造方法が、特開平8−227938号公報に開
示されている。このSTI構造の製造方法について図2
を参照して説明する。先ず、図2(a)に示すように、
半導体基板20の素子分離領域に形成されたトレンチの
途中までシリコン酸化膜21を埋め込み形成した後、全
面にシリコン窒化膜22を堆積する。そして、図2
(b)に示すように、CMP法でシリコン窒化膜22を
研磨して半導体基板20上のシリコン窒化膜を取り除
き、トレンチ内に複数層の絶縁膜を形成する。
[0004] In order to prevent the silicon oxide film in the trench from being reduced in thickness, an STI in which a plurality of insulating films are formed in the trench is formed.
A method of manufacturing the structure is disclosed in Japanese Patent Application Laid-Open No. 8-227938. FIG. 2 shows a method of manufacturing the STI structure.
This will be described with reference to FIG. First, as shown in FIG.
After a silicon oxide film 21 is buried and formed halfway in a trench formed in an element isolation region of a semiconductor substrate 20, a silicon nitride film 22 is deposited on the entire surface. And FIG.
As shown in (b), the silicon nitride film 22 is polished by the CMP method to remove the silicon nitride film on the semiconductor substrate 20, and a plurality of insulating films are formed in the trench.

【0005】この構造であれば、シリコン酸化膜からな
る保護膜のエッチング工程において、シリコン酸化膜を
選択的にエッチングすることにより、トレンチ内の最上
層に形成されたシリコン窒化膜がエッチングされず、ト
レンチ内の絶縁膜の膜減りが生じることがない。しか
し、素子分離領域の幅が大きい場合、CMP法を用いて
窒化シリコン膜を研磨する際に、ディッシングが起こり
段差が生じるという問題があった。
With this structure, the silicon oxide film is selectively etched in the step of etching the protective film made of the silicon oxide film, so that the silicon nitride film formed on the uppermost layer in the trench is not etched. There is no loss of the insulating film in the trench. However, when the width of the element isolation region is large, there is a problem that dishing occurs and a step occurs when the silicon nitride film is polished by the CMP method.

【0006】[0006]

【発明が解決しようとする課題】上記したように、トレ
ンチ内に複数層の絶縁膜が形成されたSTI構造を形成
する際、広い幅の素子分離領域の場合、最上層の絶縁膜
をCMP法を用いて研磨するとディッシングが起こり段
差が生じるという問題がある。本発明の目的は、複数層
の絶縁膜からなるSTI構造を形成する際、素子分離領
域で段差が生じることがない半導体装置の製造方法を提
供することにある。
As described above, when forming an STI structure in which a plurality of insulating films are formed in a trench, in the case of a device isolation region having a wide width, the uppermost insulating film is formed by a CMP method. There is a problem that dishing occurs when polishing is performed by using, and a step is generated. An object of the present invention is to provide a method of manufacturing a semiconductor device in which a step does not occur in an element isolation region when an STI structure including a plurality of insulating films is formed.

【0007】[0007]

【課題を解決するための手段】[構成]本発明は、上記
目的を達成するために以下のように構成されている。 (1) 本発明(請求項1)は、半導体基板に形成され
る素子を分離する素子分離領域を含む半導体装置の製造
方法であって、前記半導体基板に溝を形成する工程と、
前記半導体基板の溝の途中まで第1の絶縁膜を埋め込み
形成する工程と、前記半導体基板及び前記溝内の全面
に、該溝の上方に凹部を有する第2の絶縁膜を形成する
工程と、第2の絶縁膜の凹部内にストッパ膜を埋め込み
形成する工程と、前記ストッパ膜をマスクとして第2の
絶縁膜をエッチングし、前記半導体基板表面を露出させ
る工程と、前記ストッパ膜を除去する工程とを含むこと
を特徴とする。
Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) The present invention (Claim 1) is a method for manufacturing a semiconductor device including an element isolation region for isolating an element formed on a semiconductor substrate, the method comprising: forming a groove in the semiconductor substrate;
A step of burying and forming a first insulating film halfway in the groove of the semiconductor substrate, and a step of forming a second insulating film having a concave portion above the groove on the entire surface of the semiconductor substrate and the groove; Forming a stopper film in the recess of the second insulating film, etching the second insulating film using the stopper film as a mask, exposing the semiconductor substrate surface, and removing the stopper film And characterized in that:

【0008】本発明の好ましい実施態様を以下に示す。
凹部を有する第2の絶縁膜を全面に形成する工程におい
て、前記溝の底部の第2の絶縁膜の表面の高さが、前記
基板の表面とほぼ等しくなるように形成する。
A preferred embodiment of the present invention will be described below.
In the step of forming a second insulating film having a concave portion over the entire surface, the second insulating film is formed such that the height of the surface of the second insulating film at the bottom of the groove is substantially equal to the surface of the substrate.

【0009】前記第1の絶縁膜及び前記ストッパ膜がシ
リコン酸化膜であり、前記第2の絶縁膜がシリコン窒化
膜である。 [作用]トレンチ内の第1の絶縁膜上に凹部を有する第
2の絶縁膜を形成することによって、この凹部内にマス
クとなるストッパ膜を自己整合的に埋め込み形成するこ
とができる。そして、ストッパ膜をマスクとして、第2
の絶縁膜をエッチングすることによって、段差のないS
TI構造を形成することができる。
The first insulating film and the stopper film are silicon oxide films, and the second insulating film is a silicon nitride film. [Operation] By forming a second insulating film having a concave portion on the first insulating film in the trench, a stopper film serving as a mask can be buried in the concave portion in a self-aligned manner. Then, using the stopper film as a mask, the second
By etching the insulating film of step S
A TI structure can be formed.

【0010】[0010]

【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。図1は本発明の一実施形態に係わ
るSTI構造の製造工程を示す工程断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view showing a manufacturing process of an STI structure according to one embodiment of the present invention.

【0011】先ず、図1(a)に示すように、シリコン
基板10にトレンチを形成した後、熱酸化により露出す
るシリコン基板10の表面に薄い第1の熱酸化膜11を
形成する。次に、全面に化学気相成長法により第1のシ
リコン酸化膜(第1の絶縁膜)12を堆積する。その
後、第1の熱酸化膜11及び第1のシリコン酸化膜12
をエッチングし、シリコン酸化膜12をトレンチの途中
まで埋め込み形成する。この時、シリコン酸化膜12を
後に堆積するシリコン窒化膜の予定膜厚分だけ基板10
の表面より下げておく。
First, as shown in FIG. 1A, after a trench is formed in a silicon substrate 10, a thin first thermal oxide film 11 is formed on the surface of the silicon substrate 10 exposed by thermal oxidation. Next, a first silicon oxide film (first insulating film) 12 is deposited on the entire surface by a chemical vapor deposition method. Then, the first thermal oxide film 11 and the first silicon oxide film 12
Is etched, and a silicon oxide film 12 is buried partially in the trench. At this time, the silicon oxide film 12 is deposited on the substrate 10 by the predetermined thickness of the silicon nitride film to be deposited later.
Lower than the surface.

【0012】次いで、図1(b)に示すように、露出し
ている基板10の表面に熱酸化により薄い第2の熱酸化
膜13を形成した後、全面に化学気相成長法を用いてシ
リコン窒化膜(第2の絶縁膜)14を堆積する。このと
き、トレンチ内の第1シリコン酸化膜12の上方に凹部
が形成されるよう形成する。なお、トレンチ内のシリコ
ン窒化膜14の表面と基板10表面とが等しいことが望
ましいが、等しくなくとも良い。そして、全面に化学気
相成長法により第2のシリコン酸化膜(ストッパ膜)1
5を堆積する。
Next, as shown in FIG. 1B, after a thin second thermal oxide film 13 is formed on the exposed surface of the substrate 10 by thermal oxidation, the entire surface is formed by chemical vapor deposition. A silicon nitride film (second insulating film) 14 is deposited. At this time, the recess is formed above the first silicon oxide film 12 in the trench. It is desirable that the surface of the silicon nitride film 14 in the trench is equal to the surface of the substrate 10, but not necessarily. Then, a second silicon oxide film (stopper film) 1 is formed on the entire surface by a chemical vapor deposition method.
5 is deposited.

【0013】次いで、図1(c)に示すように、反応性
イオンエッチング、CMP法等を用い、シリコン窒化摸
14がエッチングされない条件で第2のシリコン酸化膜
15をエッチングし、第2のシリコン酸化膜15をシリ
コン窒化膜14の凹部に埋め込み形成する。この時、第
2のシリコン酸化膜15は、シリコン窒化膜14の表面
より多少オーバにエッチングされてもよく、後の工程で
マスクとして機能するだけ残っていれば良い。
Next, as shown in FIG. 1C, the second silicon oxide film 15 is etched using reactive ion etching, a CMP method or the like under conditions that the silicon nitride mask 14 is not etched. An oxide film 15 is buried in the recess of the silicon nitride film 14 and formed. At this time, the second silicon oxide film 15 may be etched slightly over the surface of the silicon nitride film 14, and it is sufficient that the second silicon oxide film 15 remains as a mask in a later step.

【0014】次いで、図1(d)に示すように、第2の
シリコン酸化膜15をマスクとして、シリコン窒化膜1
4をエッチングし、シリコン窒化膜14の表面が基板1
0表面とほぼ同じになるようにする。
Next, as shown in FIG. 1D, using the second silicon oxide film 15 as a mask, the silicon nitride film 1 is formed.
4 is etched so that the surface of the silicon nitride film 14 is
Make it almost the same as the zero surface.

【0015】次いで、図1(e)に示すように、ウェッ
トエッチング等を用いてマスク材として用いた第2のシ
リコン酸化膜15をエッチングする。以上説明したよう
に本実施形態によれば、素子分離領域のみに自己整合的
にシリコン窒化膜14を埋め込む事ができる。そして、
CMP法を用いていないので、ディッシングが起こら
ず、段差が生じることがない。
Next, as shown in FIG. 1E, the second silicon oxide film 15 used as a mask material is etched by wet etching or the like. As described above, according to the present embodiment, the silicon nitride film 14 can be embedded only in the element isolation region in a self-aligned manner. And
Since the CMP method is not used, dishing does not occur and no step occurs.

【0016】本発明は上記実施形態に限定されるもので
はない。例えば、第2の絶縁膜として、シリコン窒化膜
を以外の材料を用いることができる。また、上記実施形
態において、第1の絶縁膜とストッパ膜とは同一であっ
たが、異なる材料でも良い。また、ストッパ膜は、絶縁
物である必要はなく、第2の絶縁膜を選択的にエッチン
グする際にマスクとして働く材料であれば、導体又は半
導体を用いることが可能である。その他、本発明は、そ
の要旨を逸脱しない範囲で、種々変形して実施すること
が可能である。
The present invention is not limited to the above embodiment. For example, a material other than a silicon nitride film can be used for the second insulating film. In the above embodiment, the first insulating film and the stopper film are the same, but different materials may be used. Further, the stopper film does not need to be an insulator, and a conductor or a semiconductor can be used as long as the material functions as a mask when the second insulating film is selectively etched. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

【0017】[0017]

【発明の効果】以上説明したように本発明によれば、ト
レンチ内の第1の絶縁膜上に凹部を有する第2の絶縁膜
を、該凹部にストッパ膜を埋め込み形成し、該ストッパ
膜をマスクとして第2の絶縁膜をエッチングすることに
よって、段差のないSTI構造を形成することができ
る。また、マスクとなるストッパ膜は、第2の絶縁膜の
凹部に埋め込み形成することによって、リソグラフィ工
程を必要とせずに自己整合的に形成することができる。
As described above, according to the present invention, a second insulating film having a concave portion on a first insulating film in a trench is formed by embedding a stopper film in the concave portion, and the stopper film is formed. By etching the second insulating film as a mask, an STI structure without a step can be formed. Further, the stopper film serving as a mask can be formed in a self-aligned manner by burying the stopper film in the concave portion of the second insulating film without requiring a lithography step.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係わる半導体装置の製造
工程を示す工程断面図。
FIG. 1 is a process sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

【図2】従来のSTI構造の製造工程を示す工程断面
図。
FIG. 2 is a process cross-sectional view showing a manufacturing process of a conventional STI structure.

【符号の説明】[Explanation of symbols]

10…シリコン基板 11…第1の熱酸化膜 12…第1のシリコン酸化膜(第1の絶縁膜) 13…第2の熱酸化膜 14…シリコン窒化膜(第2の絶縁膜) 15…第2のシリコン酸化膜(ストッパ膜) DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11 ... 1st thermal oxide film 12 ... 1st silicon oxide film (1st insulating film) 13 ... 2nd thermal oxide film 14 ... Silicon nitride film (2nd insulating film) 15 ... 2 Silicon oxide film (stopper film)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に形成される素子を分離する素
子分離領域を含む半導体装置の製造方法であって、 前記半導体基板に溝を形成する工程と、 前記半導体基板の溝の途中まで第1の絶縁膜を埋め込み
形成する工程と、 前記半導体基板及び前記溝内の全面に、該溝の上方に凹
部を有する第2の絶縁膜を形成する工程と、 第2の絶縁膜の凹部内にストッパ膜を埋め込み形成する
工程と、 前記ストッパ膜をマスクとして第2の絶縁膜をエッチン
グし、前記半導体基板表面を露出させる工程と、 前記ストッパ膜を除去する工程とを含むことを特徴とす
る半導体装置の製造方法。
1. A method of manufacturing a semiconductor device including an element isolation region for isolating an element formed on a semiconductor substrate, comprising: forming a groove in the semiconductor substrate; Forming a second insulating film having a concave portion above the groove on the entire surface of the semiconductor substrate and the groove; and forming a stopper in the concave portion of the second insulating film. A semiconductor device comprising: a step of burying a film; a step of exposing a surface of the semiconductor substrate by etching a second insulating film using the stopper film as a mask; and a step of removing the stopper film. Manufacturing method.
【請求項2】第2の絶縁膜を形成する工程において、 前記溝の底部の第2の絶縁膜の表面の高さが、前記半導
体基板の表面とほぼ等しくなるよう形成することを特徴
とする請求項1に記載の半導体装置の製造方法。
2. The step of forming a second insulating film, wherein the height of the surface of the second insulating film at the bottom of the groove is substantially equal to the surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1.
【請求項3】第1の絶縁膜及び前記ストッパ膜がシリコ
ン酸化膜であり、第2の絶縁膜がシリコン窒化膜である
ことを特徴とする請求項1に記載の半導体装置の製造方
法。
3. The method according to claim 1, wherein the first insulating film and the stopper film are silicon oxide films, and the second insulating film is a silicon nitride film.
JP32120397A 1997-11-21 1997-11-21 Manufacture of semiconductor device Pending JPH11163118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32120397A JPH11163118A (en) 1997-11-21 1997-11-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32120397A JPH11163118A (en) 1997-11-21 1997-11-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11163118A true JPH11163118A (en) 1999-06-18

Family

ID=18129954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32120397A Pending JPH11163118A (en) 1997-11-21 1997-11-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11163118A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002095819A3 (en) * 2001-05-24 2003-11-20 Ibm Structure and method to preserve sti during etching
JP2006351694A (en) * 2005-06-14 2006-12-28 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2009518867A (en) * 2005-12-09 2009-05-07 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッド Insulating structure of semiconductor integrated circuit substrate and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002095819A3 (en) * 2001-05-24 2003-11-20 Ibm Structure and method to preserve sti during etching
JP2004527916A (en) * 2001-05-24 2004-09-09 インターナショナル・ビジネス・マシーンズ・コーポレーション Structure and method for retaining STI during etching
CN100343974C (en) * 2001-05-24 2007-10-17 国际商业机器公司 Structure and method to preserve STI during etching
JP2009094547A (en) * 2001-05-24 2009-04-30 Internatl Business Mach Corp <Ibm> Structure and method of preserving sti during etching
JP2010192919A (en) * 2001-05-24 2010-09-02 Internatl Business Mach Corp <Ibm> Method for protecting semiconductor shallow trench isolation (sti) oxide from etching
JP2006351694A (en) * 2005-06-14 2006-12-28 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2009518867A (en) * 2005-12-09 2009-05-07 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッド Insulating structure of semiconductor integrated circuit substrate and manufacturing method thereof
JP2015062239A (en) * 2005-12-09 2015-04-02 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッドAdvanced Analogic Technologies Incorporated Insulation structures for semiconductor integrated circuit substrates and methods of forming the same
JP2016164998A (en) * 2005-12-09 2016-09-08 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッドAdvanced Analogic Technologies Incorporated Insulation structure for semiconductor integrated circuit substrate and method of manufacturing the same

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