JPH1092952A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize memory cells effective for a highly integrated device by reducing the energy difference between the valence band top end of a second semiconductor layer and vacuum level below that between the valence band top end of a first and third semiconductor layers and vacuum level. SOLUTION: A main surface of a p-type Si substrate 1 is provided with a first p-type Si semiconductor layer 3 through a silicon oxide layer 2. On element-forming regions 21 on this layer 3 a second p-type SiGe semiconductor layer 4 and third p-type Si semiconductor layer 5 are formed. The energy difference between the valence band top end of the second semiconductor layer 4 and vacuum level is reduced below that between the valence band top end of the first and third semiconductor layers 3, 5 and vacuum level. Thus it is possible to easily realize memory cells effective for a highly integrated device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a DRAM type semiconductor memory device.

[0002]

2. Description of the Related Art Semiconductor memory devices are steadily increasing in integration and capacity. In particular, a DR in which a memory cell is constituted by one MOS transistor and one capacitor
The AM type semiconductor memory device has been most integrated because of its simple memory cell format.

In order to accurately read out a storage signal (information) while suppressing the influence of noise, it is necessary to make the amount of charge (stored charge) stored in a capacitor equal to or more than a certain value. .

Therefore, in order to further reduce the area of the memory cell and achieve higher integration, a capacitor having a large capacitance value capable of securing an accumulated charge amount equal to or more than a certain value even if the area of the memory cell is reduced. Required.

[0005] However, for this reason, it has been necessary to form a capacitor into a complicated three-dimensional shape or to newly develop an insulating film having a high dielectric constant as a capacitor insulating film, which has been a major obstacle to high integration.

It is effective to increase the power supply voltage in order to secure the accumulated charge amount. However, while the power supply voltage is lowered to reduce the power consumption, it is difficult to secure the accumulated charge amount by the power supply voltage. Have difficulty.

In order to solve these problems, some gain memory cells have been proposed in which a memory cell itself amplifies accumulated charges and supplies the charges from a power supply. However, these conventional gain memory cells are not practical because they complicate the transistor structure and cell operation.

In addition, one MO formed on the SOI substrate
A one-transistor cell using an S transistor as a memory cell has been proposed (M. Tack, M. Gao, Cla).
eyes and G. Declerck: IEEE T
transactions on Electron D
devices, ED-37 (1990) p. 1373
-1382).

In this one-transistor cell, the amount of majority carriers trapped in an electrically floating SOI substrate is used for a storage signal. The reading of the stored signal utilizes the fact that the threshold voltage of the MOS transistor changes due to the difference in the amount of majority carriers trapped in the SOI substrate.

However, the injection of majority carriers into the SOI substrate, that is, the writing of signal charges uses impact ions, so that the writing current is small,
It required a long writing time. Furthermore, since the majority carrier has insufficient holding characteristics, it has to be used at a low temperature of 77 K, which is not practical.

[0011]

As described above, one M
In a DRAM type semiconductor memory device in which a memory cell is constituted by an OS transistor and one capacitor, in order to further reduce the area of the memory cell and achieve higher integration, even if the area of the memory cell is reduced. In addition, a capacitor having a large capacitance value capable of securing an accumulated charge amount equal to or more than a certain value is required.

However, in order to increase the capacitance value, it is difficult to realize such a capacitor because it is necessary to form the capacitor into a complicated three-dimensional shape or to newly develop a capacitor insulating film having a high dielectric constant. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device having memory cells effective for high integration.

[0013]

[Means for Solving the Problems]

[Summary] In order to achieve the above object, in a semiconductor memory device according to the present invention (claim 1), a gate is connected to a word line, a source is connected to a bit line, a drain is connected to a power supply line, and a channel region is formed. A memory cell composed of an n-channel MOS transistor having a double hetero junction structure is integrated below. In the double hetero junction structure, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are arranged in this order. The energy difference between the upper end of the valence band of the second semiconductor layer and the vacuum level is the first semiconductor layer.
And a difference in energy between the upper end of the valence band of the third semiconductor layer and the vacuum level.

In another semiconductor memory device according to the present invention, a gate is connected to a word line, a source is connected to a bit line, a drain is connected to a power supply line, and a double heterojunction is provided below a channel region. P-channel MOS having structure
A memory cell composed of transistors is integrated, and the double heterojunction structure comprises a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer laminated in this order from the substrate side, Wherein the energy difference between the lower end of the conduction band of the semiconductor layer and the vacuum level is larger than the energy difference between the lower end of the conduction band of the first and third semiconductor layers and the vacuum level.

In another semiconductor memory device according to the present invention (claim 3), in the above-mentioned semiconductor memory device (claim 1, claim 2), the substrate comprises a substrate insulating layer and a substrate insulating layer. And the substrate semiconductor layer of the element formation region where the MOS transistor is formed is composed of the first, second and third semiconductor layers, and the substrate formation layer of the element formation region The thickness of the substrate semiconductor layer is such that, when the MOS transistor is in an ON state, the interface between the gate insulating film of the MOS transistor and the substrate semiconductor layer is different from the interface between the substrate insulating layer and the substrate semiconductor layer below the interface. The thickness is such that the region up to the interface is depleted,
The substrate semiconductor layer in the element isolation region sandwiched between the two MOS transistors is constituted by the first semiconductor layer;
The semiconductor substrate is characterized in that a substrate contact for applying an independent voltage is formed in units where two or more memory cells are formed.

In another semiconductor memory device according to the present invention, the substrate is constituted by a substrate insulating layer and a substrate semiconductor layer provided on a main surface of the substrate insulating layer. The substrate semiconductor layer in the element formation region where the MOS transistor is formed is composed of the first, second, and third semiconductor layers, and the thickness of the substrate semiconductor layer in the element formation region is such that the MOS transistor is turned on. In the state, the thickness from the interface between the gate insulating film of the MOS transistor and the substrate semiconductor layer to the interface below the interface between the substrate insulating layer and the substrate semiconductor layer is depleted, The first semiconductor layer exists in an element isolation region sandwiched between two memory cells sharing the same bit line, and an element isolation region sandwiched between two memory cells not sharing the same bit line exists in an element isolation region. Wherein the serial board semiconductor layer is not present.

In another semiconductor memory device according to the present invention (claim 5), in the semiconductor memory device (claims 1 to 4), the power supply line crosses the bit line and is the same. Is arranged between two adjacent word lines so as to be commonly used by two adjacent memory cells sharing the same bit line.

In another semiconductor memory device according to the present invention (claim 6), in the semiconductor memory device (claim 4), the power supply line crosses the bit line and the same bit line is connected. It is disposed between two adjacent word lines so as to be used in common by two adjacent memory cells that are shared, and the substrate semiconductor layer includes a unit in which a memory cell sharing the same bit line is formed. A substrate contact for applying an independent voltage to the substrate.

[Operation] The semiconductor memory device according to the present invention comprises:
Since the memory cell is constituted by one MOS transistor, higher integration is easier than in a conventional memory cell constituted by one MOS transistor and one capacitor.

The reason that a memory cell can be constituted by one MOS transistor is that a MOS transistor having a double heterojunction structure below a channel region is used.

When the amount of majority carriers on the substrate confined in the second semiconductor layer forming the double hetero junction structure changes, the threshold voltage of the MOS transistor also changes.
Therefore, when a gate voltage at an intermediate level between the threshold voltage when the number of confined majority carriers is large and the threshold voltage when the number of confined carriers is small is applied to the gate electrode, the trapped electrons are confined due to the magnitude of the drain current. It is possible to detect whether the amount of carriers is large or small, so that the amount of confined carriers can be used as a storage signal.

Further, since the double hetero junction structure can be constituted by a laminated structure of three semiconductor layers, the element structure is not particularly complicated. Further, since the drain of the MOS transistor is connected to the power supply line (conventionally, grounded via a capacitor), the storage signal read from the bit line is amplified by the amplification operation of the MOS transistor. Thereby, the influence of noise is suppressed, and the reading of the stored signal can be performed accurately.

[0023]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a memory cell of a DRAM device according to a first embodiment of the present invention. 2 and 3 show AA of the memory cell of FIG. 1, respectively.
断面 a sectional view and a BB sectional view.

This memory cell is a one-transistor cell including one n-channel MOS transistor formed on the SOI substrate, and is also a gain memory in which the memory cell itself amplifies a storage signal at the time of reading. The structure of this MOS transistor is characterized in that a double heterojunction structure is formed in the SOI substrate below the channel region. Hereinafter, the memory cell of the present embodiment will be described in detail.

In FIG. 1, reference numeral 1 denotes a p-type silicon substrate, and a p-type silicon layer 3 is provided on a main surface of the p-type silicon substrate 1 via a silicon oxide layer 2. P-type silicon layer 2 in element formation region (transistor region) 21
Reference numeral 1 denotes a projection on the surface of the p-type silicon layer 3 in the element isolation region 22.

On the p-type silicon layer 3 in the element forming region 21, a p-type silicon germanium layer 4 and a p-type silicon layer 5 are sequentially provided. High-concentration n-type drain diffusion layers 6 and n-type source diffusion layers 7 are selectively formed at both ends of the p-type silicon layer 5, respectively.

Here, the p-type silicon layer 3 and the p-type silicon germanium layer 4 form a hetero junction, and the p-type silicon germanium layer 4 and the p-type silicon layer 5 form a hetero junction. That is, the p-type silicon layer 3, the p-type silicon germanium layer 4, and the p-type silicon layer 5 form a double hetero junction structure.

When the SOI substrate is formed by the SIMOX method, the silicon oxide layer 2 becomes a buried silicon oxide layer, and the p-type silicon layer 3 and the p-type silicon substrate 1 are the same.

The element isolation insulating film 8 is formed in the element isolation region 22. When element isolation is performed using a groove in an SOI substrate, the silicon layer is not usually left on the element isolation region, but in the present embodiment, the silicon layer remains in the form of a recess in the p-type silicon layer 3.

This is because, in the present embodiment, the concave portion of the p-type silicon layer 3 is used as a substrate contact, and the voltage applied to the substrate contact is controlled to perform the writing operation of the storage signal at a high speed. .

The p-type silicon layer 3, the p-type silicon germanium layer 4, and the p-type silicon
When a positive voltage is applied to the gate electrode 10 to form an inversion layer, the thickness and the p-type impurity of the double heterojunction structure composed of the n-type silicon layer 5 are changed to the p-type silicon layer under the inversion layer (channel region). The depletion layer extending from the interface between the gate insulating film 9 and the gate insulating film 9 toward the interface between the silicon oxide layer 2 and the p-type silicon layer 3 under this interface has a sufficiently small value so as to reach the silicon oxide layer 2. Is set. It should be noted that this film thickness value is the same for each of the layers 2, 4,
5 depending on the p-type impurity concentration.

By setting such a film thickness, the MOS
When the transistor is on, p of element formation region 21
The type silicon layer 5 is surely separated from that of the element isolation region 22 by the depletion layer.

Further, when the MOS transistor is on, the double heterojunction is included in the depletion layer. Therefore, when the MOS transistor is on, the double heterojunction structure is affected. That is,
The threshold voltage changes depending on the amount of holes confined in the p-type silicon germanium layer 4.

A gate electrode 10 is provided on the p-type silicon layer 3 in a region sandwiched between the n-type drain diffusion layer 6 and the n-type source diffusion layer 7 with a gate insulating film 9 interposed therebetween. This gate electrode 10 is formed integrally with the word line WL.

The power supply line VL is connected to the n-type drain diffusion layer 6 through a contact hole 12 opened in the interlayer insulating film 11, and the n-type source diffusion layer 7 is opened in the interlayer insulating films 11 and 13. The bit line BL is connected via the contact hole 14.

FIG. 4 shows a band diagram of the n-channel MOS transistor of the present embodiment. This means that the gate voltage is 0
This is a state in which holes are not confined in the V and p-type silicon germanium layer 4 at all.

As shown in FIG., The double hetero junction in the valence band E _V are formed, confining holes which are majority carriers in the SOI substrate to p-type silicon germanium layer 4 between two heterojunctions be able to. In the present embodiment, the difference in the amount of holes confined in the p-type silicon germanium layer 4 (confined hole amount) is used for a storage signal (binary data).

Here, it is assumed that the state where no gate voltage is applied to the gate electrode 10 (equilibrium state) is changed to a state where an inversion layer is formed by applying a positive gate voltage to the gate electrode 10.

In this case, the p-type silicon germanium layer 4
Although the amount of the holes confined therein does not change, the surface potential decreases and an inversion layer is formed, but the decrease in the surface potential decreases as the amount of the confined holes decreases. The threshold voltage of a MOS transistor increases as the amount of confined holes decreases.

Therefore, an intermediate level voltage between the threshold voltage of the MOS transistor when the amount of confined holes is small and the threshold voltage of the MOS transistor when the amount of confined holes is large is applied to the gate electrode 10. If you apply
Drain current (readout current)
The ratio can be detected as a ratio, whereby the stored signal can be read.

Since the n-type drain diffusion layer 6 of the MOS transistor is connected to the power supply line VL,
When the transistor is in the ON state, a large read current can be obtained by the amplifying action of the MOS transistor.

As a result, it is possible to secure a high read current even when the power supply voltage is lowered, while being resistant to noise. Furthermore, even if the difference in the amount of confined holes is small, the MO
Due to the amplifying action of the S transistor, the small difference appears as a large drain current (read current) ratio. Therefore, the sense amplifier connected to the bit line can read the stored signal with high sensitivity and at high speed.

Since the memory cell is constituted by one MOS transistor, the memory cell is constituted by one MOS transistor.
Higher integration is easier than in a conventional device including a transistor and one capacitor.

As described above, in the present embodiment, the difference in the amount of confined holes is used for the storage signal. The specific form is as follows. One is a mode in which a state in which the amount of confined holes in an equilibrium state is finite and a state in which the amount of confined holes is zero are used for a storage signal. FIG. 5 shows a band diagram when a gate voltage is applied in these two states. From the figure, it can be seen that the threshold voltage is lower in the former case.

In this case, in order to write the storage signal corresponding to the former state, a substrate contact is formed on the SOI substrate as will be described later to maintain a balanced state, a zero voltage is applied to the substrate contact, and the storage corresponding to the latter state is performed. Signal writing is performed by applying a negative voltage to the substrate contact in order to draw holes in the p-type silicon germanium layer 4.

The retention time of the storage signal (data) is determined by the rate of holes generated in the p-type silicon germanium layer 4 and the amount of holes leaking out of the p-type silicon germanium layer 4 (leakage current). You.

The other is a mode in which a state in which the amount of confined holes is finite in an equilibrium state and a state in which the amount of confined holes is larger than this state are used for a storage signal. In this case, the writing of the storage signal corresponding to the former state is performed, for example, by injecting a zero voltage into the substrate contact to maintain the equilibrium state, and the writing of the storage signal corresponding to the latter state is performed by injecting holes into the p-type silicon germanium layer 4. This is done by applying a positive voltage to the substrate contact.

The retention time of the storage signal (data) is determined by the recombination rate of holes in the p-type silicon germanium layer 4 and the amount of holes leaking out of the p-type silicon germanium layer 4 (leakage current). Is done.

The state where the amount of confined holes is larger than the equilibrium state (excess state) and the state where the amount of confined holes is smaller than the equilibrium state (deficient state) are used for the storage signal.

In this case, the writing of the storage signal corresponding to the former state is performed by injecting holes into the p-type silicon germanium layer 4, for example, a positive voltage is applied to the substrate contact, and the writing of the storage signal corresponding to the latter state is performed. This is performed by applying a negative voltage to the substrate contact in order to extract holes in the p-type silicon germanium layer 4.

In each case, the ordinary DRAM
Like a cell, by refreshing a storage signal (data) at a timing shorter than the retention time,
The stored signal can be held for a long time.

When a storage signal (data) is held,
It is preferable to make the voltage of the bit line BL equal to that of the power supply line VL. Thereby, the flow of the hole current between the p-type silicon germanium layer 4 and the n-type source diffusion layer 7 can be sufficiently suppressed, and a longer retention time can be obtained.

As a method for erasing holes in the p-type silicon germanium layer 4, for example,
A voltage higher than the read voltage is applied to the holes to discharge holes in the p-type silicon germanium layer 4 out of the element through the substrate contacts. There is also a method in which a negative voltage is applied to the n-type source diffusion layer 7 so that holes in the p-type silicon germanium layer 4 are sucked out from the source side and discharged out of the element. This method can be used even when there is no substrate contact. Either method can erase holes at high speed.

FIG. 6 shows an example of a cell array layout (for one cell block). On the SOI substrate, element formation regions 21 of MOS transistors are arranged in a strip shape. Each of the element formation regions 21 is separated from each other by the trench groove. However, the p-type silicon layer 3 exists in the element formation region 21 and the element isolation region 22 as described above. That is, the convex portion of the p-type silicon layer 3 exists in the element formation region 21 and the concave portion (trench groove) of the p-type silicon layer 3
Exist in the element isolation region 22.

Word lines WL ₀ , WL ₁ , WL ₂ , WL ₃ ... Are arranged orthogonally to these element forming regions 21. Between word lines WL ₀ and WL ₁ , word lines WL ₂ ,
Power line VL is arranged so that each is between WL ₃ perpendicular to the element formation region 21. The bit lines WL ₀ , WL ₁ , WL ₂ , WL ₃
And the bit lines BL ₀ , BL orthogonal to the power supply line VL.
_1, BL _2, ... it is disposed.

That is, the power supply line VL is connected to the bit line BL
₀ , BL ₁ , BL ₂ ,... And are disposed between adjacent word lines so as to be commonly used by two adjacent memory cells sharing the same bit line.

The p-type silicon layer 3 in the element isolation region 22 is provided with a substrate contact 15 which is a region for contacting the substrate contact wiring SCL one by one for each cell block.

The substrate contact 15 is formed by forming an insulating film on the substrate and forming a contact hole in the insulating film. The substrate contact line SCL contacts the p-type silicon layer 3 in the element division region 22 through this contact hole.

The amount of confined holes can be controlled by adjusting the voltage of the substrate contact wiring SCL. Although only one substrate contact 15 is shown in the figure,
It may be several.

Since the number of the substrate contacts 15 may be one or several per cell block, the area of the substrate contact 15 occupying the cell block is small. Therefore,
The substrate contact 15 does not hinder high integration.

Assuming that the minimum processing line width is F, the area of the memory cell is 2F × 2F = 4F ² , as can be seen from FIG. 6, which is a half of that of a conventional ordinary DRAM cell (8F ² ).

The writing, holding and reading of the storage signals ("0", "1") using such a cell array are as follows. Here, the case where the confined hole amount is small is “0”, and the case where the confined hole amount is large is “1”.

For writing “1”, holes are injected only into the p-type silicon germanium layer 4 of the MOS transistor (selection MOS transistor) selected via the substrate contact 15 by applying a positive voltage to the substrate contact wiring SCL. It does by doing.

Here, the selection of the MOS transistor is as follows. A voltage of 0 V is applied to a word line (selected word line) to which the selected MOS transistor is connected, and a positive voltage of a level at which an inversion layer is formed is applied to word lines other than the selected word line (non-selected word lines).

When the inversion layer is formed, the p-type silicon layer 5
From the interface between the gate insulating film 9 and the silicon oxide layer 2
The depletion layer extending toward the interface with the type silicon layer 3 reaches the silicon oxide layer 2, whereby the MOS transistor connected to the unselected word line and the MOS transistor connected to the selected word line are electrically connected. Separated. In other words, only the MOS transistor connected to the selected word line is electrically connected to substrate contact 15.

As for the bit line, the voltage of the bit line (selected bit line) to which the selection MOS transistor is connected is set to 0 V, and holes are effectively injected from the substrate contact 15 into the p-type silicon germanium layer 4. To be done.

Before the voltage is set to 0 V, the voltage is set to the same level as that of the power supply line in order to hold a memory signal, a depletion layer extends from the n-type source diffusion layer 7 to the n-type drain diffusion layer 6, and p-type silicon germanium is formed. It is difficult to effectively inject holes into the layer 4.

Therefore, the voltage of the selected bit line is set to 0 V, the depletion layer extending from the n-type source diffusion layer 7 to the n-type drain diffusion layer 6 is reduced, and effective hole injection is realized. I do.

On the other hand, the voltage of the bit line (non-selected bit line) of the MOS transistor connected to the selected word line other than the selected bit line is reduced by the depletion layer extending from n-type source diffusion layer 7 and the n-type drain diffusion layer 6. And a p-type silicon germanium layer 4 is connected to the substrate contact 1.
5 is set to a level that is electrically separated from 5.

As a result, the MO connected to the selected bit line
The S transistor and the MOS transistor connected to the unselected bit line are electrically separated, and only the selected MOS transistor is connected to the substrate contact 15.
Therefore, holes can be injected only into the p-type silicon germanium layer 4 of the select MOS transistor.

On the other hand, writing of “0” is performed by discharging holes in the p-type silicon germanium layer 4 of the select MOS transistor (memory cell) through the substrate contact 15 to the outside of the element.

Specifically, only the voltage of the selected bit line is 0V
To release the holding state of only the MOS transistor connected to the selected bit line, and set only the voltage of the selected word line to a higher level (higher boot voltage) than the power supply line VL.

As a result, only the holes in the p-type silicon germanium layer 4 of the selected MOS transistor are discharged out of the element via the substrate contact 15. In addition, when reading the storage signal, the voltage of the selected bit line is 0 V, the voltage of the selected word line is confined, the threshold voltage of the MOS transistor when the amount of holes is small, and the voltage of the MOS transistor when the amount of confined holes is large. This is performed by setting the level to an intermediate level between the threshold voltage.

For holding the storage signal, the voltage of the word line is set to 0 V, and the voltage of the bit line is set to the same level as the power supply line VL. FIG. 7 shows a layout of another cell array.

The previous cell array in FIG. 6 is an example in which substrate contacts 15 are provided in units of cell blocks. In this cell array, memory cells are formed in units of bit lines, that is, memory cells sharing the same bit line. This is an example in which a substrate contact 15 is provided for each element forming region.

Here, the p-type silicon layer 3 is formed in the element isolation region between the two memory cells sharing the same bit line as before, but the same bit line is not shared. No p-type silicon layer 3 is formed in the element isolation region sandwiched between two memory cells.

As described above, as a result of providing the substrate contact 15 for each bit line, the area of the memory cell becomes 6F ² cells, which is larger than that of FIG. 6 (4F ² cells). However, when writing “1”, instead of the bit line selection operation, a simple operation of applying a positive voltage only to the substrate contact 15 provided on the selected bit line is performed.
The MOS transistor connected to the selected bit line and the MOS transistor connected to the non-selected bit line can be electrically separated.

On the other hand, when "0" is written, a simple operation of applying 0 V (ground voltage) only to the substrate contact 15 provided on the selected bit line instead of the bit line selecting operation is performed. The MOS transistor connected to the non-selected bit line can be electrically separated from the MOS transistor connected to the non-selected bit line.

As another layout of the cell array, the p-type silicon layer 3 is not formed also in the element isolation region sandwiched by two memory cells sharing the same bit line, and the substrate contact is made in units of memory cells. 15 is provided. In this case, the area is further increased.
Writing a storage signal to the OS transistor only requires controlling the voltage applied to the substrate contact 15, so that the writing operation becomes extremely easy.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the substrate contact is used to control the amount of confined holes, but the substrate contact is not used. A method may be used.

Specifically, the amount of confined holes is increased by an interband tunnel current from the n-type drain diffusion layer 6 and holes generated by impact ionization of hot electrons.

To generate an inter-band tunnel current,
For example, by setting the gate voltage to 0 V, the n-type drain diffusion layer 6
To apply a high positive bias. In order to generate holes by impact ionization, for example, a voltage higher than the drain voltage at the time of reading a storage signal is applied to the n-type drain diffusion layer 6, and a voltage approximately half the drain voltage is applied to the gate. Thus, it can be generated effectively.

In order to reduce the amount of confined holes, a forward bias is applied to the n-type source diffusion layer 7 to inject electrons in the p-type silicon germanium layer 4 to neutralize them.

In the above embodiment, the case where an n-channel MOS transistor is used as a memory cell has been described. However, the present invention can be applied to a p-channel MOS transistor.

In this case, since the majority carriers of the SOI substrate become electrons, it is necessary to form a double heterojunction structure capable of confining the electrons below the channel region by using three p-type semiconductor layers.

That is, as shown in FIG. 8, the energy difference between the lower ends of the conduction bands of the upper and lower p-type semiconductor layers 3p and 5p and the vacuum level is caused by the intermediate p-type semiconductor layer 4p that confines electrons.
Must be larger than the energy difference between the lower end of the conduction band and the vacuum level.

As a double hetero junction capable of confining electrons, for example, p-SiC / p-Si / p-
SiC, p-Si / p-SiGe / p-SiC, p-S
i / p-SiGeC / p-Si, p-SiC / p-Si
Ge / p-SiC, p-GaAs / p-Si / p-Ga
As, p-GaAs / p-Ge / p-GaAs, p-
a: Si / p-Si / pa: Si (amorphous S
i) and the like.

On the other hand, as a double hetero junction capable of confining holes, other than those described in the above embodiment, for example, n-SiGe / n-Si / n-SiGe,
n-SiC / n-Si / n-SiC, n-SiGe / n
-Si / n-SiC, n-SiC / n-SiGe / n-
SiC, n-GaAs / n-Si / n-GaAs, n-
GaAs / n-Ge / n-GaAs, na: Si / n
-Si / na: Si and the like.

Further, a heterojunction may be formed below the channel region in addition to the double heterojunction structure described above. For example, two double hetero junction structures may be formed below the channel region. In addition, various modifications can be made without departing from the scope of the present invention.

[0090]

As described in detail above, according to the present invention, by using a memory cell as a MOS transistor having a double heterojunction structure below a channel region, a semiconductor memory device with high integration can be realized. become.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell of a DRAM device according to a first embodiment of the present invention.

2 is a sectional view of the memory cell of FIG. 1 taken along the line AA ';

FIG. 3 is a sectional view taken along line BB of the memory cell of FIG. 1;

4 is an n-channel MOS constituting the memory cell of FIG.
Transistor band diagram

5 is an n-channel MOS constituting the memory cell of FIG.
Band diagram showing change in threshold voltage due to difference in hole amount in double heterojunction structure of transistor

FIG. 6 is a diagram showing a layout of a cell array;

FIG. 7 is a diagram showing a layout of another cell array;

FIG. 8 is a band diagram of a p-channel MOS transistor having a double heterojunction below a channel region for describing a modification of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... silicon oxide layer (substrate insulating layer) 3 ... p-type silicon layer (substrate semiconductor layer, 1st semiconductor layer) 4 ... p-type silicon germanium layer (substrate semiconductor layer, 2nd)
5 ... p-type silicon layer (substrate semiconductor layer, third semiconductor layer) 6 ... n-type drain diffusion layer 7 ... n-type source diffusion layer 8 ... element isolation insulating film 9 ... gate insulating film 10 ... gate electrode DESCRIPTION OF SYMBOLS 11 ... Interlayer insulating film 12 ... Contact hole 13 ... Interlayer insulating film 14 ... Contact hole 15 ... Substrate contact 21 ... Element formation area 22 ... Element isolation area

Claims (6)

[Claims] A gate connected to a word line, a source connected to a bit line, and a drain connected to a power supply line on a main surface of the substrate;
A memory cell comprising an n-channel MOS transistor having a double hetero junction structure is integrated below a channel region. The double hetero junction structure has a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The energy difference between the upper end of the valence band of the second semiconductor layer and the vacuum level is lower than the upper end of the valence band of the first and third semiconductor layers by the vacuum level. A semiconductor memory device which is smaller than an energy difference between the two. A gate connected to a word line, a source connected to a bit line, and a drain connected to a power supply line on a main surface of the substrate;
A memory cell composed of a p-channel MOS transistor having a double hetero junction structure is integrated below a channel region. The double hetero junction structure has a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The energy difference between the bottom of the conduction band of the second semiconductor layer and the vacuum level is lower than the bottom of the conduction band of the first and third semiconductor layers and the vacuum level. A semiconductor memory device having a larger energy difference. 3. The substrate comprises: a substrate insulating layer; and a substrate semiconductor layer provided on a main surface of the substrate insulating layer. The substrate semiconductor layer in an element forming region where the MOS transistor is formed is When the MOS transistor is in an ON state, the thickness of the substrate semiconductor layer in the element formation region is equal to the gate insulating film of the MOS transistor and the substrate semiconductor layer. A region from an interface with a layer to an interface between the substrate insulating layer and the substrate semiconductor layer below the interface is depleted, and the substrate semiconductor in an element isolation region sandwiched between the two MOS transistors A layer is composed of the first semiconductor layer, and a substrate contact for applying an independent voltage is formed in the substrate semiconductor layer in a unit where two or more memory cells are formed. It is a semiconductor memory device according to claim 1 or claim 2, characterized in. 4. The substrate includes a substrate insulating layer and a substrate semiconductor layer provided on a main surface of the substrate insulating layer. The substrate semiconductor layer in an element formation region where the MOS transistor is formed is When the MOS transistor is in an ON state, the thickness of the substrate semiconductor layer in the element formation region is equal to the gate insulating film of the MOS transistor and the substrate semiconductor layer. A region from an interface with a layer to an interface between the substrate insulating layer and the substrate semiconductor layer below the interface, the element being sandwiched between two memory cells sharing the same bit line 2. The semiconductor device according to claim 1, wherein the first semiconductor layer exists in an isolation region, and the substrate semiconductor layer does not exist in an element isolation region sandwiched between two memory cells not sharing the same bit line. Or a semiconductor memory device according to claim 2. 5. The power supply line is provided between two adjacent word lines so as to be commonly used by two adjacent memory cells that cross the bit line and share the same bit line. The semiconductor memory device according to claim 1, wherein: 6. The power supply line is disposed between two adjacent word lines so as to be commonly used by two adjacent memory cells that cross the bit line and share the same bit line. 5. The substrate semiconductor layer according to claim 4, wherein a substrate contact for applying an independent voltage is formed in a portion where the memory cell sharing the same bit line is formed in the substrate semiconductor layer. Semiconductor storage device.