JPH1083677A - Semiconductor memory and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive rationalization of activating timing margin of a sense amplifier. SOLUTION: This device is provided with a detecting means 10 detecting dispersion of process of a delay time in a delay stage, and a delay time correcting means 11 correcting a delay time of a clock in the delay stage based on a detected result of the detecting means 10, and rationalization of activating timing margin of the sense amplifier is achieved by correcting a delay time of a clock in the delay stage based on the detected result of the detecting means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Further, the present invention relates to a technique for generating a sense amplifier activation signal for activating a sense amplifier included therein, and for example, to a technique effective when applied to a static random access memory (SRAM) operated in synchronization with a clock.

[0002]

2. Description of the Related Art For example, in an SRAM in which a plurality of static memory cells are arranged in a matrix, a selection terminal of a memory cell is connected to a word line for each row direction.
Data input / output terminals of the memory cells are coupled to complementary data lines (also referred to as complementary bit lines) for each column direction. Each complementary data line is commonly connected to a complementary common line via a Y selection switch circuit including a plurality of column selection switches coupled one-to-one to the complementary data lines.

As an example of a document describing an SRAM, there is an "LSI Handbook (p.500-)" issued by Ohmsha on November 30, 1984.

[0004]

SUMMARY OF THE INVENTION In an SRAM,
When the complementary level input signal input to the sense amplifier reaches a predetermined level difference, the sense amplifier is activated to amplify the memory cell data.

In such a semiconductor memory, the operation of the timing generation device may be accelerated due to process variations. In such a case, the sense amplifier is activated before the signal level difference of the complementary common line is sufficiently obtained. It may be converted. Then, since an undesired signal is amplified by the sense amplifier, erroneous data is easily output. For this reason, generally, even when the operation of the timing generation device becomes faster due to process variation, the activation timing of the sense amplifier is sufficiently delayed so that the undesired data is not amplified by the sense amplifier. In this case, a sufficient margin is provided for starting the operation of the sense amplifier.

However, if the margin of the activation timing of the sense amplifier is determined in consideration of the case where the operation of the timing generation device becomes faster due to the process variation, when the operation of the timing generation device is relatively slow due to the process variation. In this case, the activation timing of the sense amplifier is undesirably delayed as compared with the rise of the complementary common line. That is, although the complementary common line has already reached the level difference that can be amplified by the sense amplifier, the activation of the sense amplifier is undesirably delayed.
That situation occurs. Undesirably delaying the activation of the sense amplifier means that the external output of the memory cell data is delayed correspondingly, and as a result, the memory access time is prolonged.

As described above, the margin setting of the sense amplifier activation timing in consideration of the case where the operation of the timing generation system device is accelerated due to the process variation is performed when the operation of the timing generation system device is relatively slow due to the process variation. This leads to an increase in time.

An object of the present invention is to optimize a timing margin for activating a sense amplifier.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a memory cell array (15) in which a plurality of memory cells are arranged, a sense amplifier (19) for amplifying a read signal from a memory cell during an assert period of a sense amplifier activating signal, and a clock signal When a semiconductor memory device is configured to include a delay stage (12) for generating the sense amplifier activating signal by delaying the delay stage, detection means (10, 11) for detecting a process variation in the delay time of the delay stage ) And delay time correcting means (12) for correcting the clock delay time in the delay stage based on the detection result of the detecting means.

Also, a delay circuit (10) formed near the delay stage for delaying a clock signal, and a phase comparison between a clock input to the delay circuit and a clock output from the delay circuit. And a phase comparison circuit (11) for correcting the clock delay time in the delay stage based on the phase comparison result.

At this time, the delay stage comprises a first delay stage (INV1) for delaying the input clock signal, and a second delay means for delaying the clock signal by a delay time longer than the first delay stage. (INV2, INV3, INV
4) and MOS transistors (Q11, Q14, Q19, Q19) for selectively activating the first delay stage and the second delay stage based on the comparison result of the phase comparison circuit.
Q22).

According to the above-mentioned means, the delay time correcting means or the phase comparing circuit corrects the clock delay time in the delay stage based on the detection result of the detecting means or the output of the delay circuit. This achieves an appropriate timing margin for activating the sense amplifier.

[0015]

FIG. 8 shows a data processing apparatus to which a semiconductor memory device according to the present invention is applied.

The data processing device shown in FIG. 8 includes a microcomputer 31 and a microcomputer S via a system bus BUS.
DRAM (Synchronous Dynamic Random Access Memory) 32, SRAM (Static Random Access Memory) 33, ROM (Read Only Memory) 34, Peripheral Device Control Unit 35, Display Control Unit 3
6 and the like are connected to each other so as to be able to exchange signals, and are configured as a computer system that performs predetermined data processing according to a predetermined program. The microcomputer 31 is a logical core of the present system,
It mainly has functions such as address designation, information reading and writing, data operation, instruction sequence, acceptance of interrupt, activation of information exchange between a storage device and an input / output device, and the like.
The SDRAM 32, the SRAM 33, and the ROM 34
Is positioned as an internal storage device. SDRAM
32 stores various data, and ROM 34 stores a CPU.
The program required for calculation and control in 30 is stored. The SRAM 33 is used as a main memory, a cache memory, or the like, making use of the high-speed read / write operation. By the peripheral device control unit 35, the external storage device 3
8 and information input control from the keyboard 39 and the like. Further, under the control of the display control unit 36,
Information is displayed on the CRT display 40.

FIG. 9 shows a configuration example of the microcomputer 31.

As shown in FIG. 9, the microprocessor 1 is not particularly limited, but has a CPU (central processing unit).
53, built-in ROM (read only memory) 51,
It includes various functional blocks such as a built-in RAM (random access memory) 52, a timer 54, an interrupt controller 57, and first to ninth ports 41 to 49 for inputting and outputting various signals. It is commonly connected to the upper data bus DBUSU and the like, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Also, external terminals P10 to P17, P20 to P24, P30 to P37, P30 connected to a number of external terminals, for example, input / output terminals of the first to ninth ports 41 to 49.
40 to P47, P50 to P57, P60 to P63, P7
0 to P77, P80 to P87, P90 to P97, and the like.

The built-in ROM 51 is a program memory for storing a program to be executed by the CPU 53. Although not particularly limited, the upper data bus DBUSU and the lower data bus DBUS each having an 8-bit width are used.
By being coupled to the CPU 53 via L, 2-state memory access is enabled regardless of byte data or word data. Although not particularly limited, a mask ROM in which a program is written in a manufacturing process (photomask) is applied to the built-in ROM 51.

The built-in RAM 52 is, but not limited to, a synchronous static random access memory (referred to as "synchronous SRAM") that operates in synchronization with a clock generated inside the microcomputer 31. Although this synchronous SRAM is not particularly limited, the CPU 53 is connected to the upper data bus DBUSU and the lower data bus DB each having an 8-bit width.
By being connected via USL, byte data,
Regardless of word data, two-state memory access is enabled.

The timer 54 includes a watchdog timer,
16-bit free running timer, 8-bit timer,
Various timers such as a PWM (pulse width modulation) timer are included.

FIG. 1 shows a configuration example of the built-in RAM 52.

Reference numeral 15 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminals of the memory cells are connected to word lines in each row direction, and the data input / output terminals of the memory cells are complementary in each column direction. It is coupled to a bit line (also called a complementary data line). Each complementary bit line is commonly connected to a complementary common line via a column selection circuit 18 including a plurality of column selection switches coupled one-to-one to the complementary bit lines.

An address signal AX input from outside the built-in RAM 52 is transmitted to a row decoder (XDEC) 14 via a row address buffer (XBA) 13 arranged corresponding to the address signal AX. An address signal AY input from outside the built-in RAM 52 is transmitted to a column decoder (YDEC) 17 via a column address buffer (YBA) 16 arranged correspondingly.
The word line corresponding to the input address signal is driven to the selected level based on the decode output of row decoder 14. When a predetermined word line is driven, a memory cell connected to this word line is selected. Further, the column decoder 17 turns on the column selection switch corresponding to the address signal supplied thereto, and conducts to the selected complementary common line. At this time, the potential of the complementary common line is
The signal is amplified by the sense amplifier 19 and output to the outside of the built-in RAM 52 via the output circuit 20 at the subsequent stage. In addition, built-in R
When write data is transmitted from outside the AM 52 to the write amplifier 8 via the input circuit 9, the write amplifier 8 drives a complementary common line according to the write data, and thereby the complementary bit line selected by the address signal. , Charge information corresponding to the data is stored in a predetermined memory cell.

Since the built-in RAM 52 is of a clock synchronous type, the row address buffer 13, the row decoder 14,
The column address buffer 16, the column decoder 17, and the like are operated in synchronization with clocks CKA and CKB generated based on the clock ECK, respectively. Here, the clock ECK is a clock generated by the microcomputer 31.

In the sense amplifier 19, the sense amplifier activating signal SC * (* indicates low active or signal inversion) is asserted so as to reduce the power consumption of the built-in RAM 52 and prevent unnecessary data from being externally output. It is only activated when. In reading data from the memory cell array 15, it is necessary to adjust the activation timing of the sense amplifier so that the sense amplifier 19 is activated after the potential difference of the complementary bit line reaches a certain level due to the memory cell data. For such activation timing control, the sense amplifier activation signal SC * is generated by the variable delay stage 12 that delays the clock CKC. Sense amplifier activation signal SC
* Is basically formed by delaying the clock CKC, but the delay time of the delay stage that delays the clock CKC may be undesirably shortened due to process variations of the device. In such a case, In reading data from the memory cell array 15, the sense amplifier 19 may be activated before the potential difference between the complementary bit lines becomes a sufficient level difference. In order to eliminate such a situation, in the built-in RAM 52, the clock CKC is delayed to make the delay time of the delay stage for generating the sense amplifier activation signal SC * variable, and the phase comparison result between the clock CK1 and the clock CK2 is obtained. , The delay time of the variable delay stage 12 is controlled.
Here, the clock CK1 is the clock ECK itself taken from outside the built-in RAM 52.
K2 is the clock ECK in the delay circuit 10.
Is delayed by a predetermined period, for example, approximately one period. That is, the clock ECK is delayed by one cycle in the delay circuit 10, and then transmitted to the phase comparison circuit 11 as the clock CK2, and the clock CK1 (= ECK)
And the delay time of the variable delay circuit 12 is determined according to the result of the phase comparison.
The delay circuit 10 is formed as close to the variable delay stage 12 as possible so that the process variation of the timing generation system device constituting the delay circuit 10 is equivalent to that of the timing generation system device forming the variable delay stage 12. . That is, when the delay circuit 10 is formed in the vicinity of the variable delay stage 12, the deviation of the delay time from the design value due to the process variation similarly appears in both the delay circuit 10 and the variable delay stage 12. , The delay time in the delay circuit 10 is detected, and the clock delay time in the variable delay stage 12 is corrected based on the detection result.

For example, when there is almost no process variation of the timing generation system device, the delay circuit 1
The delay of the clock ECK at 0 is approximately one cycle of the clock ECK. That is, as shown in FIG. 6A, the clock CK2 is delayed by about one cycle from the clock CK1. In this case, the phase comparison circuit 11 treats the clocks CK1 and CK2 as having almost no phase difference, and the delay time of the clock CKC in the variable delay stage 12 is a standard value.

However, if the delay time of the variable delay stage 12 is shortened due to the process variation of the timing generation device, the delay time of the delay circuit 10 formed near the variable delay stage 12 is similarly reduced. Becomes shorter. For example, as shown in FIG. 6B, assuming that the phase of the clock CK2 is faster than the clock CK1 by Δt, such a process variation also occurs in a device forming the variable delay stage 12. Therefore, the output signal of the phase comparison circuit 11 controls the delay time in the variable delay stage 12 to be longer. In other words, even if the speed of the timing generation device forming the variable delay stage 12 is increased due to device process variation or the like, such an increase in the speed of the timing generation device also appears in the delay circuit 10, which is Detected as a phase difference by the phase comparison circuit 11;
By correcting the delay time in the variable delay stage 12 based on this, the activation timing of the sense amplifier 19 is optimized.

By optimizing the activation timing of the sense amplifier 19 irrespective of the process variation of the timing generation device, data read from the memory cell array 15 can be amplified at an appropriate timing. .

Next, a detailed configuration of each section will be described.

FIG. 2 shows a configuration example of the delay circuit 10.

As shown in FIG. 2, the delay circuit 10
Is formed by connecting an even number of inverters 21-1 to 21-n in series. The delay time in the delay circuit 10 is substantially determined by the number of stages of the inverters 21-1 to 21-n. The greater the number of serial stages of the inverters, the longer the delay time there. The delay time in the delay circuit 10 is not particularly limited, but is set to a length that delays the input clock ECK by approximately one cycle.

The sense amplifier 19 will be described.

The sense amplifier 19 selectively amplifies the memory cell data transmitted to the complementary bit line by selectively coupling the complementary bit line of the memory cell array 15 to the complementary common line by the column selection circuit 18. Consists of a sense amplifier unit. One sense amplifier unit corresponds to a pair of complementary common lines, and the total number of sense amplifier units corresponds to the number of complementary common line pairs. FIG. 3 shows a plurality of sense amplifier units corresponding to the complementary common lines CDL1 and CDL1 *.

Although one sense amplifier unit SA is not particularly limited, the p-channel type MOS transistor Q
3 and an n-channel MOS transistor Q4 connected in series, a first inverter, and a p-channel MOS transistor Q4.
A transistor Q5 and a second inverter formed by connecting an n-channel MOS transistor Q6 in series are connected in a loop. The gate electrodes of the MOS transistors Q3 and Q4 are coupled to the common line CDL1 * together with the drain electrodes of the MOS transistors Q5 and Q6. The gate electrodes of the MOS transistors Q5 and Q6 are M
The drain electrodes of the OS transistors Q3 and Q4 are coupled to the common line CDL1. MOS transistor Q
The source electrodes of the transistors Q3 and Q5 are coupled to the high potential power supply Vcc, and the source electrodes of the MOS transistors Q4 and Q6 are coupled to the low potential power supply Vss via an n-channel MOS transistor Q7 as a power switch. Sense amplifier activating signal SC * from variable delay stage 12 is supplied to n-channel type MOS transistor Q via inverter 21.
7, and when the sense amplifier activation signal SC * is asserted low, the gate electrode of the n-channel MOS transistor Q7 is set to high level, and this MOS transistor By turning on Q7, the sense amplifier unit SA is energized and the sense amplifier unit SA is activated. When the sense amplifier unit SA is activated, the p-channel MOS transistors Q1 and Q2 are turned off by the output signal of the inverter 21, and the complementary common line column selection circuit 18 is electrically disconnected. While the level difference between the complementary common lines CDL1 and CDL1 * is amplified by the sense amplifier unit SA, preparations for the next memory cell data read, such as precharge of the complementary common lines CDL1 and CDL1 *, are performed. The read data amplified by the sense amplifier unit SA is supplied to the inverters 22 and 23 and the inverter 2
The signal is transmitted to the output circuit 20 through the output circuits 4 and 25, respectively.

FIG. 4 shows a configuration example of the phase comparison circuit 11.

A flip-flop circuit FF1 is formed by the two-input NAND gates 61 and 62, and clocks CK1 and CK2 are input to the flip-flop circuit FF1. Output nodes of the NAND gates 61 and 62 are denoted by N11 and N12, respectively. Subsequent to the NAND gates 61 and 62, two-input NAND gates 70 and 71 for transmitting the logic of the nodes N11 and N12 to a subsequent circuit at a predetermined timing are arranged. Subsequent to the two-input NAND gates 70 and 71, the two-input NAND gate 72,
There is provided a flip-flop circuit FF2 formed by combining the flip-flop circuits 73 with each other. The phase comparison signal DC1 * is obtained from the output terminal of the NAND gate 72, and the phase comparison signal DC1 is obtained from the output terminal of the NAND gate 73.

A two-input NAND gate 63 for taking in the clocks CK1 and CK2 is provided. An output signal of the NAND gate 63 is transmitted to one input terminal of a NOR gate 69 via inverters 64 and 65 at the subsequent stage. , And transmitted to the other input terminal of NOR gate 69 via inverters 64-68. The above NAND gates 70 and 7
1 transmits the output signals of the nodes N11 and N12 to the subsequent circuit while the output signal of the NOR gate 69 is at the high level.

FIG. 7 shows a timing waveform of a main part in the circuit shown in FIG.

This timing waveform is obtained when the phase of the clock CK2 is slightly earlier than the design value due to the process variation of the timing generation device, that is, the devices forming the delay circuit 10 and the variable delay stage 12 are more than the design value. This shows a case in which it fluctuates in the fast direction.
In that case, focusing on the input signal of the flip-flop circuit FF1, the clock CK2 goes to the high level earlier than the clock CK1, so that the flip-flop circuit FF1 goes to the high level while the node N12 goes to the low level. Set.

On the other hand, in the NAND gate 63, the clock C
By obtaining the NAND logic of K1 and CK2, the node N13 is set to the low level during a period in which the clocks CK1 and CK2 are both at the high level. NOR gate 6
9 outputs a high level while both the output logic of the inverter 65 and the output logic of the inverter 68 are at the low level. When the NAND gates 70 and 71 are activated during the high-level output period, the nodes N11 and N11
The flip-flop circuit 2 is set based on the logic of N12. That is, the node N11 is at a high level,
When the node N12 is at the low level, the output of the NAND gate 70 is at the low level, and the output of the NAND gate 71 is at the high level. Is a low level.

In the case where there is almost no process variation of the timing generation system device and the clock CK2 is slightly delayed from the clock CK1 as shown in FIG. , The output DC1 * of the NAND gate 72 forming the flip-flop circuit FF2 is low, and the output DC1 of the NAND gate 73 is low.
A rectangular pulse whose 1 is at a high level is obtained.

The rectangular pulse (DC1, DC1 *) output from the flip-flop circuit FF2 is used for correcting the clock delay time by selecting the delay stage in the variable delay stage 12.

FIG. 5 shows a configuration example of the variable delay stage 12.

P-channel type MOS transistor Q12
And an n-channel type MOS transistor Q13 are connected in series to form an inverter INV1. To activate the inverter INV1, the p-channel type M transistor is activated.
A p-channel MOS transistor Q11 is provided between the OS transistor Q12 and the high potential side power supply Vcc,
An n-channel MOS transistor Q14 is provided between the n-channel MOS transistor Q13 and the low potential power supply Vss. The operation of the p-channel MOS transistor Q11 is controlled by the phase comparison signal DC1 *, and the operation of the n-channel MOS transistor Q14 is controlled by the phase comparison signal DC1. That is, when the phase comparison signal DC1 * is at a low level and the phase comparison signal DC1 is at a high level, the inverter INV1 is activated. When the inverter INV1 is activated, the clock CKC inverted by the inverter INV1 is used as the sense amplifier activation signal SC.

A p-channel MOS transistor Q15 and an n-channel MOS transistor Q16 are connected in series to form an inverter INV2, and a p-channel MOS transistor Q17 and an n-channel MOS transistor Q17 are connected.
An OS transistor Q18 is connected in series to form an inverter INV3, and a p-channel MOS transistor Q20 and an n-channel MOS transistor Q21
Are connected in series to form an inverter INV4.
In order to activate the inverter INV4, the p-channel MOS transistor Q20 and the high-potential-side power supply Vcc are used.
And a p-channel MOS transistor Q19 is provided between the n-channel MOS transistor Q20
An n-channel MOS transistor Q22 is provided between the low-potential-side power supply Vss. n-channel type MOS
The operation of the transistor Q19 is controlled by the phase comparison signal DC1, and the operation of the n-channel MOS transistor Q22 is controlled by the phase comparison signal DC1 *. When the phase comparison signal DC1 is at a low level and the phase comparison signal DC1 * is at a high level, the inverter INV4 is activated. When the inverter INV4 is activated, the clock CKC is output from the inverter INV2 and the inverter INV4.
3, and delayed by the inverter INV4, respectively, to become the sense amplifier activation signal SC.

With such a configuration, when there is almost no process variation in the timing generation device and the clock CK2 is slightly behind the clock CK1, the flip-flop circuit FF2 is formed correspondingly. A rectangular pulse is obtained such that the output DC1 * of the NAND gate 72 is low and the output DC1 of the NAND gate 73 is high.
When the inverter INV1 is selectively activated, the clock CKC delayed by the inverter INV1 is transmitted to the sense amplifier 19 as the sense amplifier activation signal SC.

The delay circuit 10 and the variable delay stage 1
2 when the devices forming the flip-flop circuit 2 vary in a direction faster than the design value, the output DC1 * of the NAND gate 72 forming the flip-flop circuit FF2 becomes high level, and the output DC1 of the NAND gate 73 becomes low level. In this case, the inverter INV4
Are selectively activated, the clock CKC
Is delayed by the three stages of the inverters INV2, INV3, and INV4, and transmitted to the sense amplifier 19 as the sense amplifier activation signal SC. The delay time at the three inverter stages is longer than the delay time at the one inverter stage. Therefore, the output signals (DC1, DC1) of the phase comparison circuit 11
1 *), the delay time of the clock CKC at the time of forming the sense amplifier activating signal SC is corrected, and the devices forming the delay circuit 10 and the variable delay stage 12 vary in a direction faster than the design value. In this case, the sense amplifier can be activated at an appropriate timing.

According to the above example, the following functions and effects can be obtained.

(1) Even when the speed of the timing generation device forming the variable delay stage 12 is increased due to process variation or the like, such an increase in the speed of the timing generation device also appears in the delay circuit 10, which is Since the phase difference is detected by the phase comparison circuit 11 and the delay time in the variable delay stage 12 is corrected based on the detected phase difference, the activation timing of the sense amplifier 19 is optimized regardless of the process variation of the device. By optimizing the activation timing of the sense amplifier 19 in this manner, data read from the memory cell array 15 can be amplified at an appropriate timing.

(2) Due to the effect of the above (1), even when the operation of the timing generation device is relatively slow due to process variations, the activation timing of the sense amplifier is undesirably delayed as compared with the rise of the complementary common line. Therefore, the speed of memory access can be increased.

(3) Due to the operation and effect (2), in the microcomputer 31 including the built-in RAM 52, the speed of accessing the built-in RAM 52 can be increased to speed up data processing.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, in the above example, the delay time is switched in the variable delay stage 12 in two stages, but three or more stages may be switched. Further, the number of inverter stages for obtaining the delay time can be appropriately changed.

In the above description, mainly the case where the invention made by the present inventor is applied to an SRAM on-chip in a microcomputer which is a field of application as the background has been described, but the present invention is not limited thereto. For example, the present invention can be applied to a semiconductor memory device formed as a single memory LSI.

The present invention can be applied on condition that at least a sense amplifier is included.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, there are provided detecting means for detecting a process variation in the delay time of the delay stage, and delay time correcting means for correcting the clock delay time in the delay stage based on the detection result of the detecting means. By correcting the clock delay time in the delay stage based on the detection result of the detection means, the activation timing margin of the sense amplifier can be optimized.

Further, a delay circuit formed near the delay stage for delaying a clock signal is compared with a clock input to the delay circuit and a clock output from the delay circuit. A phase comparison circuit for correcting the clock delay time in the delay stage based on the phase comparison result, and correcting the clock delay time in the delay stage based on the detection result of the detection means. The activation timing margin of the amplifier can be optimized.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor memory device according to the present invention;
It is a block diagram of RAM.

FIG. 2 is a block diagram illustrating a configuration example of a delay circuit included in the SRAM.

FIG. 3 is a circuit diagram illustrating a configuration example of a sense amplifier included in the SRAM.

FIG. 4 is a circuit diagram illustrating a configuration example of a phase comparison circuit included in the SRAM.

FIG. 5 is a circuit diagram illustrating a configuration example of a variable delay circuit included in the SRAM.

FIG. 6 is a timing chart of a clock input to the phase comparison circuit.

FIG. 7 is an operation timing chart of delay time correction in the SRAM.

FIG. 8 is a block diagram of an overall configuration example of a data processing device to which a microcomputer including the SRAM is applied.

FIG. 9 is a block diagram illustrating a configuration example of the microcomputer.

[Explanation of symbols]

 Reference Signs List 8 write amplifier 9 input circuit 10 delay circuit 11 phase comparison circuit 12 variable delay stage 13 row address buffer 14 row decoder 15 memory cell array 20 output circuit 31 microcomputer 52 built-in RAM 53 CPU INV1, INV2, INV3, INV4 inverters Q11, Q14, Q19, Q22 MOS transistor

Claims (5)

[Claims] A memory cell array having a plurality of memory cells arranged therein; a sense amplifier for amplifying a read signal from the memory cell during a sense amplifier activation signal assertion; A semiconductor memory device including a delay stage that generates an amplifier activation signal; a detection unit that detects a process variation in delay time of the delay stage; and a clock delay time in the delay stage based on a detection result of the detection unit. And a delay time correcting means for correcting the delay time. 2. A memory cell array in which a plurality of memory cells are arranged, a sense amplifier for amplifying a read signal from a memory cell during an assertion period of a sense amplifier activation signal, and a clock signal for delaying the sense signal. A semiconductor memory device including a delay stage for generating an activation signal for an amplifier, a delay circuit formed near the delay stage for delaying a clock signal, a clock input to the delay circuit, and the delay circuit And a delay time correcting means for correcting a clock delay time in the delay stage based on a result of the phase comparison. apparatus. 3. The delay stage comprises: a first delay stage for delaying an input clock signal; second delay means for delaying the clock signal by a delay time longer than the first delay stage; 3. The semiconductor memory device according to claim 2, further comprising: a MOS transistor for selectively activating said first delay stage and said second delay stage based on a comparison result of a comparison circuit. 4. A memory cell array in which a plurality of static memory cells are arranged, and a plurality of bit lines disposed in a preceding stage of the sense amplifier and coupled to the memory cells are selectively shared based on a column address. 4. The semiconductor memory device according to claim 1, further comprising: a column selecting circuit for coupling to a line. 5. A semiconductor integrated circuit in which the semiconductor memory device according to claim 1 and a central processing unit capable of accessing the same are formed on one semiconductor substrate.