JPH1079405A - Semiconductor device and electronic component mounting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique of semiconductor device, capable of preventing a package board of the semiconductor device in which a semiconductor chip mounted on the package board is prevented from warping through bumps. SOLUTION: A semiconductor device is formed by a package board 1 on which first and second semiconductor chips 3a and 3b, having predetermined circuit elements on it, are mounted on both sides of the board respectively. The first and semiconductor chips 3a and 3b are mounted opposite on the other side of the package board 1 and connected electrically to the wiring layer through the bump 4. A plurality of solder bumps 2 electrically connecting the first and second semiconductor chips 3a to the mounting board through the wiring layer is formed on the package board 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a semiconductor chip mounted on a package substrate via bumps.

[0002]

2. Description of the Related Art With the miniaturization and multi-functionality of electronic and information devices, semiconductor devices mounted thereon tend to be miniaturized and multi-pin. In response to such a tide, for example,
Published by the Industrial Research Institute, Inc., “Electronic Materials (April 1995)” (Issued April 1, 1995), mounting semiconductor chips on package substrates via bumps as described on pages 22-28. , CSP (Chip S
A semiconductor device called “ize package” is known.

In order to connect the semiconductor chip and the package substrate, the semiconductor device is put into a heat treatment furnace at about 250 ° C. to melt the bumps. After the bump is melted, it is cooled to room temperature.

[0004]

However, in the above-mentioned technique, since the coefficient of thermal expansion between the semiconductor chip and the package substrate has a large difference (semiconductor chip; 3 to 5 ppm / ° C.).
(Package substrate: 17 to 25 ppm / ° C), the package substrate warps during the cooling process. When the sealing resin is filled between the semiconductor chip and the package substrate, the phenomenon is more remarkable because the curing shrinkage of the sealing resin is added.

When such a semiconductor device is connected to a mounting substrate via solder bumps or the like, the height of the solder bumps located between the package substrate and the mounting substrate varies greatly due to warpage. For solder bumps with a low height, the package
There is a problem that the stress generated between the mounting substrates cannot be sufficiently reduced, and the connection reliability is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique capable of preventing warpage of a package substrate in a semiconductor device in which a semiconductor chip is mounted on a package substrate via bumps.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device of the present invention, the first and second semiconductor chips on which predetermined circuit elements are formed are mounted on each surface of the package substrate. The first and second semiconductor chips are mounted at opposing positions and are electrically connected to a wiring layer via bumps. A plurality of mounting connectors for electrically connecting the first and second semiconductor chips to the mounting substrate through a wiring layer are formed on the package substrate. In such a semiconductor device, the first semiconductor chip can be a CPU and the second semiconductor chip can be a memory controlled by the CPU.

A semiconductor device according to the present invention includes a semiconductor chip on which a predetermined circuit element is formed, and a plate material having the same or similar thermal expansion coefficient as the semiconductor chip mounted on each surface of the package substrate. is there. The semiconductor chip and the plate material are mounted at opposing positions, and the semiconductor chip is electrically connected to the wiring layer via bumps. A plurality of mounting connectors for electrically connecting the semiconductor chip and the mounting substrate through a wiring layer are formed on the package substrate. In this semiconductor device, a ceramic of boron nitride, aluminum nitride, silicon carbide, mullite or alumina can be used for the plate material.

Further, in the semiconductor device of the present invention, a semiconductor chip on which predetermined circuit elements are formed and a dummy chip are mounted on each surface of the package substrate. The semiconductor chip and the dummy chip are mounted at opposing positions, and the semiconductor chip is electrically connected to the wiring layer via bumps. A plurality of mounting connectors for electrically connecting the semiconductor chip and the mounting substrate through a wiring layer are formed on the package substrate.

In these semiconductor devices,
Forming a concave portion on at least one surface of the package substrate,
A semiconductor chip, a plate material, or a dummy chip may be mounted in a state of being fitted into the concave portion.

Further, the electronic component of the present invention is configured such that such a semiconductor device is mounted on a mounting substrate.

According to the above-described means, the stress that tends to warp the package substrate is canceled, and the warpage of the package substrate can be reduced. Further, if the two semiconductor chips are a combination of a CPU and a memory, the signal transmission path can be shortened and the speed of the semiconductor device can be increased.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows an example of an assembling process of the semiconductor device of FIG. 1 (a) to (d). FIG. 3 is a perspective view showing a state in which the semiconductor device of FIG. 1 is mounted on a mounting board.

The semiconductor device shown in FIG. 1 has a BGA (Ball Grid) which mounts the package substrate 1 on a mounting substrate 8 (FIG. 3) via solder bumps (mounting connection bodies) 2 arranged in an array on the back surface of the package substrate 1. Array) type semiconductor device,
For example, first and second semiconductor chips 3a and 3b on which predetermined circuit elements are formed are mounted on both surfaces of a package substrate 1 formed of an insulating member such as mullite ceramic and having a wiring layer formed thereon. Have been. Here, the first semiconductor chip 3a executes a necessary process in accordance with the read command by a CPU (Central Processing Uniform).
t—Central processing unit) and the second semiconductor chip 3
b is a memory controlled by the first semiconductor chip 3a which is a CPU. However, the mounting positions of the first semiconductor chip 3a and the second semiconductor chip 3b may be reversed, or a combination other than the CPU and the memory may be used. The mounting positions of the semiconductor chips 3a and 3b are opposite to each other with the package substrate 1 interposed therebetween, and are electrically connected to the wiring layers via the bumps 4, respectively. The package substrate 1 includes the following embodiments.
The bumps 4 for connecting the semiconductor chip 3a, 3b to the package substrate 1 are formed of, for example, Au (gold), Sn (tin) -Pb.
It is made of a (lead) alloy, an Ag (silver) -Sn alloy or the like.

The second semiconductor chip 3b is mounted in such a manner as to be fitted into the concave portion 1a formed on the back surface of the package substrate 1, and the protrusion amount thereof is set to be equal to or less than the solder bump 2. The connection of the solder bumps 2 and the mounting substrate 8 due to the interference of 3b is prevented. However, if such a situation does not occur even without the concave portion 1a, the concave portion 1a is not always necessary, and a concave portion is formed on the surface to mount the first semiconductor chip 3a therein. Alternatively, the height of the semiconductor device may be reduced.

Between the package substrate 1 and each of the semiconductor chips 3a and 3b mounted thereon, a sealing resin 5 generally used in the semiconductor field is filled to protect the bumps 4 from an external atmosphere. I have. However, a thermosetting resin such as an epoxy resin, a silicone resin, a polyimide resin, and a phenol resin is used alone or as a mixture of two or more kinds of the sealing resin 5, and a filler such as silica or alumina, a curing accelerator, a mold release agent is used. Agent, colorant, flame retardant, etc.
A resin that is liquid at room temperature can be filled with a resin by potting, or a solid that is heated and melted at room temperature can be injected with a resin by a transfer method.

The semiconductor device having such a configuration is assembled through a series of steps (a) to (d) shown in FIG.

First, as shown in FIG.
The first semiconductor chip 3a on which the wiring layer is formed is aligned with a predetermined position on the front surface of the package substrate 1 on which the wiring layer is formed (here, a position facing the concave portion 1a on the back surface), and the bump 4 is melted. Heating to a temperature of about 250 ° C. connects the electrode exposed from the wiring layer to the surface and the first semiconductor chip 3a. After connecting the two, the space between the first semiconductor chip 3a and the package substrate 1 is filled with a liquid sealing resin 5 and cured by heating (FIG. 2B).

Next, the above-mentioned steps (corresponding to FIGS. 2A and 2B) are repeated in the same manner as when the package substrate 1 is turned over and the first semiconductor chip 3a is connected, and the second surface is formed on the back surface. The semiconductor chip 3b is mounted. Note that a concave portion 1a is formed on the back surface of the package substrate 1, and the second semiconductor chip 3b is mounted so as to be fitted into the concave portion 1a.

As shown in FIG. 2C, the first and second semiconductor chips 3 are provided on both sides of the package substrate 1.
After the connection of a and 3b, the solder bumps 2 are provided on the back surface of the package substrate 1, which is the connection surface with the mounting substrate 8.

The semiconductor device thus manufactured is
The electrodes of the wirings 8a formed on the mounting board 8 are electrically and mechanically connected to the corresponding bumps, and are surface-mounted on the mounting board 8 as shown in FIG. This allows
It constitutes a part of an electronic component including the mounting board 8 and a large number of semiconductor devices. By being mounted on a predetermined device in units of electronic components, signals are exchanged with another semiconductor device.

As described above, in the semiconductor device of the present embodiment, the first and second semiconductor chips 3a, 3 having the same thermal expansion coefficient are provided at opposing positions on both surfaces of the package substrate 1.
b, the stress that tends to warp the package substrate 1 due to the difference in the coefficient of thermal expansion between the package substrate 1 and the semiconductor chips 3a and 3b and the curing shrinkage of the sealing resin 5 is canceled out. Warpage can be reduced. Thereby, when the semiconductor device is connected to the mounting substrate 8, the heights of the solder bumps 2 are all the same, and the connection reliability of the device can be improved.

The two semiconductor chips 3 mounted
By using a and 3b as a combination of a CPU and a memory, the signal transmission path is shortened due to the proximity arrangement, the signal delay is reduced, and the speed of the semiconductor device can be increased.

(Embodiment 2) FIG. 4 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

In the semiconductor device according to the present embodiment, a semiconductor chip 3 on which a circuit element is formed is mounted on a surface of a package substrate 1 by being connected to a wiring layer via bumps 4, and a back surface position facing the semiconductor chip 3 is mounted. Plate material 6
Is attached. This plate material 6 is 3-5p
The semiconductor chip 3 is made of a material such as boron nitride, aluminum nitride, silicon carbide, mullite or alumina ceramic which has the same or approximate thermal expansion coefficient as pm / ° C. However, members other than those described above can be appropriately used as long as they have a coefficient of thermal expansion of 10 ppm / ° C. or less. The mounting positions of the semiconductor chip 3 and the plate member 6 may be reversed.

The assembly of the semiconductor device of the present embodiment is similar to that of the semiconductor device described in the first embodiment, that is, the semiconductor chip 3 and the package substrate 1 are heated to , The plate material 6 is mounted on the concave portion 1a, and finally the solder bump 2 is provided.

Also in the semiconductor device of the present embodiment, since the semiconductor chip 3 and the plate member 6 having substantially the same thermal expansion coefficient are mounted at opposing positions on both surfaces of the package substrate 1, the package substrate 1 Thus, the warping of the package substrate 1 can be reduced, and the connection reliability of the device can be improved.

(Embodiment 3) FIG. 5 is a sectional view showing a semiconductor device according to still another embodiment of the present invention.

In the semiconductor device according to the present embodiment, a semiconductor chip which is not electrically connected to the wiring layer of the package substrate 1 is used instead of the plate member of the second embodiment.
That is, the dummy chip 7 is mounted.

In the semiconductor device having such a structure,
Since the dummy chip 7 has the same coefficient of thermal expansion as the semiconductor chip 3, the warpage of the package substrate 1 is reduced, and the connection reliability of the device can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, although the semiconductor device described in the present embodiment uses a solder bump 2 as a mounting connector for a BGA, the present invention provides, for example, a PGA (Pin Grid Array) of a surface mounting type. ) Can be applied to various other semiconductor devices. In the case of PGA, a lead led out perpendicular to the back surface becomes a mounting connector.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) That is, according to the present invention, the difference in the coefficient of thermal expansion between the package substrate and the semiconductor chip and the stress that tends to warp the package substrate due to the curing and shrinkage of the sealing resin are canceled out. Warpage can be reduced. Therefore, when the semiconductor device is connected to the mounting substrate, the height of the solder bumps is the same in any part, and the connection reliability of the device can be improved.

(2) Further, by combining the two semiconductor chips mounted with a CPU and a memory, the signal transmission path is shortened, the signal delay is reduced, and the speed of the semiconductor device is increased. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention;

2 (a) to 2 (d) are explanatory diagrams successively showing one example of an assembling process of the semiconductor device of FIG. 1;

FIG. 3 is a perspective view showing the semiconductor device of FIG. 1 mounted on a mounting board.

FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 package substrate 1 a concave portion 2 solder bump (mounting connection body) 3 semiconductor chip 3 a first semiconductor chip 3 b second semiconductor chip 4 bump 5 sealing resin 6 plate material 7 dummy chip 8 mounting substrate 8 a wiring

Claims (7)

[Claims] 1. A first and second semiconductor chip on which a predetermined circuit element is formed, and a wiring layer formed of an insulating member, wherein the first and second semiconductor chips are opposed to each other. A package substrate mounted on each surface via a bump and electrically connected to the wiring layer, and mounted on the package substrate and mounted on the first and second semiconductor chips through the wiring layer A semiconductor device, comprising: a plurality of mounting connectors that electrically connect to a substrate. 2. The semiconductor device according to claim 1, wherein said first semiconductor chip is a CPU, and said second semiconductor chip is a memory controlled by said CPU. 3. A semiconductor chip on which a predetermined circuit element is formed, and a wiring layer formed by an insulating member, wherein the semiconductor chip is electrically connected to the wiring layer via a bump. A package substrate mounted on one surface and having a thermal expansion coefficient identical or similar to that of the semiconductor chip mounted at a position opposite to the semiconductor chip on the other surface; and A semiconductor device comprising: a plurality of mounting connectors for electrically connecting the semiconductor chip to a mounting substrate through the semiconductor device. 4. The semiconductor device according to claim 3, wherein said plate material is a ceramic of boron nitride, aluminum nitride, silicon carbide, mullite or alumina. 5. A wiring layer comprising a semiconductor chip on which a predetermined circuit element is formed, and an insulating member, wherein the semiconductor chip is electrically connected to the wiring layer via a bump. A package substrate having a dummy chip mounted on one surface and not electrically connected to the wiring layer mounted at a position opposite to the semiconductor chip on the other surface; formed on the package substrate; A semiconductor device comprising a plurality of mounting connectors for electrically connecting a semiconductor chip and a mounting substrate. 6. The semiconductor device according to claim 1, wherein a concave portion is formed on at least one surface of the package substrate, and wherein the semiconductor chip, the plate member, or the dummy chip has a concave shape. A semiconductor device, wherein the semiconductor device is mounted so as to be fitted into a part. 7. An electronic component, wherein the semiconductor device according to claim 1, 2, 3, 4, 5, or 6 is mounted on a mounting board.