JPH10333979A - Bank access control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the access efficiency to a main storage having plural banks. SOLUTION: A request buffer 1 stores a memory request of which access destination bank is busy or a memory request not matching a previously determined selecting condition. A bank busy counter 3 manages the busy states of the banks. A bank checking circuit 4 checks the busy states of access destination banks of a memory request stored in the buffer 1 by prescribed fixed cycle and a newly received memory request by referring to the counter 3. A request selection circuit 5 selects a memory request matched with the selecting condition out of memory requests of which access destination banks checks by the circuit 4 are not busy and outputs the selected memory request to a memory control part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bank access control system, and more particularly to a bank access control system for a main memory interleaved in a plurality of banks.

[0002]

2. Description of the Related Art Conventionally, in an information processing system having a main memory interleaved in a plurality of banks, a bank access to the main memory is disclosed in JP-A-60-120.
There were two control schemes as detailed in 449.

FIGS. 6 (a) and 6 (b) are block diagrams of a bank access control system described in the publication.

In FIGS. 6A and 6B, reference numeral 20 denotes an access selection circuit, reference numeral 21 denotes a bank busy management unit,
Pn are pipelines, and ACC is an access request (memory request) to a plurality of banks.

The access selection circuit 20 is a circuit for selecting one ACC from a plurality of ACCs in accordance with predetermined selection conditions (guaranteed access order for the same bank, priority selection order among the banks, etc.). The bank busy management unit 21 manages the busy state of each bank, and is a circuit that permits only access to non-bank busy banks of the ACC. Also, P1, P2, ...
The pipeline composed of Pn is a circuit for guaranteeing a bank cycle from when access to a certain bank is started to when it is completed.

[0006] In the method of FIG.
Is input to the bank busy management unit 21 to select an ACC for a bank that is not bank busy, select one ACC that satisfies the selection condition from among them, and output it to the pipeline P1. At this time, the start signal ST
Is output to the main storage device, and bank access is started. The address at the time of bank access is the pipeline P
1, P2,... Pn, and the bank cycle ends when the address reaches the pipeline Pn.
When the bank cycle ends, the bank busy management unit 21 starts selecting the next ACC.

On the other hand, in the method shown in FIG. 6B, first, one ACC that satisfies the selection condition is selected from the plurality of ACCs by the access selection circuit 20 and output to the pipeline P1,
When the address reaches the pipeline Pn, that is, when the bank cycle ends, the bank busy management unit 21 determines whether the bank to be accessed is not busy, and if not busy, outputs a start signal ST to the main storage device. I do.

[0008]

In the conventional bank access control system described above, in both of the systems shown in FIGS. 6A and 6B, a start signal ST is output to the main storage device and a bank busy occurs. Until the busy of the memory request that has become bank busy is released, that is, until the bank cycle ends, the subsequent memory request is not output to the storage device regardless of whether it is bank busy or not, and the memory access efficiency is reduced. Had the drawback that it became worse.

SUMMARY OF THE INVENTION It is an object of the present invention to efficiently perform a bank check and a request check in a bank access control method for a main memory having a plurality of banks, improve the frequency of accessing a memory, and improve the memory access efficiency. It is in.

[0010]

According to a first aspect of the present invention, in a bank access control method for a main memory having a plurality of banks, a request buffer for storing a memory request whose access destination bank is busy is provided. Issuing, to the memory control unit, the memory request in which the access destination bank is no longer in a busy state among the memory requests stored in the request buffer and the newly received memory requests at a predetermined cycle. It is characterized by having done.

In a second aspect of the present invention, in a bank access control method for a main memory having a plurality of banks, a memory request which is busy or does not meet a predetermined selection condition is stored in an access destination bank. A request buffer and a bank busy counter for managing a busy state of the bank, and a busy state of a bank to which the memory request stored in the request buffer and a newly received memory request are accessed at a predetermined cycle. A bank check circuit for checking by referring to the bank busy counter; and selecting a memory request that meets the selection condition from among memory requests in which the access destination bank checked by the bank check circuit is not in a busy state. Issue to control Characterized in that it comprises a request selection circuit.

A third invention is characterized in that in the first and second inventions, the predetermined cycle is a clock cycle.

According to a fourth aspect of the present invention, in the second aspect, the bank busy counter starts counting when the memory request is issued to the bank and enters a busy state, and resets the counter when a predetermined value is reached. By doing so, the busy state of the bank is released.

According to a fifth aspect of the present invention, the selection condition in the second aspect is such that the memory request stored in the request buffer and the newly received memory request have a priority, and the highest priority is given to the memory request. A memory request is selected.

[Operation] In a bank access control method for a main memory having a plurality of banks, a request buffer for storing a memory request which is busy or does not meet a predetermined selection condition and a bank to be accessed are provided. A bank busy counter for managing the busy state of the memory request, and refer to the bank busy counter for the busy state of the access destination bank of the memory request stored in the request buffer and the newly received memory request at a predetermined cycle. And selects a memory request that satisfies the above-described selection condition from among the memory requests in which the checked access destination bank is not busy, and issues the selected memory request to the memory control unit.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bank access control system according to the present invention, and FIG. 2 is a diagram showing the position of a bank check block 11 in a computer system which controls the bank access control system of the present invention. is there.

The outline of the present invention will be described with reference to FIGS. 1 and 2. The bank check circuit 4 and the request selection circuit 5 perform a bank check on a received memory request. When the access destination bank is not busy and satisfies the request selection condition (a condition predetermined by the system), the received memory request is output to the memory control unit 12, and the bank check is NG, that is, the received memory request is received. When the access destination bank of the memory request is bank busy or does not satisfy the request selection condition,
The received memory request is stored in the request buffer 1. The bank check is similarly performed for the subsequent memory requests. When the bank check is NG, the received memory request is stored in the request buffer 1, and when the bank check is OK, the received memory request is output to the memory control unit 12. Request buffer 1
When a plurality of memory requests with different access destination banks stored therein are simultaneously released from the bank busy, the plurality of memory requests are output to the memory control unit 12 every clock cycle in accordance with a predetermined priority.

Next, details of each block in FIG. 1 will be described.

The memory requests stored in the request buffer 1 are stored in the order of reception from word 00 to word n. For example, in the case where a memory request is stored in all words, the word 03
When the memory busy of the memory request is released,
In the next clock cycle, the memory requests of word 00, word 01 and word 02 are held as they are, word 03 is output to the memory control unit, and word 04 is output.
Through n are shifted right by one stage, and stored in words 03 through n-1. In this case, the signal for selecting the request of the word 03 is the request select signal 6. Also, to store bank busy memory requests in ascending order of word numbers,
When i requests are stored, the word 00
Is stored in the word i-1 from the beginning, and the memory request does not fall out in the middle of the word.

The bank busy counter 3 has a busy counter for each bank, decodes the access destination bank address 7 of the memory request issued to the memory control unit, and activates the bank busy counter corresponding to the access destination bank. , Count up every clock cycle,
When the bank busy counter is reset to a certain value (bank busy time) (so that it is possible to determine that the bank is not busy when the bank busy counter is reset), the bank busy information 8 of all banks is obtained. Generate and output

Next, the bank check circuit 4 will be described. FIG. 3 is a block diagram of the bank check circuit 4. The bank check circuit 4 inputs the bank busy information 8 from the bank busy counter 3 and the access destination bank address 9 of the received memory request and the memory request stored in each word of the request buffer 1 to obtain each access destination bank. By selecting the bank busy information 8 using the address as the select signal, the bank path information 10 indicating whether or not the access destination bank of all memory requests is busy is generated.

FIG. 4 is a block diagram of the request selection circuit 5. The request selection circuit 5 receives the bank path information of all the memory requests generated by the bank check circuit 4 and selects a memory request by giving priority to word 00, word 01,. Signal, request select 6
And issues the request selected by the request select 6 via the request selector 2 to the memory control unit.

FIG. 5 is a diagram showing an example of a timing chart when a memory request stored in word a accesses bank 0.

The access destination bank address stored in the word a from the request buffer 1 is input to the bank check circuit 4, and the word a pass information is generated from the busy information of the bank 0. A word a select signal is generated by the request selection circuit 5 from the word a pass information, and a request for the word a for accessing the bank 0 is sent to the memory control unit.

In the above-described embodiment, the request selection circuit 5 selects one of the bank path information generated by the bank check circuit 4 in accordance with the priority order, and receives the corresponding request via the request selector 2 into the memory control unit. In the bank path information generated by the bank check circuit 4, the bank path information to the same bank is selected according to the priority order, and the bank paths different from each other and not busy are transmitted to the request selector 2 via the request selector 2. A method of simultaneously outputting all the corresponding requests to the memory control unit is also conceivable.

[0027]

As described above, according to the present invention, when a bank busy occurs, this request is stored in the request buffer until the bank busy is released, and the access destination bank of the subsequent memory request is stored in the bank. By outputting the data to the memory control unit when it is not busy, there is an effect that the frequency of access to the memory is improved and the memory access efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bank access control system according to the present invention.

FIG. 2 is a diagram showing a position of a bank check block in a computer system which controls a bank access control system according to the present invention.

FIG. 3 is a block diagram of a bank check circuit 4 of FIG. 1;

FIG. 4 is a block diagram of a request selection circuit 5 of FIG. 1;

FIG. 5 is a diagram showing an example of a timing chart when a memory request stored in a word a accesses a bank 0;

FIGS. 6A and 6B are block diagrams showing an embodiment of the prior art.

[Explanation of symbols]

 Reference Signs List 1 request buffer 2 request selector 3 bank busy counter 4 bank check circuit 5 request select circuit 6 request select 7 bank address 8 bank busy information 9 access destination bank address 10 bank path information of all memory requests 11 bank check block 12 memory control unit 13 data Output control unit 20 Access selection circuit 21 Bank busy management unit

Claims (5)

[Claims] 1. A bank access control method for a main memory having a plurality of banks, comprising: a request buffer for storing a memory request whose access destination bank is busy, wherein said request buffer is stored at a predetermined cycle. Memory access efficiency, wherein the memory request in which the access destination bank is no longer in the busy state among the memory requests stored in the memory request and the newly received memory request is issued to a memory control unit. Bank access control method aiming at improving the performance. 2. A bank access control method for a main memory having a plurality of banks, wherein a request buffer for storing a memory request in which an access destination bank is busy or does not meet a predetermined selection condition, and a request buffer of the bank. A bank busy counter for managing a busy state, and refer to the bank busy counter for a busy state of an access destination bank of the memory request stored in the request buffer and a newly received memory request at a predetermined cycle. A bank check circuit for checking the memory request, and selecting a memory request that satisfies the selection condition among memory requests in which the access destination bank checked by the bank check circuit is not in a busy state and issues the request to a memory control unit. circuit A bank access control method for improving memory access efficiency, characterized by comprising: 3. The bank access control method according to claim 1, wherein said predetermined period is a clock cycle. 4. The bank busy counter starts counting when the memory request is issued to the bank and makes the bank busy, and resets the counter when the memory request reaches a certain value to release the busy state of the bank. 3. The bank access control method according to claim 2, wherein: 5. The selection condition is such that the memory request stored in the request buffer and a newly received memory request have a priority, and the memory request having the highest priority is selected. The bank access control method according to claim 2.