JPH10288653A - Jitter measuring method and semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to measure the width of jitter by moving a strobe signal sequentially, detecting the presence or absence of fails and obtaining the rear-edge position and the front-edge position of the jitter. SOLUTION: From a test-pattern generator 20, a specified reference clock signal 21clk , is supplied into a reference-clock input terminal 11 of a DUT. A fail counter 40 initially sets the position of a strobe signal at the position of the rear-edge side of jitter, which does not detect a fail. Then, the timing position of the strobe signal is sequentially moved forward until the fail counter 40 detects the fail for a specified time. The position of the strobe signal when the fail is detected is made to be the jitter rear-edge position Max . Furthermore, the fail counter 40 initially sets the position of the strobe signal at the position of the front-edge side of the jitter for detecting all fails. The timing position of the strobe signal is sequentially moved to the rear side. The position when all fails are not detected is made to be the jitter front-edge position Min . The difference between the rear-edge position Max and the front-edge position Min is obtained and made to be the width of the jitter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to measurement of jitter output from a device having an oscillation circuit or a device for outputting a clock signal containing jitter using a semiconductor test apparatus.

[0002]

2. Description of the Related Art Some recent devices have a PLL inside.
There is a device that has a built-in circuit and outputs a predetermined frequency signal in synchronization with an externally supplied reference clock. In such a device test, it is necessary to set and control predetermined conditions such as internal registers of the device, apply a high-purity reference clock, receive an output signal from the device, and measure the amount of jitter. is there.

A prior art example will be described with reference to a jitter measurement configuration diagram of FIG. It is assumed that the device under test (DUT) is a device with a built-in PLL circuit. The configuration of the jitter measuring device includes a device internal condition setting control unit 70, a reference signal generator 80, and an output waveform observation device 90 (for example, an oscilloscope).

[0004] The device internal condition setting control unit 70 includes a DU
It supplies a control signal for setting the setting conditions of the T internal register and the like to predetermined conditions. The reference signal generator 80
It is a high-purity reference clock generation source of a desired frequency that does not affect the jitter measurement accuracy of the UT, and is supplied to the reference clock input terminal 11 of the DUT and the trigger input terminal of the output waveform observation device 90. The output waveform observation device 90 sweeps in synchronization with the reference clock signal 81 from the reference signal generator 80, receives the output signal from the output terminal 12 of the PLL oscillation frequency of the DUT, observes this jitter width, Inspect whether it is within the standard of the device specification.

As described above, a dedicated jitter measuring jig is prepared, and the device internal condition setting control unit 70 controls the DU.
The test is performed with the T internal condition set to a predetermined condition. However, since the measurement is often performed a plurality of times while changing the DUT internal condition, an inspection time is required. Particularly, in a device that is mass-produced, various tests of general DC characteristics, AC characteristics, and functional characteristics of other built-in circuits are tested by a semiconductor test device. For this reason, it is practically inconvenient to separately install a dedicated jig for jitter measurement and perform a separate test, in terms of test cost / measurement time.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a measuring method and a jitter measuring apparatus for measuring a jitter of a frequency signal output from a device using a semiconductor test apparatus. .

[0007]

FIG. 1, FIG. 2, and FIG. 3 show a solution according to the present invention. First, in order to solve the above problem, in the configuration of the present invention, a predetermined reference clock signal 21clk is supplied to the reference clock input terminal 1 of the DUT.
1, a strobe signal STB1 is sequentially moved backward from the front side in response to the oscillation output signal 15 from the DUT output terminal 12, and the failure counter 40 fails at each strobe movement position. A means for detecting the presence / absence (or presence / absence of a path) and obtaining a Min position 201 of the leading edge of the jitter based on the presence / absence of the DUT is provided.
In response to the oscillation output signal 15 from the output terminal 12, the strobe signal STB1 is sequentially moved from the rear side to the front, and the presence or absence of a failure (or the presence or absence of a path) by the fail counter 40 is detected at each strobe movement position. Means for calculating the trailing edge Max position 202 are provided, and the difference between the calculated jitter positions is obtained as a jitter width. Thus, the strobe signal STB1 of the timing comparison unit 30 and the fail counter 40 are used.
In a semiconductor test apparatus for measuring jitter of a device under test, jitter measurement of a frequency signal output from the device under test is realized.

FIG. 2 shows a solution according to the present invention. Second, in order to solve the above-described problem, in the configuration of the present invention, a predetermined reference clock signal 21clk is supplied from the test pattern generator 20 to the reference clock input terminal 11 of the DUT, and the fail counter 40 performs Initially, the position of the strobe signal STB1 is set at the position on the trailing edge side, fail detection is performed by the fail counter 40 for a predetermined time Tmeas, and if no fail is detected first, the strobe signal STB is detected in the direction to detect the jitter trailing edge.
The timing is shifted to the position of No. 1 and repeatedly executed. When the second fail is detected, the position of the strobe signal STB1 is obtained and stored as the Max position 202 of the trailing edge of the jitter.
Next, the position of the strobe signal STB1 is initially set to a position on the leading edge side of the jitter where the fail counter 40 detects all failures (that is, a position that never makes a pass), and the failure detection by the fail counter 40 is performed for a predetermined time Tmeas. First, when all failures are detected (that is, when no pass is detected), the timing position of the strobe signal STB1 is moved repeatedly in the direction to detect the leading edge of the jitter, and secondly, all failures are detected. If not (ie, if a path is detected at least once), the position of the strobe signal STB1 is changed to the Min position 201 of the leading edge of the jitter.
And a jitter measurement method for obtaining a difference between the Min position 201 of the leading edge of the jitter and the Max position 202 of the trailing edge of the jitter as a jitter width. Thereby, the strobe signal STB of the timing comparison unit 30 included in the semiconductor test device
1, and using the fail counter 40, for example, PL
In a jitter measurement of a device under test incorporating an L oscillation circuit, a jitter measurement method of a frequency signal output from the device under test is realized.

As a method of measuring the jitter stabilization time until the jitter is stabilized, the above-mentioned measuring method is used to measure the M at the leading edge of the jitter.
In position 201 and Max position 202 of the trailing edge of jitter are obtained, and when a predetermined reference clock signal 21 clk is supplied from the test pattern generator 20 to the reference clock input terminal 11 of the DUT, the output is stopped for a predetermined period or the output is unstable. After setting the reference clock signal 21clk, the original stable reference clock signal 21clk is supplied. From this point, the elapsed time by the built-in clock is measured, and the jitter leading edge Min obtained in advance is determined.
The position of the strobe signal STB1 is set at a predetermined position adjacent to the position 201 or the Max position 202 of the trailing edge of the jitter where no fail is detected, and the count data of the fail counter 40 is read every unit minute time, and the count data does not change. There is a measurement method for obtaining the elapsed time as the jitter stabilization time of the DUT. Thus, the measurement of the jitter stabilization time from when the stable reference clock signal 21clk is supplied to when the jitter is stabilized is realized.

FIG. 5 shows a solution according to the present invention. Third, in order to solve the above problem, in the configuration of the present invention, the test pattern generator 2 that supplies a predetermined reference clock signal 21clk to the reference clock input terminal 11 of the DUT.
0, receiving the oscillation output signal 15 from the DUT output terminal 12 and sequentially moving one strobe signal S
A means for moving TB1, detecting the presence or absence of a failure by the fail counter 40 at each strobe movement position, and obtaining a Min position 201 of the leading edge of the jitter based on the failure is provided.
In response to the oscillation output signal 15 from the T output terminal 12, the value of the expected value pattern 25exp is inverted, and the other strobe signal STB2 is sequentially moved from the rear side to the front side. Is detected, and from this, the Max position 20 of the trailing edge of the jitter is detected.
There is a measuring method in which a means for obtaining the value 2 is provided and the difference between the obtained jitter positions is obtained as a jitter width. In this case, the jitter width measurement method uses both strobe signals STB1 and STB2.

In the above-described jitter measurement, two comparator circuits 31, 3 provided in the timing comparing section 30 are provided.
In the case where the measurement method using only one of the two strobe signals STB1 is used, both strobe signals STB1 and STB2 are used.
1. There is an advantage that the jitter measurement error factor can be reduced as compared with the case where the STB 2 is used.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

FIG. 1 is a block diagram of a main part relating to the measurement of jitter in the embodiment of the present invention, FIG.
The detection operation by the fail counter of FIG. 3 will be described with reference to FIG.

The main configuration of the present invention is as shown in FIG.
A test pattern generator 20, a timing comparison unit 30,
It comprises a fail counter 40, a measurement program 50, and a control unit 60. All of these configurations are functional elements of the semiconductor test apparatus. The counting operation of the fail counter 40 is a basic functional element of the semiconductor test device,
The expected value pattern 2 from the test pattern generator 20 for the signal latched by the comparator circuits 31 and 32
5exp is counted when there is a mismatch and when the CPE (comparator enable) signal is valid.
The expected value pattern 25exp and the CPE signal differ depending on the memory test device and the logic test device. For example, there is a configuration in which counting is controlled by a 3-bit code signal. In any case, as an input function element for controlling the fail counter, Same and prior art.

In the present invention, the presence or absence of the count value of the fail counter 40 (that is, the presence or absence of a failure) is checked while sequentially moving the strobe point, thereby obtaining a value corresponding to the jitter width.
This is a method in which a boundary point at a location is obtained, and a jitter width is obtained from the boundary point. In the present invention, only one strobe signal STB1 of one of the comparator circuits 31 and 32 provided in the timing comparison unit 30 is used so that the jitter measurement can be performed with higher accuracy. This is to remove the measurement error factor on the measurement side as much as possible in order to accurately measure a minute jitter width of several tens of picoseconds.

The jitter measurement operation will be described below with reference to the measurement flowchart of FIG. When measuring the jitter, it goes without saying that various setting conditions of the pin electronics circuit are set in advance so that the oscillation output signal 15 from the DUT output terminal 12 is supplied to the timing comparing section 30.

First, in step # 100, the DUT is set up in a jitter measurement state. That is, the internal conditions of the DUT are set to a predetermined value, the other input pins of the DUT are set to a predetermined state, and a high-purity reference clock signal 21cl from the test pattern generator 20 is output.
k is supplied to the reference clock input terminal 11 of the DUT.
Further, the expected value of the expected value pattern 25exp is set to “L”, and D
Predetermined elapsed time Twa for jitter to stabilize from the start of UT operation
After it, the fail counter 40 detects the failure (Fa).
il) The strobe signal STB1 is initialized at a position where no detection is performed, that is, at a strobe point 200 shown in FIG. The reference clock signal 21clk supplied from the test pattern generator 20 to the DUT is a stable signal source with little jitter included in the semiconductor test device. The strobe point 200, which is the initial position, first uses the device test function of the semiconductor test apparatus to measure the transition point of the oscillation output signal 15 of the DUT in advance, and uses this position information. Second, there is a method of coarsely moving the strobe point using the measurement methods # 101 to # 103 described below and using the position information.

In the operation steps # 101 to # 103,
The position 202 of the jitter trailing edge is determined. # 101 is
Fail counting is performed for a predetermined time Tmeas. That is, a predetermined clock time is waited at the designated strobe point 200, and the fail counter 40 performs the fail counting during this period. As a result, the level of the oscillation output signal 15 of the DUT becomes "
If the value becomes "H", the failure is counted and the failure is detected. Here, the predetermined time Tmeas is a clock time capable of detecting a randomly generated jitter, for example, 1000 to 1000 clock times. This time is extremely short. The detection of the presence or absence of a failure is performed at high speed.

Step # 102 is a decision branch. That is, the contents of the fail counter 40 are read out. If the count value is zero, the flow proceeds to # 103, and if there is, the flow proceeds to # 104. That is, the above # 1
As shown in FIG. 3A, when the strobe point 200 is sequentially moved to the near side by 03, a failure is detected, and the process proceeds to # 104. # 103 is the next strobe point 2
In order to move to the 00 position, for example, the unit time is moved 20 picoseconds in the forward direction. Then, the fail count measurement is performed in the same manner in # 101. # 104 corresponds to FIG.
As shown in (a), this position is stored as the Max position 202 of the trailing edge of the jitter.

In step # 105, the same condition is maintained while the expected value of the expected value pattern 25exp remains "L", and the strobe signal ST
The strobe point 200 of B1 is moved to the position shown in FIG. 3B so that all the fail counters 40 fail. Thereafter, the flow proceeds to # 106.

In the operation steps # 106 to # 109,
The Min position 201 of the leading edge of the jitter is obtained. # 106 is
The CPE signal is enabled for a predetermined number of known periods, and the fail counter 40 counts the failures during this period. If the count value matches the total number of failures, all are detected as failed, and if different from the total number of failures, at least one pass is detected.
This operation is repeatedly performed a predetermined number of times. As a result of this test, at least one pass has been detected if all failures have not been detected even once. # 107 is a decision branch. That is, upon receiving the test result of # 106, the process proceeds to # 108 in the case of all failures, and proceeds to # 109 in the case of detecting a pass even once. That is, as shown in FIG. 3B, the strobe point 200 is sequentially moved backward, and if a pass is detected even once, the process proceeds to # 109. # 109
As shown in FIG. 3B, this position is defined as the Min position 201 of the leading edge of the jitter.

Finally, in # 110, the jitter width 205 of the DUT to be obtained is obtained as Max = Min position.
This is obtained as the jitter width of the DUT. It goes without saying that the measurement program 50 is prepared and described so that the above-described measurement is performed. In the above measurement flow, # 105 to # 109 may be measured first.

According to the above-described measuring method, the jitter of the DUT is detected by using only one comparator circuit 31 in the timing comparing section 30 and sequentially moving the strobe point 200 to detect the presence or absence of a failure. Since it is possible to measure the leading edge and the trailing edge, a great advantage that accurate jitter measurement can be realized is obtained. Further, there is obtained a great advantage that various tests of the DUT including the jitter measurement items can be performed only by the semiconductor test device.

In the above description of the embodiment, the case where the oscillation output signal 15 from the DUT is a rectangular wave is described. VOL (for example, 0.00V
It is clear that the same operation can be performed because the digital signal can be converted into a digital signal by giving the setting.

In the description of the above embodiment, the case where the frequency of the oscillation output signal 15 from the DUT is the same as the applied reference clock signal 21clk has been described. Even so, since there is a phase synchronous correlation with the reference clock signal 21clk, it is sufficient to create and execute a test program so as to make the CPE signal valid only in a predetermined clock cycle, which is easy for a semiconductor test apparatus. That is. For example, in the case of the oscillation output signal 15 which is 1/10 of the reference clock signal 21clk, the CPE signal may be enabled every 10 clock cycles of the reference clock signal 21clk. Therefore, the present invention can be similarly implemented even in the case of different output frequencies.

In the above embodiment, the measurement is performed after a predetermined elapsed time Twait when the jitter of the oscillation output signal 15 of the DUT is stabilized. However, until the jitter is stabilized using the above-described method. Can be measured. That is, the Min position 2 of the leading edge of the jitter in the measurement method described above.
01 and the Max position 202 of the trailing edge of the jitter are obtained in advance, and a predetermined reference clock signal 21cl is output from the test pattern generator 20.
In the case where k is supplied to the reference clock input terminal 11 of the DUT, the reference clock signal 21clk in a random state (or another clock frequency or clock stop) is temporarily set for a predetermined period, and then the original stable reference clock signal 2
1clk is supplied, and the elapsed time by the built-in clock is measured from this point, and the Min position 2 of the leading edge of the jitter obtained in advance is determined.
01 or a desired position where no fail is detected adjacent to the jitter maximum position 202 (desired jitter standard position)
, The position of the strobe signal STB1 is set, and the count data of the fail counter 40 is read out every unit minute time.
There is a method of obtaining the elapsed time when the count data does not change as the stabilization time of the DUT, and this jitter stabilization time measurement method may be additionally provided. This makes it possible to measure and realize the jitter stabilization time from when the stable reference clock signal 21clk is supplied to when the jitter is stabilized. For example, in the case of a PLL oscillation circuit, the effect of measuring the elapsed time until phase lock is obtained.

In the above description of the embodiment, an example has been described in which a fail count is performed during a relatively short period of time Tmeas to detect the presence or absence of jitter. In order to obtain the jitter width, the worst jitter width may be obtained by performing fail counting for a long period of time Tmeas.

In the description of the above-described embodiment, a measurement example in which the conditions of the DUT other than the jitter measurement are not changed has been described. However, if necessary, other peripheral circuits of the DUT internal circuit may be changed. A desired test pattern can be applied to the DUT from the test pattern generator 20 at the same time as the measurement of the dynamic jitter in parallel with the measurement. Therefore, the measurement can be performed in the same manner by using the same method as described above. It is clear. In this case, the actual DU
An advantage is obtained in that jitter measurement accompanying the influence of interference on adjacent circuits inside the DUT can be realized under operating conditions close to the operating state of T.

In the above description of the embodiment, a specific example of jitter measurement of a DUT having a built-in PLL oscillation circuit has been described. If desired, an output signal having a phase synchronization correlation with the reference clock signal 21clk may be used. Jitter can be measured in the same manner in other devices that output the same.

In the description of the above embodiment, in order to reduce an error factor at the time of jitter measurement, a measuring method using only one strobe signal STB1 of one of the comparator circuits 31 and 32 provided in the timing comparing section 30 is used. Has been described, but if desired, as shown in the measurement flowchart of FIG. 5B, both strobe signals ST
B1 and STB2 are used, and correspondingly, the expected value of the expected value pattern 25exp is inverted at # 105, and
The test and determination in # 108 may be performed in the same manner as in # 101 to # 103 to detect the presence / absence of a failure and obtain the Min position 201 of the leading edge of the jitter. In this case, a skew error factor between both strobe signals STB1 and STB2 is added, but it is practical.

[0031]

According to the present invention, the following effects can be obtained from the above description. According to the configuration of the above-mentioned invention, the presence or absence of jitter is detected by sequentially moving the strobe point 200, and the jitter width can be obtained by measuring the leading edge and the trailing edge of the jitter using this. . Further, there is obtained a great advantage that various tests of the DUT including the jitter measurement items can be performed only by the semiconductor test device, and the test cost can be reduced, and the economic effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part relating to measurement of jitter according to the present invention.

FIG. 2 is a measurement flowchart of the present invention.

FIG. 3 is a diagram illustrating the operation of a fail counter according to the present invention.

FIG. 4 is an example of a conventional jitter measurement configuration.

FIG. 5 is another measurement flowchart of the present invention.

[Explanation of symbols]

 Reference Signs List 20 test pattern generator 30 timing comparison section 31, 32 comparator circuit 40 fail counter 50 measurement program 60 control section 70 device internal condition setting control section 80 reference signal generator 90 output waveform observation device DUT device under test

Claims (4)

[Claims] 1. A device under test (DU) using a strobe signal of a timing comparison unit and a fail counter.
A test pattern generator for supplying a predetermined reference clock signal to a reference clock input terminal of the DUT, and receiving an output signal from the DUT output terminal and sequentially rearward from the near side. The strobe signal is moved, and the presence or absence of a failure or the presence or absence of a path is detected by a fail counter at each strobe movement position, and a means for obtaining the Min position of the leading edge of the jitter is received from the strobe signal. Means for sequentially moving the strobe signal from the rear side to the near side, detecting the presence or absence of a failure or the presence or absence of a path by a fail counter at each strobe movement position, and determining the Max position of the trailing edge of the jitter from this; And a difference between the two jitter positions is obtained as a jitter width. 2. In a jitter measurement of a device under test using a fail counter, and a strobe signal of a timing comparison section included in a semiconductor test apparatus, a predetermined reference clock signal is supplied from the test pattern generator to D.
The strobe signal is supplied to the reference clock input terminal of the UT, the position of the strobe signal is initially set to a position on the trailing edge side of the jitter where the fail counter does not detect a fail, and the fail counter performs the fail detection for a predetermined time. If not, the timing position of the strobe signal is moved in the direction of detecting the trailing edge of the jitter, and the repetition is performed. If the second fail is detected, the position of the strobe signal is obtained and stored as the Max position of the trailing edge of the jitter. Initially, the position of the strobe signal is initially set at a position on the leading edge side of the jitter where the fail counter detects a fail, the fail detection is performed by the fail counter for a predetermined time. The timing position of the strobe signal is moved in the direction in which the edge is detected, and the operation is repeatedly performed. If no fail is detected, the position of the strobe signal is obtained as the Min position of the leading edge of the jitter, and the difference between the Min position of the leading edge of the jitter and the Max position of the trailing edge of the jitter is determined as the jitter width. Jitter measurement method. 3. A jitter measuring method for a device under test using a strobe signal of a timing comparing section and a fail counter of a semiconductor test apparatus, the method comprising: Max position is obtained, and a predetermined reference clock signal is supplied from the test pattern generator to D
When supplying to the reference clock input terminal of the UT, after stopping the output for a predetermined period or making the reference clock signal indefinite, supply the original stable reference clock signal, and measure the elapsed time by the built-in clock from this time, A strobe signal position is set at a predetermined position where no fail is detected adjacent to the jitter leading edge Min position or the jitter trailing edge Max position obtained in advance, and the count data of the fail counter is read out every unit minute time. A jitter measuring method, wherein an elapsed time when the count data does not change is obtained as a jitter stabilization time of the DUT. 4. A semiconductor test apparatus for measuring jitter of a device under test by using both strobe signals of a timing comparison section and a fail counter, wherein a predetermined reference clock signal is supplied to a reference clock input terminal of a DUT. In response to the output signal from the test pattern generator and the DUT output terminal, one strobe signal is sequentially moved from the near side to the back, and the presence or absence of a failure is detected by a fail counter at each strobe movement position. Means for determining the edge Min position, and receiving the output signal from the DUT output end, sequentially moving the other strobe signal from the rear to the front, detecting the presence or absence of a failure by a fail counter at each strobe movement position, Means for determining the Max position of the jitter trailing edge; The semiconductor testing apparatus and obtaining a partial as jitter width.