JPH1028223A - Image data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image data processor for obtaining image data which can be easy to see even when pixel density is converted. SOLUTION: An image data processor 1 is provided with a gradation emphasizing circuit 11 and a pixel-density converting circuit 12. The gradation- emphasizing circuit 11 considers one pixel among plural pixels, calculates the average of the multilevel data of the plural pixels adjacent to the pixel under consideration, and outputs an arithmetic result based on a difference between the multilevel data of the arithmetic result and the multilevel data of the pixel under consideration as new multilevel data in which the density of the pixel under consideration is emphasize. Also, a pixel-density converting circuit 12 calculates the average of the multilevel data of the adjacent two pixels for the multilevel data of each pixel, inputted from the gradation emphasizing circuit 11, selects and outputs the multilevel data of the arithmetic result or the multilevel data before the arithmetic operation, and converts the number of the pixels worth one line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image data processing apparatus, and more particularly, to an image data processing apparatus capable of processing by converting the pixel density of image data.

[0002]

2. Description of the Related Art Generally, facsimile, copy, OCR
The image data processing device used in the above-described apparatus converts an analog image signal input from a line sensor such as a CCD or a contact sensor into high-quality binary image data, and outputs the binary image data. The facsimile transmits the converted binary image data to a destination via a modem. In copying, the converted binary image data is output to a printer to create a document. Also, OCR is
The converted binary image data is output to a computer such as a personal computer.

By the way, with respect to image data obtained by a line sensor, the required pixel density may differ between communication and copying. For example, 200 dpi for communication and 400 dpi for copying
i, etc. When communicating, the pixel density is reduced to reduce the amount of data to reduce the transfer speed, and when copying, the pixel density is increased to improve image quality.

In this case, the image data processing device converts the pixel density of data according to the pixel density of communication, a printer, a personal computer or the like. For example, in the case of copying, the image data processing device enlarges the image data, that is, outputs the data of each input pixel twice, thereby doubling the number of pixels and increasing the pixel density. . When image data input from a personal computer is output to a printer, the pixel density (for example, 800 dpi) of the image data handled by the personal computer is often higher than the pixel density of the printer. Accordingly, the image data processing apparatus reduces the image data input from the personal computer, that is, reduces the pixel density by reducing the number of pixels by half by outputting every other pixel of the image data and thinning it out. Output to a printer.

[0005]

However, when the pixel density is increased, the pixels are output twice, that is, two pixels of the same data are continuously output. May be.

On the other hand, when the pixel density is reduced, the width of a line having the same thickness may change or a thin line may disappear. For example, in the case of a line for three pixels, a line for two pixels is obtained when one pixel at the center is thinned, and a line for one pixel is obtained when two pixels on both sides are thinned. In addition, the line for one pixel was sometimes thinned out.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an image data processing apparatus capable of obtaining easy-to-view image data even if the pixel density is converted. .

[0008]

According to a first aspect of the present invention, multi-valued data obtained by quantization for each pixel from image data constituting one screen, which is continuous in units of one line, is fetched. An image data processing device that converts and outputs multivalued data to value data, calculates an average value of multivalued data corresponding to two adjacent pixels, and calculates multivalued data of the calculation result and multivalued data before calculation, The gist of the present invention is to provide a pixel density conversion circuit for selectively outputting the number of pixels per line to a desired number by selectively outputting in response to a selection clock of a predetermined pattern.

According to a second aspect of the present invention, multi-valued data obtained by quantization for each pixel is taken from image data constituting one screen, which is continuous in units of one line, and is converted into binary data in order. An image data processing device for outputting, wherein a difference between the multi-value data of a specific pixel of each line and the multi-value data of another pixel adjacent to the pixel is added to emphasize the shading between pixels. And a multi-level emphasis circuit that outputs multi-level data, multi-level data of each pixel is input from the multi-level emphasis circuit, and an average value of multi-level data corresponding to two adjacent pixels is calculated. A pixel density conversion circuit for selectively outputting data and multi-value data before operation in response to a selection clock of a predetermined pattern, and converting the number of pixels per line into a desired number. And

[0010] The invention described in claim 3 is the invention according to claim 1 or 2.
In the image data processing device described in the above, the pixel density conversion circuit, a plurality of serially connected registers that sequentially store multi-valued data of a plurality of pixels that are continuously input, and a plurality of registers stored in the plurality of registers Among the multi-valued data, multi-valued data of two adjacent pixels is input, an average operation circuit for calculating an average of the multi-valued data, multi-valued data stored in the register, A selection circuit that receives the operation result and selects and outputs multi-valued data and the operation result in response to a selection clock of a predetermined pattern generated according to the density of the pixel to be converted.

According to a fourth aspect of the present invention, in the image data processing apparatus according to the second aspect, the density enhancement circuit comprises:
A plurality of registers for respectively storing multi-value data of a plurality of adjacent pixels, and among the multi-value data stored in the plurality of registers, adjacent to the specific pixel with respect to image data of a specific pixel of interest A subtractor for calculating the difference between the multi-value data of the pixel and a calculation result of the subtractor,
A multiplier for multiplying the set emphasis degree, an operation result of the multiplier, and multi-value data of the specific pixel are added, and the addition result is output as new multi-value data for the specific pixel And an adder.

Therefore, according to the first aspect of the present invention,
In the pixel density conversion circuit, an average value of multi-value data corresponding to two adjacent pixels is calculated, and multi-value data of the calculation result and multi-value data before calculation are selected in response to a selection clock of a predetermined pattern. As a result, the number of pixels per line is converted into a desired number.

According to the second aspect of the present invention, in the shading emphasis circuit, the difference between the multi-value data of a specific pixel in each line and the multi-value data of another pixel adjacent to the pixel is determined. New multi-value data in which the addition and the shading between pixels are emphasized is output. In the pixel density conversion circuit, multi-value data of each pixel is input from the shading emphasis circuit, the average value of multi-value data corresponding to two adjacent pixels is calculated, and the multi-value data of the calculation result and the multi-value data before calculation are calculated. Data is selectively output in response to a selection clock of a predetermined pattern, and the number of pixels per line is converted to a desired number.

According to the third aspect of the present invention, the pixel density conversion circuit includes a plurality of registers, an average operation circuit, and a selection circuit. The plurality of registers respectively store the input multi-value data of the plurality of pixels.
The averaging circuit receives multi-value data of two adjacent pixels among the multi-value data stored in the register, and calculates an average of the multi-value data. The selection circuit inputs the multi-value data stored in the register and the operation result of the averaging circuit, and selects and outputs the multi-value data and the operation result according to the density of the pixel to be converted.

According to the fourth aspect of the present invention, the gray level emphasizing circuit includes a plurality of registers, a subtractor, a multiplier, and an adder. The plurality of registers respectively store multivalue data of a plurality of adjacent pixels. The averaging circuit, among the multi-value data stored in the register,
The multi-value data of a plurality of pixels adjacent to the pixel of interest is input, and the average of the multi-value data is calculated. The subtractor calculates the difference between the calculation result of the average calculation circuit and the multi-value data of the pixel of interest. The multiplier multiplies the operation result of the subtractor by the set emphasis degree. Then, the adder adds the operation result of the multiplier and the multi-value data of the pixel of interest, and outputs the addition result as new multi-value data of the pixel of interest.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic block circuit diagram of the image data processing device. The image data processing device 1 can be used for various applications such as facsimile. Image data processing device 1
Converts an analog image signal obtained from a CCD or a contact sensor into high-quality binary image data. The converted binary image data is used for facsimile and copy. Further, the image data processing device 1 outputs multi-valued data before conversion to binary image data. This multi-value data is used for image input of a personal computer.

The image data processing device 1 includes an analog unit 2,
Distortion correction unit 3, multi-level resolution conversion unit 4, gamma correction unit 5,
A filter section 6, a halftone section 7, a binarization section 8, a control circuit 9,
And a register 10 integrated on one chip.

The line sensor divides a transmission original into a plurality of pixels in the main scanning direction, reads the density of each pixel, and outputs an image signal having a voltage corresponding to the density. The image signal input from the line sensor is input to the analog unit 2.
The image signal is an analog value, for example, a high voltage when the pixel is black, a low voltage when the pixel is white, and an intermediate voltage when the pixel is gray. The analog unit 2 includes an A / D converter having a predetermined number of bits (for example, 8 bits).
The image signal is quantized and converted into multi-value data of a plurality of gradations (256 gradations). The converted multi-value data has a value corresponding to the density of each pixel. Then, the converted multi-value data is output to the distortion correction unit 3.

The distortion correction unit 3 reads the distortion correction data stored in advance in a memory (not shown) and
The multi-value data for the line is subjected to gradation correction based on the distortion correction data, and the multi-value data resulting from the correction is output to the multi-value resolution conversion unit 4. The distortion correction data (shading data) is data for numerically correcting distortion generated in the optical system.

The multi-level resolution conversion unit 4 converts the data input from the distortion correction unit 3 into a multi-level data by performing a density enhancement process for enhancing the density of each pixel and a density conversion process for converting the pixel density. It is provided for performing. The multi-level resolution converter 4 includes a density enhancement circuit 11 as a density enhancement circuit and a pixel density conversion circuit 12.

The multi-level data corrected by the distortion correction unit 3 is input to the gray level emphasizing circuit 11. Shade emphasis circuit 11
Performs a shading enhancement process based on multi-value data of a plurality of pixels in the main scanning direction. In the present embodiment, the gray level emphasizing circuit 11 holds multi-value data of three pixels, performs gray level processing based on the multi-level data of the three pixels, and performs multi-level processing of each pixel subjected to the gray level processing. The value data is output to the pixel density conversion circuit 12.

As shown in FIG. 8, one line of image data L1 read in the main scanning direction is composed of a plurality of pixels G. Then, the gray level emphasizing circuit 11 inputs a plurality of (three in this embodiment) pixels G at each time,
Shade emphasis processing is performed based on the input multi-value data of the plurality of pixels G. In order to distinguish the pixel G input to the density enhancement circuit 11 at this time from other pixels G, FIG.
1, G2, and G3.

The gradation emphasizing circuit 11 performs a gradation emphasizing process on a central pixel G2 among three pixels G1 to G3 adjacent in the main scanning direction. The shading emphasis circuit 11 calculates a shading difference between the shading of the pixel of interest G2 and the average of shading of two adjacent pixels G1 and G3, and uses the shading difference as a first-order differential coefficient. Then, the shading emphasis circuit 11 multiplies the primary differential coefficient by a preset emphasis degree, and adds the multiplication result to the multi-value data of the target pixel G2. The addition result becomes new multi-value data of the pixel of interest G2 that has been subjected to the shading emphasis processing.

In the above-described shading emphasis processing, assuming that the multivalued data of the pixel of interest G2 is D0 and the multivalued data of the adjacent pixels G1 and G3 are D1 and D2, respectively, the primary differential coefficient K1 is K1 = D0- (D1 + D2 ) / 2 (1). Further, assuming that the degree of emphasis is K2 and the new multi-value data of the pixel of interest G2 is DX, DX = D0 + K2 × K1 (2)

For example, as shown in FIG. 9, the values representing the multivalued data of a plurality of (five in FIG. 9) pixels G11 to G15 in the main scanning direction are “100” and “120”, respectively.
“120”, “100”, and “100”, and the degree of emphasis K2 is “2”. First, the gray level emphasizing circuit 11 includes a pixel G11.
To the center pixel of interest G1 based on the multi-valued data of
The two new multivalued data are calculated to obtain “140” as the multivalued data of the pixel G12a. Next, the shading emphasis circuit 11
Calculates new multivalued data of the pixel of interest G13 based on the multivalued data of the pixels G12 to G14,
"140" is obtained as multi-valued data. Further, the gray-scale emphasizing circuit 11 calculates new multi-value data of the pixel of interest G14 based on the multi-value data of the pixels G13 to G15, and obtains “80” as the multi-value data of the pixel G14a.

Therefore, the difference between the multivalued data of the pixels G12a and G13a and the multivalued data of the pixel G14a is
Since the difference is larger than the difference between the multi-value data of G2 and the multi-value data of G13 and the multi-value data of pixel G14, the shading of the pixels G12 to G14 is emphasized.

The pixel density conversion circuit 12 calculates the average of the pixels adjacent in the main scanning direction, and outputs the calculation result and the multi-value data of the adjacent pixels according to the conversion density, thereby reducing the number of pixels. It is designed to increase or decrease. For example, FIG.
As shown in FIG. 0 (b), the pixel density conversion circuit 12 calculates an average for every two adjacent pixels input and outputs only multi-valued data of the calculation result. That is, the pixel density is converted to “１ ／” by calculating and outputting multi-value data of one pixel based on two pixels. Further, as shown in FIG. 10C, the pixel density conversion circuit 12 calculates the average of two adjacent pixels every other pixel, and calculates the multivalued data of one pixel that has not been calculated and the multivalued data of the calculation result. Are output alternately. That is, by calculating and outputting one pixel from two pixels every other pixel, the pixel density is converted to “画素”.

As shown in FIG. 10D, the pixel density conversion circuit 12 calculates an average for every two adjacent pixels.
The multi-value data of the original two pixels and the multi-value data of the operation result are output. At this time, the pixel density conversion circuit 12 outputs the multi-value data of the operation result between the original multi-value data of the two pixels. That is, the pixel density is converted to "3/2 times" by calculating one pixel from two pixels and outputting the original two pixels and the calculation result. Further, as shown in FIG. 10 (e), the pixel density conversion circuit 12 calculates the average of the input two adjacent pixels, and alternately outputs the input pixel and the multi-value data of the calculation result. That is, by inserting the average calculation result of the two pixels between two adjacent pixels, the pixel density is set to “2/1”.
To "double". FIG. 10A shows the case of no conversion.
That is, the case where the pixel density is converted to “1/1” is shown.

The pixel density conversion circuit 12 switches the pixel density to be converted based on control data written in a register described later. Then, the multi-value data of the operation result output from the pixel density conversion circuit 12 is
Output to the gamma correction unit 5.

The gamma correction unit 5 reads gamma correction data stored in a memory (not shown) in advance, and performs gamma correction on the multi-value data input from the multi-value resolution conversion unit 4 based on the gamma correction data. I do. The gamma correction data is data for correcting a deviation between a photoelectric conversion characteristic of the line sensor and a change in light intensity that a person actually visually perceives. The gamma correction unit 5 outputs the multi-value data of the correction result to the filter unit 6. The gamma correction unit 5
Outputs the multi-value data of the correction result directly to the outside.

The filter section 6 is based on the multi-valued data for two lines stored in a memory (not shown) and the multi-valued data for one line input from the gamma correction section 5 and has a size of 3 × 3.
, And outputs the filtered data to the halftone unit 7 or the binarization unit 8. This spatial filter performs filter processing such as edge enhancement on multi-valued data.
The basic configuration is the same as the configuration of the gradation emphasizing circuit 11 described later.

The binarizing unit 8 converts the input multi-value data into binary data based on a preset threshold. The binary data is, for example, “1” when the multi-valued data is larger than the threshold, and “0” when the multi-valued data is smaller than the threshold. When the binary data is "0", the output document is white, and when the binary data is "1", the document is black.

On the other hand, the halftone section 7 performs an error diffusion process on the input multi-valued data, and creates binary data representing the halftone in a pseudo manner. In the error diffusion processing, in order to express multi-value data as binary data, an error generated when binarizing multi-value data of a certain pixel is added to multi-value data of pixels around the pixel. It was done.

The binary data output from the halftone section 7 and the binarization section 8 are output to the outside via the switch SW. The switch SW is an analog switch,
Switching is performed by a control circuit 9 described later according to an image area including the output binary data. The image area includes an area composed of characters and the like, an area composed of photographs and the like. In the character image area consisting of white data and black data,
By switching the switch SW to the binarizing unit 8, binary data with a clear edge can be obtained. On the other hand, in a photographic image area composed of halftone multivalued data, the switch S
By switching W to the halftone section 7, binary data capable of expressing the error-diffusion density in a pseudo manner is obtained.

The control circuit 9 and the register 10 are composed of
8 is provided for control. The register 10 stores various data such as the pixel density to be converted, which is input from a controller for controlling the entire facsimile or the like. The control circuit 9 outputs a control signal to each of the units 2 to 8 based on various data stored in the register 10,
Each of the units 2 to 8 operates based on a control signal.

Next, the configurations of the density enhancement circuit 11 and the pixel density conversion circuit 12 constituting the multi-level resolution conversion section 4 will be described with reference to FIGS. As shown in FIG. 2, the multi-level data TD of each pixel is sequentially input to the gray level emphasizing circuit 11 one pixel at a time. Further, the clock signal CLK and the emphasis signal MF are input to the shading emphasis circuit 11. The clock signal CLK is synchronized with the input timing of the multi-value data TD to be subjected to the shading process.

The emphasis signal MF is generated corresponding to the degree of emphasizing the multi-value data of each pixel. For example, as shown in FIG. 5, to “00” for “emphasized × 0”, to “01” for “emphasized × 1”, to “10” for “emphasized × 2”. , “Emphasis × 4” is set and input to “11”, respectively. Note that “emphasized × 0” indicates that no gray level emphasis processing is performed, “emphasized × 1” indicates that one-time gray level emphasizing processing is performed, and “emphasized × 2” indicates that two-times gray level emphasizing processing is performed. "4" indicates a case where a four-fold shading enhancement process is performed.

The shade emphasizing circuit 11 includes registers 21 and
2, 23, an adder 24, a divider 25, a subtractor 26, a multiplier 27, an adder 28, and a limiter 29.

Each of the registers 21 to 23 is formed of a multi-bit flip-flop circuit, and stores multi-value data TD for one pixel. Registers 21-23
Are connected in series, and the multi-valued data TD
Are sequentially input. Also, in each of the registers 21 to 23,
A clock signal CLK is input, and the clock signal CL
Based on K, the multi-level data TD is sequentially taken in and stored. Each of the registers 21 to 23 outputs the stored multi-value data. Therefore, the registers 21 to 23
Holds multivalued data of three adjacent pixels.
Then, the multi-valued data output from the register 22 becomes the multi-valued data D0 of the target pixel on which the gray level emphasizing process is performed by the gray level emphasizing circuit 11, and the multi-level data output from the registers 21 and 23 are adjacent to the target pixel. Data D1 and D2 of the pixel to be processed.

Multi-value data D output from register 21
1 and the multi-level data D2 output from the register 23,
It is input to the adder 24. The adder 24 performs an addition operation on the input multi-value data D1 and D2, and outputs the operation result to the divider 25. The divider 25 halves the operation result of the adder 24 and outputs the result to the subtractor 26 as a signal AVE. The divider 25 is composed of, for example, a shift register, and shifts the input data by one bit in the lower bit direction to thereby reduce the operation result of the adder 24 by １ ／.
And output.

The subtracter 26 receives the multilevel data D0 output from the register 22 together with the signal AVE.
The subtracter 26 subtracts the signal AVE from the multi-value data D0 and outputs the result of the subtraction to the multiplier 27. Accordingly, the subtracter 26 calculates a gray level difference between the gray level of the pixel of interest and the average of the gray levels of two adjacent pixels, that is, the first derivative K1 of the equation (1). Output.

The multiplier 27 receives the emphasis signal MF. The multiplier 27 multiplies the primary differential coefficient K1 input from the subtractor 26 by the enhancement K2 (Equation 2) based on the input enhancement signal MF, and outputs the calculation result to the adder 28. . The multiplier 27 is composed of, for example, a shift register, and converts the input first derivative K1 into an emphasis signal M
By shifting based on F, the degree of emphasis K2 is multiplied.

As shown in FIG. 5, in the case of “emphasis × 0”,
The multiplier 27 outputs 0 (zero) for the enhancement degree K2 based on the enhancement signal MF. In this case, no shading emphasis processing is performed. In the case of “emphasis × 1”, the multiplier 27 outputs “through”, that is, the primary differential coefficient K1 as it is.
In the case of “emphasis × 2”, the multiplier 27 calculates the first derivative K1
Is shifted one bit upward, that is, twice (K2 = 2)
And output. In the case of “emphasis × 4”, the multiplier 27
The first derivative K1 is shifted upward by 2 bits, that is,
The output is quadrupled (K2 = 4).

The multiplier 27 outputs a limit signal LIM based on the calculation result. The limit signal LIM is output by a limiter 29 described later in accordance with the number of bits of the output multi-level data ED. For example, when the multi-level data ED (multi-level data TD) is 8 bits, the multi-level data ED takes a value from 0 to 255. On the other hand, the primary differential coefficient K1 output from the subtractor 26
Is positive or negative because it is the difference between the average of the shades of two adjacent pixels and the shade of the target pixel. Therefore, the value of the multi-value data ED output from the limiter 29 may exceed the range of 8 bits. Therefore, based on the result calculated by the multiplier 27, the multi-level data ED is set to a positive value in the limiter 29 so as to be within a predetermined number of bits.

Then, as shown in FIG.
If D is a positive value and falls within a predetermined number of bits,
The multiplier 27 sets the limit signal L
IM is set to “00” and output. Also, multi-value data ED
Is a positive value and exceeds the predetermined number of bits, the multiplier 27 sets the limit signal LIM as the “FF limit” (FF is the maximum value represented by unsigned 8 bits (255 in hexadecimal notation)). Is output as "01".
When the multi-value data is a negative value, the multiplier 27 determines “0 limit” (0 is the minimum value represented by unsigned 8 bits)
And outputs the limit signal LIM as "10".

The operation result output from the multiplier 27 is input to an adder 28. Further, the multi-value data D0 of the pixel of interest output from the register 22 is input to the adder 28. The adder 28 performs an addition operation on the operation result of the multiplier 27 and the multi-value data D0 of the pixel of interest, and outputs the operation result. The calculation result becomes new multi-value data of the pixel of interest in (Equation 2).

The limiter 29 receives the calculation result output from the adder 28 and the limit signal LIM output from the multiplier 27. The limiter 29 performs limit processing on the operation result of the adder 28 based on the limit signal LIM, and outputs the processing result as multi-value data ED.

As shown in FIG. 3, the pixel density conversion circuit 12
, Multi-valued data ED as a result of the shading emphasis processing performed by the shading emphasizing circuit 11 is input. Further, the clock signal CLK, the selected clock signal CHS, and the output selection signal RES are input to the pixel density conversion circuit 12. The clock signal CLK is common to the above-described shading emphasis circuit 11.

The selected clock signal CHS is generated and input as a pulse signal corresponding to the density of the pixel to be converted based on the clock signal CLK. Pixel density conversion circuit 1
2, when the selected clock signal CHS is at the H level,
The multi-value data of the calculation result obtained by calculating the average of two adjacent pixels is output. When the selected clock signal CHS is at the L level, the multi-value data of the original pixel is output.

The density of the pixels to be converted is, for example, as shown in FIG.
As shown in (a) to (e), “1/1”, “1/2”
Double, "2/3 times,""3/2times,""2/1times." Corresponding to this, as shown in FIG. 7, the selected clock signal CHS is always generated as an L-level signal when "1/1 times", and is always at an H level when "1/2 times". Is generated as In the case of “2/3”, the selected clock signal CHS is generated as a clock signal in which two cycles are at L level for three cycles of the clock signal CLK. In the case of “3/2 times”, the selected clock signal CHS is set to 1.
Five periods are generated as clock signals having the L level. Further, in the case of “2/1 times”, the selected clock signal CH
S is generated as a clock signal in which 0.5 cycle is L level for one cycle of the clock signal CLK.

The output selection signal RES is set and input according to the density of the pixel to be converted. For example, as shown in FIG. 6, the output selection signal RES is “000” for “1/1”, “001” for “１ ／”,
"010" for "2/3 times", "011" for "3/2 times", and "100" for "2/1 times"
Is set to

The pixel density conversion circuit 12 includes a register 31,
32, 33, adders 34 and 35, dividers 36 and 37, and selection circuits 38, 39 and 40.
Each of the registers 31 to 33 is formed of a multi-bit flip-flop circuit, and stores multi-value data of one pixel. The registers 31 to 33 are connected in series similarly to the registers 21 to 23 of the shading emphasis circuit 11, and sequentially take in and store the multi-value data ED based on the clock signal CLK. With this configuration, the registers 31 to 3
3 holds multivalued data of three adjacent pixels. Then, the register 31 outputs the stored data as the multi-value data WR1. The register 32 outputs the stored data as multi-value data WR2. Further, the register 33 stores the stored data in the multi-value data WR.
Output as 3.

Multi-value data W output from register 31
R1 and multi-value data WR2 output from the register 32
Is input to the adder 34. The multi-value data WR 2 output from the register 32 and the multi-value data WR 3 output from the register 33 are input to the adder 35.
That is, the multi-value data of two adjacent pixels are input to the adders 34 and 35, respectively.

The adder 34 receives the input multi-value data WR
1 and WR2, and outputs the operation result to the divider 36. The divider 36 calculates the operation result of the adder 34 as 1 /
2, and outputs the result as a signal AVE1. The divider 36 is formed of, for example, a shift register, and shifts the input data by one bit in the lower bit direction, thereby halving the operation result of the adder 34 and outputting the result.

The adder 35 performs an addition operation on the input multi-value data WR2 and WR3, and outputs the operation result to the divider 37. Divider 37 halves the operation result of adder 35 and outputs the result as signal AVE2. The divider 37 is composed of, for example, a shift register, and shifts the input data by one bit in the lower bit direction, thereby halving the operation result of the adder 35 and outputting the result.

That is, the adder 34, the divider 36, and the adder 3
5 and the divider 37 constitute an averaging circuit for calculating the average of multi-value data of two adjacent pixels, and output the calculation results as signals AVE1 and AVE2, respectively.

The selection circuit 38 receives the signal AVE1 and the multi-value data WR2 output from the register 32. The multi-value data WR2 output from the register 32 and the signal AVE2 are input to the selection circuit 39. Also, the selection clock signals CH are supplied to both the selection circuits 38 and 39.
S is input.

The selection circuit 38 selects the selected clock signal CHS
AVE1 and multi-level data WR based on
One of the two is selected and output as a signal SEL1. Similarly, the selection circuit 39 outputs the selected clock signal CHS
Based on the input multi-value data WR2 and signal AVE
2 is selected and output as a signal SEL2.

For example, when the selected clock signal CHS is at the L level, both of the selection circuits 38 and 39 provide the multi-level data WR2
Select The selection circuits 38 and 39 hold the selected signal while the selected clock signal CHS is at the L level, and output the signals as signals SEL1 and SEL2, respectively.

When the selected clock signal CHS is at the H level, the selection circuit 38 outputs the signal AVE1 to the selection circuit 39.
Selects the signal AVE2. Then, the selection circuits 38, 3
9 holds the selected signal while the selected clock signal CHS is at the H level, and outputs signals SEL1 and SEL, respectively.
Output as EL2.

The signals SEL1 and SEL2 output from the selection circuits 38 and 39 are input to the selection circuit 40. Further, the multi-value data WR2 output from the register 32 is input to the selection circuit 40. Further, the selection circuit 4
To 0, the output selection signal RES is input.

The selection circuit 40 selects one of the signals SEL1 and SEL2 and the multi-value data WR2 based on the output selection signal RES, and outputs it as multi-value data MD.
The output selection signal RES corresponds to the density of the pixel to be converted. Therefore, the selection circuit 40 selects one of the signals SEL1 and SEL2 and the multi-value data WR2 according to the density of the pixel to be converted, and outputs the multi-value data MD.

That is, the selection circuits 38 to 40 select average multi-value data of two adjacent pixels and multi-value data of the original pixel based on the selection clock signal CHS and the output selection signal RES. , And outputs the converted multi-value data MD.

As shown in FIG. 6, when the density of the pixel to be converted is “1/1”, the selection circuit 40 outputs the multi-value data WR
2 is selected and output as multi-value data MD as it is.
As the multi-level data WR2, the multi-level data of the pixel stored in the register 32 is output in synchronization with the clock signal CLK. Therefore, the multi-value data M output from the selection circuit 40
D is the multi-value data E input to the pixel density conversion circuit 12
D, which does not include the calculation result, that is, is output without conversion of the pixel density.

The density of the pixels to be converted is "1/2 times".
In this case, the selection circuit 40 selects the signal SEL1 and outputs it as multi-value data MD. The signal SEL1 is always supplied to the selection circuit 38 by the selection clock signal C at H level.
The signal AVE1 selected based on the HS is output.
Therefore, since the pixel density conversion circuit 12 outputs multi-value data MD for one pixel from multi-value data ED for two pixels, the pixel density is reduced to half.

The density of the pixels to be converted is "2/3 times"
In this case, the selection circuit 40 selects the signal SEL1 and outputs it as multi-value data MD. The signal SEL1 is selected and output by the selection circuit 38 based on the selected clock signal CHS, either the average calculation result of two adjacent pixels or the multi-value data WR2. Selection circuit 38
Is the multi-level data WR for two cycles of the clock signal CLK.
2 is selected and output as a signal SEL1. During a period of one cycle of the clock signal CLK, the signal AVE1 is selected and the signal SE
Output as L1. Therefore, the pixel density conversion circuit 12
Outputs the multi-value data MD for two pixels from the multi-value data ED for three pixels, so that the pixel density is 2/3.

The density of the pixel to be converted is "3/2 times"
In this case, the selection circuit 40 selects the signal SEL2 and outputs it as multi-value data MD. The signal SEL1 is selected and output by the selection circuit 39 based on the selected clock signal CHS, either the average calculation result of two adjacent pixels or the multi-value data WR2. Selection circuit 39
Selects the multi-value data WR2 for 1.5 cycles of the clock signal CLK and outputs it as the signal SEL2, and selects the signal AVE2 for 0.5 cycles of the clock signal CLK and outputs it as the signal SEL2. Therefore, the pixel density conversion circuit 12 outputs the multi-value data MD for three pixels from the multi-value data ED for two pixels, so that the pixel density is 3/2.

Further, the density of the pixel to be converted is "2/1 times"
In this case, the selection circuit 40 selects the signal SEL2 and outputs it as multi-value data MD. The signal SEL2 is selected and output by the selection circuit 39 based on the selected clock signal CHS, either the average calculation result of two adjacent pixels or the multi-value data WR2. Selection circuit 39
Selects the multi-value data WR2 during the 0.5 cycle of the clock signal CLK and outputs it as the signal SEL2, and selects the signal AVE2 during the 0.5 cycle of the clock signal CLK and outputs it as the signal SEL2. Therefore, the pixel density conversion circuit 12 alternately outputs the multi-valued data of the original pixel and the multi-valued data obtained by calculating the average.
It becomes 1.

As described above, the present embodiment has the following advantages. (1) The image data processing device 1 includes a density enhancement circuit 11 and a pixel density conversion circuit 12. Shade emphasis circuit 1
1 focuses on one of the plurality of pixels, calculates an average of multi-valued data of a plurality of pixels adjacent to the focused-on pixel, and calculates multi-valued data of the calculation result and multi-valued of the focused-on pixel The calculation result calculated based on the difference from the data is output as new multivalued data in which the density of the focused pixel is emphasized. Further, the pixel density conversion circuit 12 calculates an average of multi-value data of two adjacent pixels with respect to multi-value data of each pixel input from the shading emphasis circuit 11, and calculates multi-value data of the calculation result, The multi-value data before the operation is selected and output, and the number of pixels for one line is converted. As a result, the pixel density is converted in advance with the multi-value data,
Since characters and the like rarely become thick and thin lines disappear, it is possible to obtain easy-to-view image data.

The present invention may be carried out as follows in addition to the above embodiment. (1) In the above embodiment, the multi-level resolution conversion unit 4 is configured by the gray level emphasizing circuit 11 and the pixel density conversion circuit 12, but may be implemented only by the pixel density conversion circuit 12. In this case, the density of the image is flattened, but the pixel density can be increased or decreased without deteriorating the gradation.

(2) In the above embodiment, the gray level emphasizing circuit 11 includes the multi-valued data of the pixel of interest G2 shown in FIG. 8 and the two adjacent data adjacent to the pixel of interest G2 in the main scanning direction.
The new multi-valued data of the pixel of interest G2 is calculated based on the multi-valued data of the two pixels G1 and G3 to emphasize the shading, but based on the multi-valued data of two or more pixels before and after each pixel. New multi-value data of the pixel of interest may be calculated to emphasize the shading of the pixel.

Further, the emphasis processing may be performed based on the density of pixels adjacent to the pixel of interest in the sub-scanning direction.
Further, the process of emphasizing the density of the pixel may be performed based on the density of the pixel adjacent in the main scanning direction and the pixel adjacent in the sub-scanning direction.

Further, in the above embodiment, the gray level emphasizing circuit 11 averages the difference between the multi-value data of the target pixel and the multi-value data of a plurality of peripheral pixels and adds the average to the multi-value data of the target pixel. However, the difference between the multi-value data of the target pixel and the multi-value data of one pixel located before or after the target pixel may be added to the multi-value data of the target pixel.

[0074]

As described above in detail, according to the present invention, it is possible to provide an image data processing apparatus capable of obtaining image data which is easy to view even if the pixel density is converted.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an image data processing apparatus according to an embodiment.

FIG. 2 is a circuit diagram of a gray level emphasizing circuit constituting a multi-level resolution conversion unit.

FIG. 3 is a circuit diagram of a pixel density conversion circuit constituting a multi-level resolution conversion unit.

FIG. 4 is an explanatory diagram showing the operation of the gray level emphasizing circuit.

FIG. 5 is an explanatory diagram showing the operation of the gray level emphasizing circuit.

FIG. 6 is an explanatory diagram showing an operation of the pixel density conversion circuit.

FIG. 7 is a waveform chart showing the operation of the pixel density conversion circuit.

FIG. 8 is an explanatory diagram showing pixels to be calculated.

FIG. 9 is an explanatory diagram illustrating a pixel shading emphasis process.

FIGS. 10A to 10E are explanatory diagrams illustrating a pixel density conversion process.

[Explanation of symbols]

 Reference Signs List 4 Multi-level resolution conversion unit 11 Shading emphasis circuit 12 Pixel density conversion circuit 21-23 Register 24 Adder 25 Divider 26 Subtractor 27 Multiplier 28 Adder 31-33 Register 34, 35 Adder 36 as an average arithmetic circuit 36, 37 Divider as Average Calculation Circuit 38-40 Selection Circuit

Claims (4)

[Claims] 1. An image data processing apparatus which takes in multi-value data obtained by quantization for each pixel from image data which is continuous in units of one line and constitutes one screen, converts the data into binary data in order, and outputs the binary data. And calculates an average value of multi-value data corresponding to two adjacent pixels, and selectively outputs multi-value data of the calculation result and multi-value data before calculation in response to a selection clock of a predetermined pattern. An image data processing apparatus including a pixel density conversion circuit (12) for converting the number of pixels per line into a desired number. 2. An image data processing apparatus which takes in multi-value data obtained by quantization for each pixel from image data constituting one screen which is continuous in units of one line, converts the data into binary data in order, and outputs the binary data. Then, a new multi-valued data in which the difference between the multi-valued data of a specific pixel in each line and the multi-valued data of another pixel adjacent to the pixel is added to emphasize the shading between pixels is output. Multi-level data of each pixel is input from the gray-scale emphasizing circuit (11), and the average of multi-level data corresponding to two adjacent pixels is calculated, and multi-level data of the calculation result is obtained. And an image density conversion circuit (12) for selectively outputting the multi-valued data and the multi-value data before the operation in response to a selection clock of a predetermined pattern and converting the number of pixels per line into a desired number. Data processing device. 3. The image data processing device according to claim 1, wherein the pixel density conversion circuit (12) is connected in series for sequentially storing multivalued data of a plurality of pixels that are continuously input. A plurality of registers (31-33), and among the multi-value data stored in the plurality of registers (31-33), multi-value data of two adjacent pixels are input, and the average of the multi-value data is calculated. An averaging circuit (34, 35, 36, 37) for calculating, multi-valued data stored in the register (32), and an operation result of the averaging circuit are input and converted according to the density of pixels to be converted. An image data processing device comprising a selection circuit (38, 39, 40) for selecting and outputting multi-value data and an operation result in response to a generated selection clock of a predetermined pattern. 4. The image data processing device according to claim 2, wherein the density enhancement circuit (11) includes a plurality of registers (21 to 23) each storing multi-value data of a plurality of adjacent pixels; Of the multi-valued data stored in the plurality of registers (21 to 23), for the image data of the particular pixel of interest,
A subtractor (26) for calculating a difference between the multi-value data of a pixel adjacent to the specific pixel and a multiplier (27) for multiplying a calculation result of the subtracter (26) by a set emphasis degree And an adder (28) for adding the operation result of the multiplier (27) and the multi-value data of the specific pixel and outputting the addition result as new multi-value data for the specific pixel.
And an image data processing device.