JPH1027498A - Self test circuit for rom and test method for rom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self test circuit for a ROM having configuration in which even a ROM having large capacity can be used. SOLUTION: A self test circuit 32 for a ROM comprises a data read-out circuit 10 and a counter 12. The data read-out circuit 10 comprises a word address specifying circuit 14 and a bit position specifying circuit 16. The counter 12 comprises a pulse generation circuit 18 and a data numbers counter 20. The pulse generation circuit 18 comprises a multiplexer 22 and an AND circuit 24. Also, this circuit is provided with a numerical value holding circuit 26, a comparator 28, and a test control circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-test circuit provided in an integrated circuit having a built-in ROM for testing the function of the ROM and a method of testing the function of the ROM.

[0002]

2. Description of the Related Art Conventionally, a self-test circuit for a ROM (Read Only Memory) has been disclosed in Japanese Patent Laid-Open Publication No.
4536 ". In this configuration example, the R stores information as a plurality of bits as one word.
It is provided in an integrated circuit (logic LSI) having a built-in OM, reads out information stored in the ROM in units of words, adds values represented by these words, and prepares the addition result in advance. The function of the ROM is diagnosed by comparing it with the expected value.

[0003]

However, with the recent miniaturization of the process technology, the data width (word) stored in the ROM mounted on the logic LSI has been increased. There is a problem that the circuit itself becomes large-scale.

For example, in the configuration example disclosed in the above document, the number of address bits is m (m is a positive integer),
All the information stored in the ROM whose data bit number (data width) is n (n is a positive integer) is read in units of words, and the value represented by each read word is added. When the bit values (values of binary data taking “1” and “0”) constituting each word are all “1”, the added value is expressed by the following equation (1).

[0005] {2 ^(n-1) +2 ^(n-2) +... +2 ⁰ } × 2 ^m (1) In {} of this equation (1), the common ratio is 2 and the initial ratio is 2. This is the sum of a geometric series with a value of 1. Therefore, equation (1) can be transformed into the following equation (2).

(2 ⁿ -1) × 2 ^m (2) In order to convert the value represented by the expression (2) into a binary number, the value of the base 2 is expressed by the following expression (3). Just take the logarithm.

Log ₂ {(2 ⁿ -1) × 2 ^m } (3) As described above, to calculate the addition value represented by the expression (1), the addition value is represented by the expression (3) It requires an adder (counter) having the number of bits. However, if the adder is 1 bit (bi
Since the value is expressed in units of t), values below the decimal point of the value represented by Expression (3) are rounded up. Then, the portion of (2 ⁿ -1) in equation (3) may be treated as 2 ⁿ . Therefore,
Equation (3) can be modified as in the following equation (4).

Log ₂ (2 ⁿ × 2 ^m ) = m + n (4) As described above, the addition of the value represented by each word stored in the ROM is represented by Expression (4). An adder with the number of bits of the value must be used. Generally, the adder has a configuration in which 1-bit full adders of the number of stages corresponding to the number of bits are connected in series. Therefore, in order to increase the number of bits of the adder, one bit forming the adder
Must be increased in the number of stages of the full adder.

As described above, in the conventional configuration, as the number of address bits and data bits of the ROM to be tested increases, the number of bits of the adder forming the self-test circuit must be increased. There is a problem that the self-test circuit becomes large-scale.

Therefore, conventionally, a ROM self-test circuit and a ROM having a configuration capable of coping with an increase in the storage capacity of a ROM have been disclosed.
The advent of an OM test method was desired.

[0011]

According to a ROM self-test circuit of the present invention, a ROM is provided in an integrated circuit having a built-in ROM that stores information with a plurality of bits as one word, and the function of the ROM is clocked. In a self-test circuit for testing while synchronizing with a signal,
A word address signal for reading a word from M is output, and 2 bits for each bit position of the read word are output.
A data read circuit for outputting a bit position designation signal for outputting value data, and "1" which is a bit value of the binary data outputted in response to the bit position designation signal
And a count counter that outputs the number of occurrences of any one of the specific bit values of “0” and “0”.

As described above, the data read circuit allows RO
A word is read from M and binary data for each bit position is output, and a specific counter value (for example, one of “1” and “0” of the output binary data) , “1”) can be output. Therefore, according to this configuration, it is possible to obtain the number of appearances of the specific bit value, that is, the total number of the specific bit values constituting the information stored in the ROM. Then, by comparing the obtained number of appearances of the specific bit value with an expected value prepared in advance,
It is possible to diagnose whether the function of the target ROM is normal or defective.

For example, all information stored in a ROM having an address bit number of m and a data bit number (data width) of n is read in word units, and each bit constituting the read word is read out. Add values. If the bit values that make up each word are all “1”,
The addition value is expressed by the following equation (5).

N × 2 ^m (5) In order to convert the value represented by the expression (5) into a binary number, the logarithm of the base 2 may be obtained as represented by the following expression (6). .

Log ₂ (n × 2 ^m ) = m + log ₂ n (6) Therefore, to calculate the addition value represented by the expression (5), the number of bits represented by the expression (6) is calculated by Adder (counter) with
is necessary. Compared with the conventional case, it can be seen from the comparison of the above equations (4) and (6) that in the configuration of the present invention, an adder having a small number of bits by (n-log ₂ n) bits is sufficient. Therefore, the configuration of the present invention has a feature that it is easier to cope with an increase in the capacity of the ROM than the conventional configuration.

According to a preferred configuration of the present invention, the data read circuit responds to a word address designating circuit for outputting the word address signal and a bit count signal outputted from the word address designating circuit. A bit position designating circuit that outputs the bit position designating signal, wherein the count counter outputs a pulse according to the specific bit value at the bit position designated by the bit position designating signal; A data number counter for counting the number of pulses.

As described above, the data read circuit is provided by the word
With the configuration using the address specifying circuit and the bit position specifying circuit, it is possible to read a word from the ROM and output binary data for each bit position. Further, by forming the counting counter with a pulse generation circuit and a data number counter, it is possible to output the number of appearances of a specific bit value of the output binary data.

According to a preferred configuration example of the present invention,
The pulse generation circuit generates the 2
A multiplexer for outputting value data, and an AND circuit for outputting the pulse by taking the logical product of the binary data and the clock signal.

Here, the multiplexer means a circuit for selecting and outputting one of several data inputs by a control input. As described above, by configuring the pulse generating circuit with the multiplexer and the AND circuit, each of the binary data forming the word input to the multiplexer is sequentially converted to the AND circuit by using the bit position designation signal as the control input. And a pulse can be generated according to whether or not the value of the binary data output to the AND circuit is a specific bit value.

According to a preferred configuration example of the present invention,
Further, a numerical value holding circuit for storing the number of the specific bit values (referred to as a data number) written in the ROM as an expected value, a count number of the data number counter and an expected value stored in the numerical value holding circuit. And a test control circuit for controlling the word / address specifying circuit, the bit position specifying circuit, the data number counter and the comparator while synchronizing with the clock signal. .

As described above, by comparing the count number of the data number counter with the number of data stored in the numerical value holding circuit by the comparator, the target R is obtained.
Diagnose whether the OM function is normal or defective. The operation of each component constituting the self test circuit of the ROM is controlled by the test control circuit.

According to the ROM testing method of the present invention, when testing the function of the ROM,
"1" which is the bit value of all the binary data stored in
And the function of the ROM is diagnosed by counting the number of specific bit values of either one of “0” and “0”, and comparing this number with an expected value prepared in advance.

As described above, by counting the number of specific bit values of all binary data stored in the ROM, the counted number is compared with an expected value prepared in advance. It is possible to diagnose whether the function of the target ROM is normal or defective.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the drawings are schematically shown to the extent that the configuration, arrangement, and operation of the present invention can be understood, and the numerical conditions and the like described below are merely examples. There is no limitation to the form.

In this embodiment, an integrated circuit having a built-in ROM that stores information with a plurality of bits as one word is provided.
A description will be given of the ROM self-test circuit 32 for testing while maintaining synchronization with the LK. FIG. 1 is a block diagram showing a configuration of a ROM self-test circuit according to an embodiment of the present invention. Self test circuit 32 of the ROM of this configuration example
Mainly includes a data read circuit 10 and a counter 1
2 and a value holding circuit 26, a comparator 28, a test control circuit 30
It has a configuration including:

First, the data read circuit 10 outputs a word address signal WA for reading a word from the ROM, and outputs a word address signal WA for each bit (digit) position of the read word.
A bit position designation signal BP for outputting (or generating) value data in the counter 12 is output to the counter 12.
Output to the circuit. The word address signal WA is
It is output from an address output terminal (also referred to as an address out terminal) AD_O of the self test circuit 32 of the ROM to the outside. In response to the word address signal WA, RO
Words stored at predetermined addresses of M are read, and each word is input to the counter 12 via a data input terminal (also referred to as a data-in terminal) DIN of the self-test circuit 32.

Here, the word address signal W shown in FIG.
A symbol m attached to the signal line indicating A indicates that the word to be tested is m when the number of address bits of the ROM to be tested is m.
This indicates that there are m signal lines for transmitting the address signal WA and m address output terminals AD_O. Further, [m-] described next to the address output terminal AD_O in FIG.
2: 0] indicates that the number of address bits m is 3, and that there are three address output terminals AD_O.

Next, the counter 12 counts a specific bit value of one of "1" and "0" of the binary data output in response to the bit position designation signal BP, for example, "1". Is a circuit that outputs the number of occurrences of "." The count counter 12 responds to the bit position designation signal BP from each word input from the data input terminal DIN.
The value data is selected, and the number of occurrences of the specific bit value of the binary data, that is, the total number of the specific bit values is counted and output.

Here, the symbol n attached to the signal line input to the counter 12 from the data input terminal DIN in FIG.
When the number of data bits of the ROM to be tested is n, the count counter 12 is input from the data input terminal DIN.
, There are n signal lines and data input terminals DIN. Also, the data input terminal DIN of FIG.
[N-1: 0] described next to indicates that the data bit number n is 2 and that there are two data input terminals DIN.

In the configuration of this embodiment, the above-mentioned data read circuit 10 includes a word / address designating circuit 14 and a bit position designating circuit 16.

The word address designating circuit 14 is a circuit for outputting a word address signal WA. Further, the bit position designating circuit 16 comprises a word address designating circuit 14.
Is a circuit that outputs the bit position designation signal BP in response to the bit count signal BC output by the. Thus, the word addressing circuit 14 and the bit position specifying circuit 16
Is specified by the timing of level switching of the bit count signal BC.
4 and 16 together read data read circuit 1 for outputting word address signal WA and bit position designating signal BP.
0 is mainly configured. Word of this embodiment
Address specifying circuit 14 and bit position specifying circuit 16
Is preferably configured with a normal counter.

In the configuration of this embodiment, the counter 12 includes a pulse generator 18 and a data counter 20. The pulse generation circuit 18 is a circuit that outputs a pulse according to a specific bit value at a bit position specified by the bit position specification signal BP, for example, “1” or “0”. The data number counter 20 is a circuit that counts the number of pulses output by the pulse generation circuit 18.

As described above, the pulse generating circuit 18 takes in the word specified by the word / address signal WA from the data input terminal DIN, specifies the bit position of this word by the bit position specifying signal BP, and One pulse is generated according to one of the bit values (specific bit values) of “1” or “0”, for example, “1”.

For example, when one word is composed of two bits, the bit position designation signal BP designates, for example, a lower bit and an upper bit sequentially twice.
If the bit values of each bit are all “1”, a specific bit value of “1” is output in the order of bit designation by the signal BP, and if the bit values of each bit are all “0”, the specific bit value is “ "1" is not output. For example, if the bit value of the lower digit is “1” and the bit value of the upper digit is “0”, when the lower bit position is designated by the signal BP, the specific bit at this bit position Since the value is "1", one pulse is generated when this bit position is specified. However, no pulse is generated when the upper bit position is specified. As described above, the specific bit value in which the bit value at the designated bit position is “1” is output, and a pulse is output in accordance with the specific bit value.

The number of pulses is counted by the data number counter 20 for all words, and the number of specific bit values (data number) stored in the ROM can be counted based on the total count number. This counting result is input to one input terminal of the comparator 28 described later via the output signal line 42. The output signal line 42 is composed of (m + log ₂ n) lines as shown in the above equation (6).

The above-described pulse generating circuit 18 includes a multiplexer 22 and an AND circuit 24.
The multiplexer 22 is a circuit that outputs binary data at a bit position designated by the bit position designation signal BP. The AND circuit 24 is a circuit that calculates the logical product of the binary data and the clock signal CLK and outputs the above-described pulse.

Further, the configuration of this embodiment includes the numerical value holding circuit 26, the comparator 28, and the test control circuit 30, as already described.

The numerical value holding circuit 26 is a circuit that previously stores the number of specific bit values (the number of data) written in the ROM as an expected value. The comparator 28
Is a circuit for comparing the count number of the data number counter 20 with the expected value stored in the numerical value holding circuit 26. The test control circuit 30 includes a word / address specifying circuit 14, a bit position specifying circuit 16, and a data number counter 20.
And a circuit that controls the comparator 28 while synchronizing with the clock signal CLK.

The output signal line 44 of the above-mentioned numerical value holding circuit 26
Is the number required to express the expected value, that is, (m + 1
og ₂ n) lines. Comparator 2
8 outputs a test result signal Test_Res for transmitting a test result to an external circuit. Further, the test control circuit 30 supplies the test enable signal Test_Enb
Is received from the external circuit to start the test operation, and outputs a test status signal Test_Sts to transmit the test completion to the external circuit.

FIG. 2 shows a ROM self-test circuit 32 having the above-described configuration, and an integrated circuit (LSI) having a built-in ROM 36.
FIG. 34 is a block diagram illustrating a configuration provided in a unit 34. This integrated circuit 34 mainly includes a ROM self-test circuit 32,
It comprises an OM 36, a logic circuit 38 and a second multiplexer 40.

The self test circuit 32 of the ROM outputs the word address signal WA from the address output terminal AD_O, as described above. This word address signal WA
Are timed by a second multiplexer 40 in accordance with an output signal from a logic circuit (a circuit forming a logical function using a logic element) 38 as a peripheral circuit, and input to an address terminal Addr of the ROM 36. Signal. In response to the input of the word address signal WA, the ROM 36 outputs the word stored at the designated address from the data output terminal DOut.

The word specified by the word address signal WA and output from the ROM 36 is input to the data input terminal DIN of the self test circuit 32 of the ROM. At the same time, this word is also output to the logic circuit 38 side and timed. Then, the logic circuit 38 outputs the clock signal CLK and the test enable signal Test_Enb to the ROM self-test circuit 32, and detects the test status signal Test_Sts and the test result signal Test_Res output from the ROM self-test circuit 32. Thus, the integrated circuit 34 is controlled.

Next, the operation of this embodiment will be described. FIG. 3 is a flowchart showing a test flow of the self test circuit of the ROM. FIG. 4 is a diagram showing a timing chart of the self test circuit of the ROM. In this embodiment, the ROM 36 is an 8-word 2-bit ROM (one word is composed of 2 bits and can store 8 words. That is, the number m of address bits is 3). , The number of data bits n
Is ROM. ) Will be described. In FIG. 3, steps of the flow are indicated by S. In FIG. 3, the decision box is indicated by a double-frame box.

(A) First, the test enable signal Tes
t_Enb is set to an active state (low level; represented as L) (S1 in FIG. 3 and Test_En in FIG. 4).
b). By setting Test_Enb = L in this manner, the supply of the clock signal CLK to the circuits (the word / address designating circuit 14, the AND circuit 24, and the test control circuit 30) constituting the ROM self-test circuit 32 is started. (CLK in FIG. 4).

(B) In accordance with the supply of the clock signal CLK, the count value of the word / address designating circuit 14 is counted up (S2 in FIG. 3). The count value of the word / address specifying circuit 14 is represented by Addr_Cnt.
Then, the value of the Addr_Cnt is output to the address terminal Addr of the ROM 36 as the word address signal WA (S3 in FIG. 3 and Addr in FIG. 4). From the ROM 36 to which the word address signal WA has been input, the word stored in the storage location to which the designated address is assigned is read (D0 and D1 in FIG. 4; the signals D0 and D1 in FIG. This is a signal indicating the state of the bits constituting each word input to the input terminal DIN. In this way, bits corresponding to the data width of one word are read at a time.)

The read word is stored in the multiplexer 22.
The multiplexer 22 receives the signal D from the data input terminal DIN according to the level of the bit position designation signal BP inputted to the bit position designation circuit 16.
Either 0 or D1 is selected and output. In this embodiment, first, the signal D0 is output when the bit position designation signal BP is at a low level, and then the signal D1 is output when the bit position designation signal BP is at a high level. (BP, D0 and D1 in FIG. 4).

The level switching instruction of the bit position designation signal BP from low level to high level is performed by the bit count signal BC output from the word / address designation circuit 14. Although not shown in FIG. 4, the bit count signal BC changes according to the number of pulses of the clock signal CLK input to the word / address designating circuit 14. The bit count signal BC according to the present embodiment has a bit position designation when eight clock signal CLK pulses are counted after the test enable signal Test_Enb is activated (S1 in FIG. 3 and Test_Enb in FIG. 4). This signal instructs to switch the level of the signal BP.

The binary data output from the multiplexer 22 is input to one input terminal of an AND circuit 24,
The logical product with the clock signal CLK input to the other input terminal is taken and output. 1 and FIG.
The output signal of the D circuit 24 is shown as Dat_pulse. The pulse number of the Dat_pulse signal indicates the number of appearances of the specific bit value.

That is, in this embodiment, "1" is taken as the specific bit value, and as shown in FIG. 4, when the bit position designation signal BP is at the low level, the logical product of the clock signal CLK and the signal D0 is taken. Dat_pull
Output as a se signal. The number of high-level states of the Dat_pulse signal corresponds to the number of “1” that is the specific bit value. When the bit position designation signal BP is at a high level, the logical product of the clock signal CLK and the signal D1 is output as a Dat_pulse signal. Dat_pulss output in this way
The number of pulses of the e signal indicates the total number of specific bit values stored in the ROM 36. This Dat_pull
The se signal is input to the data number counter 20, where the number of pulses is counted (S4 in FIG. 3 and Data_Cnt in FIG. 4).

(C) The count number of the word / address specifying circuit 14 is monitored by the test control circuit 30, and this count number is equal to the maximum word number (Word_MAX).
Called. ) The above-mentioned step (b) is repeatedly performed until 2 ^m is reached (S5 in FIG. 3).

(D) Also, the count number (referred to as Data_Cnt) of the bit position specifying circuit 16 is monitored by the test control circuit 30, and this count number is the maximum data bit number (referred to as Data_MAX) n.
The above steps (b) and (c) are repeatedly performed until (S6 and S7 in FIG. 3).

As described above, one of the specific bit values of the bit values “1” and “0” of all the binary data stored in the ROM 36 (in this embodiment,
The number of “1”) is counted.

(E) Next, the count value of the data number counter 20 (referred to as ROMDat_Cnt) is compared with the value stored in the numerical value holding circuit 26 (referred to as ROMDatNum) (S8 in FIG. 3). When these values are equal, ie, ROMDat_Cnt = ROMDat
When Num, the comparator 28 outputs the test result signal T
est_Res is set to a low level (referred to as a Pass state) (S9 in FIG. 3 and Test in FIG. 4).
_Res). On the other hand, ROMDat_Cnt ≠ ROMDa
At tNum, the comparator 28 sets the test result signal Test_Res to a high level (referred to as a fail state) (S10 in FIG. 3 and Te in FIG. 4).
st_Res).

As described above, by comparing the number of specific bit values with the expected value prepared in advance, the RO
Diagnose the function of M.

(F) Next, the test status signal Tes
t_Sts is set to a low level state, and an external circuit (FIG.
To the logic circuit 38) (S11 in FIG. 3 and Test_Sts in FIG. 4). Finally, it is confirmed that the test enable signal Test_Enb has transitioned to a high level (represented by H) (S12 in FIG. 3), and the test status signal Test_S
By switching ts to a high level, it is made inactive (S13 in FIG. 3).

[0056]

As is clear from the above description, according to the ROM self-test circuit of the present invention, the data read circuit reads a word from the ROM, outputs binary data for each bit position, and counts. The counter can output the number of occurrences of the specific bit value of the output binary data. Therefore, according to this configuration, it is possible to obtain the number of appearances of the specific bit value, that is, the total number of the specific bit values constituting the information stored in the ROM.
Then, by comparing the obtained number of appearances of the specific bit value with an expected value prepared in advance, the target ROM value is obtained.
Can be diagnosed whether the function is normal or defective. Also,
Compared to the conventional configuration, the configuration of the present invention
It has the feature that it is easy to adapt to the increase in capacity.

According to a preferred configuration example of the present invention, the data read circuit is constituted by the word address designating circuit and the bit position designating circuit. Data can be output. Further, by forming the counting counter with a pulse generation circuit and a data number counter, it is possible to output the number of appearances of a specific bit value of the output binary data.

According to a preferred embodiment of the present invention,
By configuring the pulse generation circuit with a multiplexer and an AND circuit, each of the binary data constituting the word input to the multiplexer is sequentially output to the AND circuit using the bit position designation signal as a control input. , AN
A pulse can be generated according to whether or not the value of the binary data output to the D circuit is a specific bit value.

Furthermore, according to the preferred embodiment of the present invention, the count of the data number counter is compared with the number of data stored in the numerical value holding circuit by the comparator to determine whether the target ROM is normal. Diagnose whether it is defective. The operation of each component constituting the self test circuit of the ROM is controlled by the test control circuit.

According to the ROM testing method of the present invention, the number of specific bit values of all binary data stored in the ROM is counted, and the counted number is prepared in advance. By comparing with the expected value, it is possible to diagnose whether the function of the target ROM is normal or defective.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a self test circuit of a ROM.

FIG. 2 is a diagram illustrating a configuration of an integrated circuit including a ROM.

FIG. 3 is a diagram showing a test flow of a ROM self-test circuit.

FIG. 4 is a diagram showing a timing chart of a ROM self-test circuit.

[Explanation of symbols]

 10: Data readout circuit 12: Count counter 14: Word address designation circuit 16: Bit position designation circuit 18: Pulse generation circuit 20: Data number counter 22: Multiplexer 24: AND circuit 26: Numeric value holding circuit 28: Comparator 30: Test Control circuit 32: ROM self-test circuit 34: LSI 36: ROM 38: Logic circuit 40: Second multiplexer 42, 44: Output signal line

Claims (5)

[Claims] 1. A self-test circuit provided in an integrated circuit having a built-in ROM for storing information in which a plurality of bits are stored as one word and testing the function of the ROM while synchronizing with a clock signal. A data read circuit for outputting a word address signal for reading a word from the ROM, and for outputting a bit position designation signal for outputting binary data for each bit position of the read word; And a counter for outputting the number of occurrences of a specific bit value of one of "1" and "0" which is a bit value of the binary data output in response to Self test circuit. 2. The ROM self-test circuit according to claim 1, wherein said data read circuit outputs a word address signal, and a bit count output by said word address specification circuit. A bit position designation circuit that outputs the bit position designation signal in response to a signal, wherein the count counter outputs a pulse according to the specific bit value at a bit position designated by the bit position designation signal. A self-test circuit for a ROM, comprising: a generation circuit; and a data number counter for counting the number of pulses. 3. The ROM self-test circuit according to claim 2, wherein the pulse generation circuit is configured to detect the position of the designated bit position in the ROM.
A self-test circuit for a ROM, comprising: a multiplexer that outputs value data; and an AND circuit that outputs a pulse by taking a logical product of the binary data and the clock signal. 4. A self-test circuit for a ROM according to claim 2, further comprising: a numerical value holding circuit for storing a number of said specific bit values (referred to as a data number) written in said ROM as an expected value. A comparator for comparing the count number of the data number counter with an expected value stored in the numerical value holding circuit; and the word / address specifying circuit, the bit position specifying circuit, the data number counter, and the comparator using the clock signal. A self-test circuit for a ROM, comprising: a test control circuit for controlling while synchronizing. 5. In testing the function of the ROM, the number of specific bit values of one of “1” and “0”, which are the bit values of all binary data stored in the ROM, is counted. A method for testing a ROM, wherein the function of the ROM is diagnosed by comparing the number with an expected value prepared in advance.