JPH10270860A - Multilayered printed wiring board - Google Patents

Multilayered printed wiring board

Info

Publication number
JPH10270860A
JPH10270860A JP7254497A JP7254497A JPH10270860A JP H10270860 A JPH10270860 A JP H10270860A JP 7254497 A JP7254497 A JP 7254497A JP 7254497 A JP7254497 A JP 7254497A JP H10270860 A JPH10270860 A JP H10270860A
Authority
JP
Japan
Prior art keywords
conductors
holes
printed wiring
wiring board
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7254497A
Other languages
Japanese (ja)
Inventor
Mitsuo Kuwabara
満夫 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP7254497A priority Critical patent/JPH10270860A/en
Publication of JPH10270860A publication Critical patent/JPH10270860A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate testing whether conductor-depositing order or the like is appropriate or not, by providing through holes for checking, connected to a common through hole via the conductors, corresponding to the number of conductors, and checking conduction between the conductors and checking circuits of the same number as that of the conductors. SOLUTION: Through holes 7a to 7e include a common through hole 7a and four checking through holes 7b to 7e of the same number as that of conductors 6a to 6d. The common through hole 7a is connected to the through holes for checking 7b to 7e respectively via connection portions 8a to 8d. The multilayered printed circuit board is completed by depositing the conductors 6a to 6d and a prepreg, and forming the through holes 7a to 7e and the like. Thereafter, to examine whether or not the structure and order of the conductors 6a to 6d are appropriate, one end of a tester is abutted against the through holes for checking 7b to 7e while the order end is abutted against the common through hole 7a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は多層プリント配線板
に関し、導体の順番等が適正か否か容易に検査できるよ
うにしたものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, which can easily inspect whether or not the order of conductors is appropriate.

【0002】[0002]

【従来の技術】電子部品の小形化や高密度化や高速度化
を図るため、プリント配線板を複数枚積層した多層プリ
ント配線板が設けられる。
2. Description of the Related Art In order to reduce the size, increase the density, and increase the speed of electronic components, a multilayer printed wiring board in which a plurality of printed wiring boards are stacked is provided.

【0003】多層プリント配線板のうちの例えばプリン
ト配線板を3枚積層した4層構造の多層プリント配線板
を図3に示す。図中1a〜1cは基板、2a〜2dは銅
箔や銅メッキによって形成された導体、3a〜3gはス
ルーホールである。導体2a〜2d上の太線はスルーホ
ールどうしを接続する接続部を表示しており、スルーホ
ール3b,3c間,スルーホール3c,3d間,スルー
ホール3e,3f間,スルーホール3f,3g間は接続
部4a,4b,4c,4dにより夫々接続されている。
FIG. 3 shows a multilayer printed wiring board having a four-layer structure in which, for example, three printed wiring boards are stacked among the multilayer printed wiring boards. In the figures, 1a to 1c are substrates, 2a to 2d are conductors formed by copper foil or copper plating, and 3a to 3g are through holes. The bold lines on the conductors 2a to 2d indicate the connection parts connecting the through holes, and between the through holes 3b and 3c, between the through holes 3c and 3d, between the through holes 3e and 3f, and between the through holes 3f and 3g. They are connected by connecting parts 4a, 4b, 4c, 4d, respectively.

【0004】斯かる多層プリント配線板は以下の手順で
製造される。まず、板厚が70μmの銅箔(高密度の回
路には35μmや18μmのものが用いられる)におけ
る不要部分をエッチング法により薬品で溶かし、電気回
路を有する導体2a〜2dを形成する。次に、プリプレ
グと称する半硬化状の絶縁材を導体2a〜2d間に挾ん
で加熱圧縮し、導体2a〜2d間に基板1a〜1cを形
成する。次に、導体2a〜2d間において電気的導通を
必要とする部分と、部品のリード線を挿入する部分とに
孔を形成し、無電解銅メッキ工程と電解銅メッキ工程と
を行ってスルーホール3a〜3gを形成する。
[0004] Such a multilayer printed wiring board is manufactured by the following procedure. First, unnecessary portions of a copper foil having a thickness of 70 μm (35 μm or 18 μm is used for a high-density circuit) are dissolved by an etching method with a chemical to form conductors 2 a to 2 d having an electric circuit. Next, a semi-cured insulating material called a prepreg is heated and compressed between the conductors 2a to 2d to form substrates 1a to 1c between the conductors 2a to 2d. Next, a hole is formed in a portion where electrical conduction is required between the conductors 2a to 2d and a portion where a lead wire of a component is inserted, and an electroless copper plating process and an electrolytic copper plating process are performed to form a through hole. 3a to 3g are formed.

【0005】[0005]

【発明が解決しようとする課題】ところが、導体とプリ
プレグとを重ねて加熱圧縮する積層工程において、以下
のようなミスを生じ易い。導体2a〜2dの数が不足す
る場合があり、この場合は回路が構成されず厚さが不足
するために発見しやすい。また導体2a〜2dの順番を
誤る場合があり、この場合は外観から発見できず、回路
は構成されるが回路の動作スピードが上がるとOVライ
ンと一定の距離に回路を構成している場合は回路特性を
安定させるために不安定動作をし、原因の追求が難し
い。更に、ある導体が複数積層されて他の導体が不足す
ることがあり、この場合は回路は構成されないが、厚さ
は変わらないので発見が難しい。
However, in the laminating step in which the conductor and the prepreg are stacked and heated and compressed, the following mistakes are likely to occur. In some cases, the number of conductors 2a to 2d is insufficient. In this case, a circuit is not formed and the thickness is insufficient, so that it is easy to find. In some cases, the order of the conductors 2a to 2d may be incorrect. In this case, the circuit cannot be found from the external appearance, and the circuit is configured. Performs unstable operation to stabilize circuit characteristics, making it difficult to find the cause. Further, there may be a case where a plurality of certain conductors are laminated and other conductors become insufficient. In this case, a circuit is not formed, but the thickness does not change, so that it is difficult to find out.

【0006】そこで本発明は、斯かる課題を解決した多
層プリント配線板を提供することを目的とする。
Therefore, an object of the present invention is to provide a multilayer printed wiring board which has solved the above-mentioned problems.

【0007】[0007]

【課題を解決するための手段】斯かる目的を達成するた
めの請求項1に係る多層プリント配線板の構成は、回路
を構成する薄板状の複数枚の導体と、導体どうしの間に
設けた絶縁部材とで構成した多層プリント配線板におい
て、前記導体等を貫通する共通スルーホールを設ける一
方、前記導体の一部である接続部を介して前記共通スル
ーホールに個別に接続される確認用スルーホールを、前
記導体等を貫通して前記導体の数だけ設けたことを特徴
とする。
According to a first aspect of the present invention, there is provided a multilayer printed wiring board comprising a plurality of thin plate-like conductors constituting a circuit, and a plurality of conductors provided between the conductors. In a multilayer printed wiring board composed of an insulating member, a common through-hole penetrating the conductor or the like is provided, and a confirmation through-hole individually connected to the common through-hole via a connection part that is a part of the conductor. Holes are provided by the number of the conductors penetrating the conductors and the like.

【0008】[0008]

【発明の実施の形態】以下、本発明を図面に示す実施例
に基づいて詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings.

【0009】(a)実施例1 本発明による多層プリント配線板の実施例1の構成を、
図1に示す。本実施例は、4枚の導体6a〜6dの間に
プリプレグを夫々介在させて構成されるが、導体6a〜
6dの全体は図示せずにそのうちの一部である接続部8
a〜8dとなる部分のみを示し、プリプレグについても
図示することは省略する。
(A) Embodiment 1 The configuration of the multilayer printed wiring board according to Embodiment 1 of the present invention is as follows.
As shown in FIG. In this embodiment, the prepreg is interposed between the four conductors 6a to 6d, respectively.
The entirety of 6d is not shown, and the connecting portion 8 which is a part thereof is not shown.
Only the portions a to 8d are shown, and illustration of the prepreg is omitted.

【0010】本発明における多層プリント配線板では、
回路を構成する部分である中央部から離れた外縁近傍の
余分なスペースに、図1の5つのスルーホール7a〜7
eが導体6a〜6d等を貫通して設けられている。スル
ーホール7a〜7eは、共通スルーホール7aと、導体
6a〜6dの枚数と同数の4つの確認用スルーホール7
b〜7eとの2種類に分けられる。共通スルーホール7
aは、個別の接続部(導体6a〜6dの一部が接続部8
a〜8dとなる)8a〜8dを介して確認用スルーホー
ル7b〜7eに個別に接続されている。
In the multilayer printed wiring board according to the present invention,
In the extra space near the outer edge away from the center, which is a part constituting the circuit, the five through holes 7a to 7 in FIG.
e is provided penetrating the conductors 6a to 6d and the like. The through holes 7a to 7e are common through holes 7a and four confirmation through holes 7 of the same number as the number of conductors 6a to 6d.
b to 7e. Common through hole 7
a is an individual connection part (a part of the conductors 6a to 6d
a to 8d) are individually connected to the confirmation through holes 7b to 7e via 8a to 8d.

【0011】次に、斯かる多層プリント配線板の作用を
説明する。導体6a〜6dとプリプレグとを積層して加
熱圧縮し、図1の構成となるようにスルーホール7a〜
7e等を形成して多層プリント配線板を完成させる。こ
のあと、導体6a〜6dの構成や順番が適正になってい
るか検査するには、テスターの一端を共通スルーホール
7aに当接させた状態で、他端を確認用スルーホール7
b〜7eに順番に当接させてみればよい。確認用スルー
ホール7b〜7eの全てについて導通が確認できれば合
格であり、確認できなければ不合格ということになる。
Next, the operation of the multilayer printed wiring board will be described. The conductors 6a to 6d and the prepreg are laminated and heated and compressed, so that the through holes 7a to
7e and the like are formed to complete a multilayer printed wiring board. Thereafter, in order to inspect whether the configurations and the order of the conductors 6a to 6d are proper, one end of the tester is brought into contact with the common through hole 7a and the other end is connected to the confirmation through hole 7a.
What is necessary is just to make contact with b-7e in order. If conduction can be confirmed for all of the confirmation through holes 7b to 7e, the result is a pass, and if not, the result is a failure.

【0012】(2)実施例2 次に、本発明による多層プリント配線板の実施例2を図
2に示す。この実施例は、共通スルーホール7cに対し
て4つの確認用スルーホール7a,7b,7d,7eを
設けたものである。共通スルーホール7cには、接続部
8a〜8dを介して確認用スルーホール7b,7a,7
e,7dが個別に接続されている。
(2) Second Embodiment Next, FIG. 2 shows a second embodiment of the multilayer printed wiring board according to the present invention. In this embodiment, four confirmation through holes 7a, 7b, 7d, 7e are provided for the common through hole 7c. Confirmation through holes 7b, 7a, 7 are connected to the common through hole 7c through the connection portions 8a to 8d.
e and 7d are individually connected.

【0013】その他の構成と作用は実施例1と同じなの
で説明を省略する。
The other configuration and operation are the same as those of the first embodiment, and the description is omitted.

【0014】[0014]

【発明の効果】以上の説明からわかるように、請求項1
に係る多層プリント配線板によれば、多層プリント配線
板を構成する夫々の導体を介して共通スルーホールに個
別に接続される確認用スルーホールを導体の数だけ設け
たので、導体の数と同数の確認回路の導通を確認するこ
とにより、導体を積層する順番等が適正か否かを容易に
検査することができる。
As can be seen from the above description, claim 1
According to the multilayer printed wiring board according to the above, the same number of conductors is provided as the number of conductors for confirmation which are individually connected to the common through holes via the respective conductors constituting the multilayer printed wiring board. By checking the continuity of the check circuit, it is possible to easily check whether or not the order of lamination of the conductors is appropriate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による多層プリント配線板の実施例1に
おける要部の構成を示す構成図。
FIG. 1 is a configuration diagram showing a configuration of a main part of a multilayer printed wiring board according to a first embodiment of the present invention.

【図2】本発明による多層プリント配線板の実施例2に
おける要部の構成を示す構成図。
FIG. 2 is a configuration diagram showing a configuration of a main part of a multilayer printed wiring board according to a second embodiment of the present invention.

【図3】従来の多層プリント配線板の断面図。FIG. 3 is a sectional view of a conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

6a〜6d…導体 7a〜7e…スルーホール 8a〜8d…接続部 6a to 6d: conductors 7a to 7e: through holes 8a to 8d: connection portion

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 回路を構成する薄板状の複数枚の導体
と、導体どうしの間に設けた絶縁部材とで構成した多層
プリント配線板において、 前記導体等を貫通する共通スルーホールを設ける一方、
前記導体の一部である接続部を介して前記共通スルーホ
ールに個別に接続される確認用スルーホールを、前記導
体等を貫通して前記導体の数だけ設けたことを特徴とす
る多層プリント配線板。
1. A multilayer printed wiring board comprising a plurality of thin plate-like conductors constituting a circuit and an insulating member provided between the conductors, wherein a common through hole penetrating the conductors and the like is provided.
A multi-layer printed wiring, wherein a number of confirmation through holes individually connected to the common through hole via a connection portion that is a part of the conductor are provided by the number of the conductors penetrating the conductor or the like. Board.
JP7254497A 1997-03-26 1997-03-26 Multilayered printed wiring board Pending JPH10270860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7254497A JPH10270860A (en) 1997-03-26 1997-03-26 Multilayered printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7254497A JPH10270860A (en) 1997-03-26 1997-03-26 Multilayered printed wiring board

Publications (1)

Publication Number Publication Date
JPH10270860A true JPH10270860A (en) 1998-10-09

Family

ID=13492417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7254497A Pending JPH10270860A (en) 1997-03-26 1997-03-26 Multilayered printed wiring board

Country Status (1)

Country Link
JP (1) JPH10270860A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009060505A1 (en) * 2007-11-05 2009-05-14 Fujitsu Limited Lamination order inspection method and wiring board manufacturing method
KR20190049826A (en) * 2017-07-28 2019-05-09 빅토리 자이언트 테크놀로지 (후이저우) 컴퍼니.,리미티드. Multifunctional circuit board detection module and detection method
CN112351582A (en) * 2019-08-08 2021-02-09 北大方正集团有限公司 Circuit board and manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009060505A1 (en) * 2007-11-05 2009-05-14 Fujitsu Limited Lamination order inspection method and wiring board manufacturing method
JP5104874B2 (en) * 2007-11-05 2012-12-19 富士通株式会社 Lamination sequence inspection method and wiring board manufacturing method
KR20190049826A (en) * 2017-07-28 2019-05-09 빅토리 자이언트 테크놀로지 (후이저우) 컴퍼니.,리미티드. Multifunctional circuit board detection module and detection method
CN112351582A (en) * 2019-08-08 2021-02-09 北大方正集团有限公司 Circuit board and manufacturing method

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