JPH10253710A - Semiconductor device and measuring method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time required for measurement by providing, for example, a buffer circuit with the output of a comparator, where the potential of both terminals of a resistor being connected in series with a power supply line is set to input, as input. SOLUTION: An internal circuit 120 to be measured is connected to a low- potential power supply wiring 106 via a high-potential power supply wire 105 and a resistor 101 for measuring current in series. A current (i) flows into the resistor 101 for measuring current and generates a potential difference. The potential difference is inputted to a comparator 114 via a high-potential side input line 107 and a low-potential side input line 108. The output of the comparator 114 is connected to the input of the buffer circuit 115 via an output line 110. The output of the buffer circuit 115 is connected to a test output pad 104 via an output line 111. When an abnormal current that indicates the failure of the internal circuit 120 is compared with an expectation value, potentials are compared and a current needs not be converted to a voltage, thus performing a measurement by operating a CMOS semiconductor integrated circuit at a required speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit configuration of a semiconductor device comprising a CMOS semiconductor integrated circuit, and more particularly, to a configuration of a test circuit formed on a CMOS semiconductor integrated circuit, a measuring method using the test circuit, and a measuring method. It is about.

[0002]

2. Description of the Related Art Generally, a functional test of a digital CMOS semiconductor integrated circuit is performed by a method of inputting a test signal from an input terminal and comparing a signal output from an output terminal with an expected value.

This method is suitable for testing the logical operation of a digital CMOS semiconductor integrated circuit.
It is known that it is insufficient to test the quality of each transistor and wiring constituting an OS semiconductor integrated circuit.
To compensate for this, a method of measuring a current flowing to a power supply of a CMOS semiconductor integrated circuit has been devised.

Referring to FIG. 3, the principle of a method for measuring a current flowing through a power supply of a CMOS semiconductor integrated circuit will be described. Generally, a CMOS semiconductor integrated circuit is supplied with a clock from the outside and operates in synchronization with the clock.

In a CMOS semiconductor integrated circuit, a current flows into a power supply only when the above-described clock is input. It is for this reason that it is generally known that the power consumption of CMOS is low.

If the circuit is completely synchronized with the above-mentioned clock, a current flows sufficiently in synchronization with the above-mentioned clock. Even in the case of a circuit that is not completely synchronized, the current increases near the change of the clock.

FIG. 3 shows a case where the circuit operates almost in synchronization with the rise of the clock. The current that has hardly flowed until then rapidly increases with the rise of the clock. Generally, the internal operation of a CMOS semiconductor integrated circuit has a time delay due to charging and discharging, so that the circuit is activated according to the signal propagation path of the circuit, and at the same time, current flows to the power supply.

As shown by the normal current in FIG. 3, the current shows a constant distribution in accordance with the above-mentioned time delay. When signal propagation by one clock is completed, the current becomes extremely small and does not change until the next clock is input.

[0009] It is well known that in the case of a failure in a CMOS semiconductor integrated circuit, the current in a CMOS remains increased even in the vicinity other than the vicinity of a clock change. FIG.
The abnormal current indicates that the transistor has failed and the current cannot be cut off completely.

As shown by the measurement points in FIG. 3, if the current is measured at a time when the current becomes sufficiently small, apart from the clock change, a method for comparing a signal coming out of the output terminal with an expected value is provided. Even without performing this, it is possible to find out the failure of the transistor during the semiconductor integration.

Even if a transistor fails and an abnormal current flows, the logic operation of CMOS may be correct.
However, the power consumption of the CMOS semiconductor integrated circuit itself increases due to the abnormal current. For low power devices such as small portable devices,
The slight increase in power consumption is significant and cannot be detected by comparing the signal coming out of the output terminal with the expected value.

In a method of inputting a test signal from an input terminal and comparing a signal output from an output terminal with an expected value, a CMO
It is necessary to input a test signal so that the influence of a failure in the S semiconductor integrated circuit propagates to the output terminal.
Depending on the logic of the semiconductor integrated circuit, it may be difficult to generate a test signal, or it may be necessary to input a very large test signal.

On the other hand, in the method of measuring the current flowing to the power supply of the CMOS semiconductor integrated circuit, since the logical output of each CMOS circuit only needs to change once, a fault can be detected efficiently with a small number of test signals.

As described above, the method of measuring the current flowing through the power supply of the CMOS semiconductor integrated circuit has many advantages, but the time required for measuring the current is longer than that of the voltage comparison method. However, the cost required for testing has increased significantly, and has not been put to practical use.

Referring to FIG. 4, the reason why the method of measuring the current flowing through the power supply of the CMOS semiconductor integrated circuit increases the measurement time will be described.

CMOS semiconductor integrated circuit 4 to be measured
20 is a high-potential power supply wiring 401 and a total low-potential power supply wiring 40
2 and a test circuit 400 provided outside.

The test circuit 400 has a power supply 404 having a high-potential power supply line 401 connected to the positive side and a low-potential power supply line 402 connected to the negative side via a current measurement resistor 403, and inputs both ends of the current measurement resistor 403. A / D converter (hereinafter, referred to as an A / D converter) 408, an A / D converter output line 409, and an expected value input line 411 as an input and a comparator 410 as a comparison result determination line 412 as an output.

When the CMOS semiconductor integrated circuit 420 starts operating, a current i flows from the power supply 404 through the high potential power supply line 401. This current passes through the CMOS semiconductor integrated circuit 420, passes through the current measuring resistor 403, and the power source 404.
Reach

When the current i flows through the current measuring resistor 403, a potential difference is generated between both ends of the current measuring resistor 403. This potential difference is supplied to the A / D converter 40 via a high potential side input line 406 connected to one end of the current measuring resistor 403 and a low potential side input line 407 connected to the other end.
Reach 8.

The A / D converter 408 generates a digital signal corresponding to the current i flowing through the current measuring resistor 403. The generated signal is input to the comparator 410 via the A / D converter output line 409.

An expected value representing the maximum current value allowed for a test is input to the comparator 410 in digital form via an expected value input line 411. The value output from the A / D converter and the expected value are compared in the comparator 410, and when the expected value is exceeded, a change is caused in the comparator result determination line 412.

In general, digital signal processing is sufficiently fast, but analog-to-digital conversion takes a long time. The current i flowing through the current measuring resistor 403 is generally a minute current, and a longer time is required to convert the minute current with high accuracy.

In general, the operation of a CMOS semiconductor integrated circuit is sufficiently fast, and it is extremely difficult to measure the current flowing through the power supply of the CMOS semiconductor integrated circuit described above while operating the CMOS semiconductor integrated circuit at the operating speed in actual use. , When measuring
It is necessary to stop the operation of the MOS semiconductor integrated circuit and wait for the completion of the A / D conversion. It is practically impossible to measure the current flowing through the power supply while operating the CMOS semiconductor integrated circuit at the operating speed in actual use.

In general, the measurement of the current flowing to the power supply of a CMOS semiconductor integrated circuit is 100 to 1000 times that of a method of inputting a test signal from an input terminal and comparing a signal output from an output terminal with an expected value. take time. For this reason, the cost required for the test is greatly increased, and it cannot be put to practical use except in extremely limited cases.

[0025]

SUMMARY OF THE INVENTION As described above, CMOS
A method for measuring a current flowing through a power supply of a semiconductor integrated circuit is as follows.
There is a problem that the time required for measurement is significantly longer than a method of inputting a test signal from an input terminal and comparing a signal coming out of an output terminal with an expected value.

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device and a measuring method thereof, which greatly reduce the time required for measurement.

[0027]

In order to achieve the object, a semiconductor device according to the present invention comprises an internal circuit, a test circuit, and an input / output circuit, and the test circuit is connected in series to a power supply line of the internal circuit. Resistor, a comparator having positive and negative potentials at both ends of the resistor, a buffer circuit having an output of the comparator as an input, a pad connected to the buffer output, and a power supply line of the comparator. A connected MOS transistor,
It is characterized by comprising a pad connected to the gate of the MOS transistor.

The comparator is connected to two P-type transistors having a source and a gate having the same potential and the source connected to a high-potential power supply and having the same conductivity, and a drain of the P-type transistor, respectively. The gates are connected to the positive and negative inputs of the comparator, respectively.
It is characterized by comprising N-type transistors and N-type transistors connected between the sources of the two N-type transistors and a low potential power supply.

In the comparator, two N-type transistors having slightly different conductivity coefficients are constituted by depression-type transistors.

The comparator is connected to two N-type transistors having a source and a gate having the same potential and the source connected to a low-potential power supply and having the same conductivity coefficient, and a drain of the N-type transistor, respectively. The gates are connected to the positive and negative inputs of the comparator, respectively.
It is characterized by comprising P-type transistors and P-type transistors connected between the sources of the two P-type NOS transistors and a high potential power supply.

In the semiconductor device according to the present invention, whether the current flowing through the power supply of the CMOS semiconductor integrated circuit is normal or not is converted into a voltage inside the semiconductor device and output to the outside of the semiconductor device. Does not require an A / D converter.

In the semiconductor device of the present invention, a method of measuring a current flowing to a power supply of a CMOS semiconductor integrated circuit is substantially the same as a method of inputting a test signal from an input terminal and comparing a signal output from an output terminal with an expected value. It is possible to do in the same time.

[0033]

FIG. 1B is a diagram for explaining the structure of a CMOS semiconductor integrated circuit according to the present invention.
0, an input / output 121, and a test circuit 122.

FIG. 1A shows the input / output circuit 12 in FIG. 1B.
FIG. 2 is a diagram showing a more detailed configuration of the test circuit 1 and a test circuit 122, and shows a circuit provided with a circuit for converting a current flowing through a power supply of the CMOS semiconductor integrated circuit into a voltage. First, the configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

In the input / output circuit 121 shown in FIG.
Usually, a plurality of input / output pads 112 are provided,
Is used to input and output a test signal and output the state of the internal circuit 120 to the outside during a test.

The high potential power supply pad 100 is connected to a high potential power supply wiring 105 inside the semiconductor device,
02 is connected to the low potential power supply wiring 106 inside the semiconductor device.

The internal circuit 120 to be measured is connected to the low-potential power supply wiring 106 via the high-potential power supply wiring 105 and the current measuring resistor 101 in series.

The high-potential end of the current measuring resistor 101 is connected to a high-potential input of a comparator 114 via a comparator high-potential-side input line 107, and the low-potential end of the current measuring resistor 101 is
The comparator 114 is connected to the low potential input of the comparator 114 via the low potential side input line 108.

The low-potential power supply of the comparator 114 is connected to the low-potential power supply wiring 106 inside the semiconductor, and the high-potential power supply of the comparator 114 is connected to the test control transistor 113 via the comparator high-potential power supply wiring 116. Further, the test control transistor 113 is connected to the high potential power supply wiring 105 inside the semiconductor. In this example, the test control transistor 113
Is a P-type transistor.

The gate input of the test control transistor 113 is connected to the test control pad 103 via the test control line 109.

The output of the comparator 114 is the comparator output line 11
0 is connected to the input of the buffer circuit 115. The output of the buffer circuit 115 is connected to the test output pad 104 via the test output line 111.

The current measuring resistor 101 is connected to the internal circuit 120.
Must be low enough not to hinder the operation of the circuit.

Further, an example of the comparator 114 will be described with reference to FIG. The comparator has a circuit configuration known as a differential amplifier. The sources of the P-type load transistors 201 and 202 are connected to the comparator high-potential power supply wiring 116.
The P-type load transistors 201 and 202 need to have exactly the same conductivity coefficient.

The gate inputs of the P-type load transistors 201 and 202 are connected to each other, and further connected to the drain of one of the load transistors 202.

The drain of the P-type load transistor 201 is connected to the comparator output line 110, and further connected to the drain of the N-type transistor 203. Similarly, the drain of the P-type load transistor 202 is connected to the drain of the N-type transistor 204.

The sources of N-type transistors 203 and 204 are connected to each other, and
Connect to the drain of Current limiting N-type transistor 20
5 is a low-potential power supply line 10 inside the semiconductor device.
Connect to 6.

The gate input of the N-type transistor 203 is connected to the comparator low potential side input line 108, and the gate input of the N-type transistor 204 is connected to the comparator high potential side input line 107. Further, the current limiting N-type transistor 20
A constant voltage is applied to the gate input 206 of No. 5 and the low potential power supply line 106.

The conductivity coefficients of the N-type transistors 203 and 204 are made slightly different. N-type transistor 203
Although there is a difference in the operation of the comparator 114 between the case where the conductivity coefficient is larger than the conductivity coefficient of the N-type transistor 204 and the case where the conductivity coefficient is opposite, it will be described in detail in the description of the measuring method according to the present invention.

Further, the N-type transistors 203 and 204 are constituted by depression type transistors. The current measuring resistor 101 is low enough not to hinder the circuit operation of the internal circuit 120. Therefore, the potential difference generated between both ends of the current measuring resistor 101 is small, and the comparator low potential side input line 10
8 or the potential difference between the comparator high potential side input line 107 and the low potential power supply line 106 is also small. That is, the potential difference between the gate and the source of the N-type transistors 203 and 204 is small, and the potential difference between the gate and the source of the enhancement-type transistor becomes less than the threshold value of the transistor, so that the operation cannot be performed. To prevent this, the N-type transistors 203 and 204 are constituted by depletion type transistors.

Next, a measuring method according to the present invention will be described with reference to FIGS. When operating the CMOS semiconductor integrated circuit for a normal purpose, the test control pad 103 is set to the same potential as the high potential power supply pad 101. As a result, the test control transistor 113 is turned off, and the comparator 114 does not operate. In this case, the signal generated at test output pad 104 has no meaning.

When measuring the current flowing through the CMOS semiconductor integrated circuit, the test control pad 103 is set to the same potential as the low potential power supply pad 102. As a result, the test control transistor 113 is turned on, and the comparator 114 operates correctly.

When the comparator 114 is operating properly, some test signal is input from the input terminal to the internal circuit 120.
And operate it. As described with reference to FIG. 3, the current i flows through the internal circuit 120 almost in synchronization with the clock.

The current i flows into the current measuring resistor 101 to generate a potential difference. This potential difference is input to the comparator 114 via the comparator high potential side input line 107 and the comparator low potential side input line 108.

The conductivity coefficients of the N-type transistors 203 and 204 constituting the comparator 114 are slightly different. As an example,
If the conductivity of the N-type transistor 203 is made larger than the conductivity of the N-type transistor 204, even if there is no potential difference between the comparator high potential side input line 107 and the comparator low potential side input line 108, the comparator output line Reference numeral 110 denotes the potential of the low potential power supply, and the test output pad 104 also reaches the potential of the low potential power supply through the buffer circuit 115.

At the measurement point shown in FIG.
, The current flowing through the current measuring resistor 101 is close to zero, and there is no potential difference across the current measuring resistor 101. Therefore, the test output pad 104 is at the potential of the low potential power supply as described above.

Next, considering the case where the current flows to the internal circuit 120 at the measurement point in FIG.
Is not close to zero at the abnormal timing. That is, a potential difference is generated between both ends of the current measuring resistor 101.

This potential difference is input to the comparator 114. N
The gate potential of the type transistor 204 is higher than the gate potential of the N-type transistor 203. Therefore, the N-type transistor 204 is turned on more than the N-type transistor 203. Therefore, the comparator output line 110 changes to the potential of the high potential power supply. The test output pad 104 also changes to the potential of the high potential power supply through the buffer circuit 115.

If the potential of the test output pad 104 is referred to as one signal when the potential of the test potential pad 104 is equal to the potential of the high potential power source, and referred to as the zero signal when the potential of the test output pad 104 is equal to the potential of the low potential power source, the present invention makes it possible to measure the current flowing inside the semiconductor. It can be seen that this is the same as the conventional method of comparing the signal coming out of the output terminal with the expected value.

In this embodiment, the expected value of the normal current is always 0 signal, and the expected value of the abnormal current indicating a failure inside the CMOS semiconductor integrated circuit is 1 signal. The comparison of expected values is a comparison of potentials, and there is no need to convert current to voltage.
Therefore, the measurement can be performed while operating the CMOS semiconductor integrated circuit at a required speed.

In general, the abnormal current is not a constant value,
It is expected to vary depending on the configuration of the S semiconductor integrated circuit and the manufacturing method. Therefore, the lower limit of the abnormal current depends on the purpose of the test. What is necessary is just to set the value of the conductivity coefficient of the N-type transistors 203 and 204 so that the output of the comparator 114 changes at the point where the lower limit of the abnormal current is exceeded.

The conductivity coefficient of a MOS transistor is proportional to the ratio between the channel width and the channel length. That is, the setting of the conductivity coefficient of the N-type transistors 203 and 204 is adjusted by designing the channel width or the channel length.

Further, the normal current at the measurement point in FIG.
It is not always zero depending on the configuration of the MOS semiconductor integrated circuit and the manufacturing method. However, the current measuring resistor 101 may be set so that it can be determined that the current is zero when the current is normal and that the current is clearly larger than zero when the current is abnormal.

In the above embodiment, the N-type transistor 203 is used.
Is larger than the conductivity coefficient of the N-type transistor 204, and the signal appearing on the test output pad 104 is 0 when the current is normal and 1 when the current is abnormal. Conversely, when the conductivity of the N-type transistor 204 is larger than the conductivity of the N-type transistor 203, the signal appearing on the test output pad 104 is 1 when the current is normal and 0 when the current is abnormal. It is easy to guess.

FIG. 2B shows another embodiment of the comparator 114. The sources of the N-type load transistors 211 and 212 are connected to the comparator low-potential power supply wiring 106.
The N-type load transistors 211 and 212 need to have exactly the same conductivity coefficient.

The gate inputs of the N-type load transistors 211 and 212 are connected to each other and further to the drain of one of the load transistors 212.

The drain of the N-type load transistor 211 is connected to the comparator output line 110, and further connected to the drain of the P-type transistor 213. Similarly, the drain of the N-type load transistor 212 is connected to the drain of the P-type transistor 214.

The sources of P-type transistors 213 and 214 are connected to each other.
Connect to the drain of Current limiting P-type transistor 21
5 is a high potential power supply line 11 inside the semiconductor device.
Connect to 6.

The gate input of the P-type transistor 213 is connected to the comparator low potential side input line 108, and the gate input of the P-type transistor 214 is connected to the comparator high potential side input line 107. Further, a constant voltage is applied between the gate input 216 of the current limiting transistor 215 and the high potential power supply line 116.

The conductivity coefficients of the P-type transistors 213 and 214 are made slightly different. P-type transistor 213
There is a difference in the operation of the comparator 114 between the case where the conductivity coefficient is larger than the conductivity coefficient of the P-type transistor 214 and the opposite case, but this is the same as in the above-described embodiment.

The measuring method in the embodiment shown in FIG. 2B is the same as that in the example shown in FIG. 2A. In both cases, the current flowing in the power supply of the CMOS semiconductor integrated circuit is measured. This method can be performed in substantially the same time as a method of inputting a test signal from an input terminal and comparing a signal coming out of an output terminal with an expected value.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a comparator according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating the principle of a method for measuring a current flowing through a power supply of a semiconductor integrated circuit.

FIG. 4 is a circuit diagram illustrating a measuring method of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 High potential power supply pad 101 Current measurement pad 102 Low potential power supply pad 103 Test control pad 104 Test output pad 105 High potential power supply line 106 Comparator low potential power supply line 107 Comparator high potential side input line 108 Comparator low potential side Input line 109 Test control line 110 Comparator output line 111 Test output line 113 Test control transistor 114 Comparator 115 Buffer circuit 116 Comparator high potential power supply line 120 Internal circuit 121 Input / output circuit 122 Test circuit 201, 202 P-type load transistor 203 First N-type transistor 204 Second N-type transistor 205 Current-limited N-type transistor 206 Gate of current-limited N-type transistor 211, 202 N-type load transistor 213 First P-type transistor 214 Second P-type transistor Transistor 215 current limiting P-type transistor 216 gate of current limiting P-type transistor 400 test circuit 401 high-potential power supply wiring 402 low-potential power supply wiring 403 current measuring resistor 404 power supply 406 high-potential-side input line 407 low-potential-side input line 408 A / D converter 409 A / D converter output line 410 Comparator 411 Expected value input line 412 Comparison result judgment line

Claims (5)

[Claims] 1. A semiconductor device comprising a CMOS semiconductor and comprising an internal circuit, a test circuit, and an input / output circuit, wherein the test circuit comprises: a resistor connected in series to a power supply line of the internal circuit; A comparator having the potentials at both ends of the comparator as positive and negative inputs, a buffer circuit having the output of the comparator as an input,
A semiconductor device comprising a pad connected to a buffer output of the buffer circuit, a MOS transistor connected in series to a power supply line of the comparator, and a pad connected to a gate of the MOS transistor. 2. In the comparator, two P-type transistors having a source and a gate having the same potential and a source connected to a high-potential power source and having the same conductivity coefficient, and a drain connected to the P-type transistor, respectively. A gate connected to the positive and negative inputs of the comparator, two N-type transistors having slightly different conductivity coefficients, and an N-type transistor connected between the sources of the two N-type transistors and a low potential power supply. The semiconductor device according to claim 1, wherein the semiconductor device is configured. 3. The semiconductor device according to claim 1, wherein in the comparator, two N-type transistors having slightly different conductivity coefficients are configured as a depression type. 4. In the comparator, two N-type transistors whose sources and gates have the same potential and whose sources are connected to a low-potential power source and have the same conductivity coefficient are connected to the drains of the N-type transistors, respectively. Two P-type transistors having gates respectively connected to the positive and negative inputs of the comparator and having slightly different conductivity coefficients; and a P-type transistor connected between the sources of the two P-type transistors and a high potential power supply. The semiconductor device according to claim 1, wherein: 5. A test circuit comprising an internal circuit, a test circuit, and an input / output circuit. The test circuit includes a resistor connected in series to a power supply line of the internal circuit, and a potential at both ends of the resistor. A comparator as an input, a buffer circuit as an input to the output of the comparator, a pad connected to a buffer output of the buffer circuit, a MOS transistor connected in series to a power line of the comparator, and a MOS transistor A method of measuring a semiconductor device comprising a pad connected to a gate of the semiconductor device, wherein a voltage generated in the resistor by a current flowing through the internal circuit in synchronization with a change point of a clock input from the input / output circuit is compared with the comparison result. The potential is converted to a potential of 1 or 0 by a device and output to a pad connected to the buffer output via the buffer circuit, and further separated from the clock change point. And measuring the potential of the output connected to the buffer output.