JPH10242052A - Polycrystalline silicon thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form uniform p-Si (polycrystalline silicon) by making a-Si (amorphous silicon) above a gate electrode polycrystalline. SOLUTION: Above a gate electrode 12 formed on a substrate 10, an a-Si film 20 is formed across the gate electrode 12 via a gate insulating film 14, and then subjected to annealing for polycrystallization (ELA or RTA). In a region adjacent to the gate electrode 12, gate dummy films 16 are previously formed by the same process as the gate electrode 12. The heat capacity of a-Si above the gate electrode 12 and that of a-Si above the gate dummy films 16 become nearly equal. Thereby uniform p-Si can be formed in a channel of a TFT(thin film transistor) and its peripheral region. When a gate aperture part or a protruding part is formed in the gate electrode 12, or it is made a bent strip pattern, uniform p-Si can be formed on a gate forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (TF) for a matrix type display device such as a liquid crystal display.
The present invention relates to various transistors such as T: Thin Film Transistor, and in particular, a TF using a polycrystalline silicon film obtained by polycrystallizing an amorphous silicon film as an active layer of the transistor.
Regarding the configuration of T.

[0002]

2. Description of the Related Art In recent years, high-definition and high-quality display has been demanded as a display device. For a liquid crystal display, an active matrix type liquid crystal display using a thin film transistor as a switching element for driving a liquid crystal (hereinafter, AMLCD: Active Matrix Liquid Cryst
al Display).

In an AMLCD using a TFT, an active layer of a thin film transistor, that is, a channel region is used as an active layer.
Amorphous silicon TFT using amorphous silicon (hereinafter a-Si) and polycrystalline silicon (hereinafter p-Si)
Is known.

[0004] Among them, the amorphous silicon TFT is a-
Since the Si film can be formed at a low temperature (for example, 300 degrees),
Since it is easy to form on an inexpensive glass substrate having a low melting point and it is easy to form a uniform a-Si film over a wide area, it is advantageous for increasing the size of the panel.
At present, it is often used for large LCDs.

One polycrystalline silicon TFT is a-Si TFT.
The mobility of the p-Si film is higher than that of the film, and when a TFT is used, the on-state current is large and the sheet resistance (on-resistance) is low. Therefore, high definition
It is considered useful as a switching element of a high-quality LCD. In addition, since the selection period (duty ratio) decreases as the size increases, its usefulness as a liquid crystal driving element for a large LCD has been pointed out. In addition, since a polycrystalline silicon TFT uses a p-Si film as an active layer, it can be used not only as a liquid crystal driving element of a pixel portion but also as a switching element constituting a logic circuit of a driving circuit. These liquid crystal driving elements and logic circuit elements can be formed on the same substrate in the same step. For this reason, polycrystalline silicon TFTs are currently used as so-called driver-incorporated LCDs in which a pixel portion and a drive portion are formed on the same substrate, for example, small and medium-sized LCDs that require high definition, high image quality, and small size. LCDs are widely used.

As described above, the polycrystalline silicon TFT has the L
By increasing the definition and image quality of the CD and by incorporating a driver, the space around the panel can be saved and the weight can be reduced. Therefore, in order to achieve a large size, like the amorphous silicon TFT, the polycrystalline silicon TFT has a melting point (about 600 degrees).
It is required to form a high yield on an inexpensive glass substrate with a low yield. However, at present, it is difficult to form a p-Si film having an appropriate grain size at a temperature lower than the melting point of the glass substrate (about 600 degrees). For this reason, a method of forming a p-Si film at a relatively low temperature by first forming an a-Si film on a substrate and then polycrystallizing the a-Si film using laser annealing is adopted. ing.

For example, in manufacturing a polycrystalline silicon TFT having a bottom gate structure for an LCD as shown in FIG. 8, an a-Si film formed on a glass substrate is irradiated with an excimer laser to form the a-Si film. A laser annealing method of heating and polycrystallizing this is known.

[0008] Bottom gate structure polycrystalline silicon TFT
First, a Cr film is formed on a glass substrate 10 and patterned into a predetermined shape to form a gate electrode 12 integral with a gate wiring as shown in FIG. 8A. Next, as shown in FIG. 8B, a gate insulating film 14 having a two-layer structure and an a-Si film are formed by plasma CVD (PE-C
VD: Plasma Enhanced Chemical Vapor Deposition)
To form continuously.

Then, the formed a-Si film 20 is irradiated with an excimer laser to anneal the a-Si film 20 (EL
A: Excimer Laser Annealing).
Si is polycrystallized to obtain a p-Si film 22. The ambient temperature at this time is usually about 300 degrees.

After the p-Si film 22 is formed by polycrystallization, a region on the p-Si film 22 where a channel region 44 is to be formed (a region facing the gate electrode 12) is formed.
An implantation stopper film 30 made of SiO ₂ is formed (FIG. 8).
(D)). Next, using the implantation stopper film 30 as a mask, a region corresponding to the source / drain region of the TFT is doped with an impurity (for example, phosphorus) from above in the figure. Note that the TFT shown in FIG.
ghtly Doped Drain) structure and the area 42L in the figure
S and 42LD are low concentration (N−) source / drain regions, respectively, and regions 40S and 40D are high concentration regions (N−).
+).

After the impurity doping, a short-time thermal annealing treatment by RTA (RTA: Rapid Thermal Annealin)
g) is performed to activate the doped impurities, thereby forming source / drain regions and channel regions in the p-Si film 22. After that, the interlayer insulating films 50 and 52 are formed, a source electrode (often also serving as a source wiring) 70 is connected to the source region 40S, and the drain region 40D is connected to a TFT in a pixel portion of the LCD. ITO (Indium Tin Oxid) which is a transparent conductive film as the pixel electrode 60
e) is connected to obtain one substrate of the LCD. FIG.
The planar arrangement of the TFT shown in (d) is, for example, an arrangement as shown in FIG. 9 (however, FIG.
0, before the pixel electrode 60 is formed).

[0012]

As described above, conventionally,
In a polycrystalline silicon TFT having a bottom gate structure,
The a-Si film 20 is polycrystallized by excimer laser annealing to obtain a p-Si film 22.

Since such polycrystallization of a-Si depends on the amount of heat supplied, that is, the amount of energy, a-Si
It is important to uniformly control the amount of heat applied to the i-film, that is, the in-plane energy of the excimer laser, for forming a uniform p-Si film 22.

However, the uniformity of energy in the irradiated surface of the a-Si film is poor, and it is difficult to form uniform p-Si.

The largest cause of such energy non-uniformity is that, in the TFT having the bottom gate structure, a part of the a-Si film 20 to be polycrystallized has heat conduction as shown in FIG. 8 or FIG. This is because it is formed so as to cover the upper part of the gate electrode 12 having high property, that is, to straddle the gate electrode 12. That is, the metal material (for example, Cr) constituting the gate electrode 12 has a higher thermal conductivity than the surrounding glass substrate 10 and the like. When the a-Si film 20 is irradiated with an excimer laser, the a-Si film In the region where the gate electrode 12 exists in the lower layer of 20, the heat generated by the excimer laser diffuses faster along the gate electrode 12 and the gate wiring than in other glass substrate regions.

For example, as shown in FIG. 10, in the region 22Sub without the gate electrode 12, although the a-Si film 20 becomes p-Si having an appropriate grain size, the presence of the gate electrode 12 is maintained under the same annealing condition. A- of the region 22G
The polycrystallization of the Si film 20 is insufficient, and it does not become p-Si having an appropriate grain size. This is apparent from FIG. 11 showing the relationship between the energy of ELA and the grain size of p-Si. That is, as shown in FIG. 11, when the ELA energy is set so that the grain size of the region (drain / source region) 22sub becomes an appropriate value (Es), the grain size of the region (channel region) 22G is set to the allowable lower limit ( (φ150 nm) marginally or less.

Since the region 22G above the gate electrode of the p-Si film 22 constitutes the channel region of the TFT,
Laser annealing conditions may be controlled so that the grain size of the polycrystal in region 22G is sufficiently large. However, also in this case, as shown in FIG. 11, if the ELA energy is set such that the grain size of the upper region 22G of the gate electrode becomes appropriate (E
g), the ELA energy is excessively supplied to the region 22Sub on the glass substrate, and the grain size is rather small, and the grain size falls below the allowable lower limit. Therefore, even if the annealing conditions were adjusted to the polycrystallization of the channel region, it was not possible to form a uniform and appropriate grain size p-Si film.

Further, when a TFT is formed by using the p-Si film 22 having an in-plane non-uniform grain size as described above, characteristics of each TFT (for example, ON current and sheet resistance depending on the grain size) are reduced. Variation increases. Therefore, when the TFT is used as a TFT in a pixel portion of an LCD, there is a problem that display unevenness occurs, which causes a bad influence on the display quality of the LCD.

The present invention has been made to solve such a problem, and has as its object to polycrystallize a-Si to form uniform p-Si. Also,
It is an object to provide a thin film transistor having excellent characteristics using such a p-Si film.

[0020]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned object, and has the following features.

First, the present invention relates to a polycrystalline silicon thin film transistor, comprising: a gate electrode patterned on a substrate; and a material film having a heat capacity similar to that of the gate electrode formed in a region adjacent to the gate electrode. Forming an amorphous silicon film above the gate electrode and the material film, polycrystallizing the amorphous silicon film by annealing, and using the obtained polycrystalline silicon film as an active layer of a thin film transistor. It was what was.

Further, according to the present invention, in the present invention, a predetermined common potential or a ground potential of a device including the polycrystalline silicon thin film transistor is applied to a material film formed in a region adjacent to the gate electrode.

Further, according to the present invention, an amorphous silicon film is formed above a gate electrode patterned on a substrate,
This amorphous silicon film is polycrystalline by annealing treatment, and the obtained polycrystalline silicon film is a polycrystalline silicon thin film transistor used as an active layer of the thin film transistor.
The gate electrode is provided with one or both of a protrusion and a gate opening in a region covered with the amorphous silicon film.

Further, an amorphous silicon film is formed above the patterned gate electrode on the substrate, and the amorphous silicon film is polycrystallized by an annealing treatment. A polycrystalline silicon thin film transistor used for a layer, wherein the gate electrode has a bent band pattern at least in a region covered with the amorphous silicon film.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings. In the following description, the same parts as those in the drawings already described are denoted by the same reference numerals, and description thereof will be omitted.

Embodiment 1 The polycrystalline silicon thin film TFT according to the first embodiment is a TFT used for driving a liquid crystal of an LCD or the like, and has a bottom gate structure in which a channel region and source / drain regions of the TFT are formed above a gate electrode. have. In the channel region formed above the gate electrode, in the first embodiment, a gate dummy film is formed in a region adjacent to the gate electrode as a material film having the same heat capacity as the gate electrode.

The gate dummy film is arranged close to the gate electrode, and has an a-S
In order to obtain uniform p-Si by equalizing the a-Si annealing conditions in the region above the gate electrode and the region above the gate dummy film during the polycrystallization annealing treatment of i.

FIG. 1 shows a plan view and a sectional state of a gate electrode (hereinafter, simply referred to as a gate electrode) 12 integrated with a gate wiring of a TFT and a gate dummy film 16 provided therearound. 1A shows a planar structure, and FIG. 1B shows a cross-sectional structure along line X1-X1 in FIG. 1A. 2 and 3 show a manufacturing process of the polycrystalline silicon TFT according to the first embodiment.

The gate electrode 12 is made of Cr having high thermal conductivity.
(W, Ta, TaMo may be used), and the gate dummy film 16 is formed at the same time as the gate electrode 12 is patterned on the glass substrate 10 as shown in FIG.

After the formation of the gate electrode 12 and the gate dummy film 16, a two-layered gate insulating film 14 (SiN, SiO ₂ ) and an a-Si film 20 are continuously formed on the entire surface of the substrate 10 including these surfaces by PE-CVD. Forming (FIG. 1 (b),
(See FIG. 2B).

Next, as shown in FIG.
The film 20 is subjected to a polycrystallization annealing treatment by ELA, and a
The p-Si film 24 is formed by polycrystallizing the -Si film 20. In the first embodiment, since the gate electrode 12 and the gate dummy film 16 have the same thermal conductivity (that is, the heat capacity), the film temperature is substantially the same in the a-Si region formed above the gate electrode 12 and the gate dummy film 16, and the polycrystallization is performed. Will proceed under similar conditions. For this reason, the channel region of the TFT and its neighboring region (for example, LD (Ligthy Dope
d) p- with homogeneous grain size in region)
As a result, a Si film 24 is obtained.

As described above, if the ELA using an excimer laser is used as the polycrystallization annealing treatment, annealing at a low temperature (about 300 degrees) is possible.
It is possible to easily form a p-Si film by crystal growth on an inexpensive glass substrate 10 having a low melting point.

Further, in the case of polycrystallization annealing by ELA, as described above, in the a-Si region where the electrode material film having a high thermal conductivity exists in the lower layer, the heat conduction of the electrode material film causes the heat conduction of the electrode material film to be larger than that of the glass substrate. The heat spreads quickly. Therefore, a in the formation region of the gate electrode and the gate dummy film,
-Annealing conditions are set according to the rate of polycrystallization of Si. In the first embodiment, the gate electrode and the gate dummy film are arranged in the vicinity of the gate electrode in a region corresponding to the channel region of the TFT and its periphery. Therefore, if the ELA conditions are set so as to meet the polycrystallization conditions in these regions, a uniform and appropriate p-Si layer is formed in and around the channel region which is important for maintaining the characteristics of the polycrystalline silicon TFT.
Can be formed. Note that E shown in FIG.
Considering the relationship between the LA energy and the grain size, the grain size of the source / drain regions 36S and 36D (see FIGS. 3 and 4) of the TFT does not increase.
Since these regions are heavily doped with impurities as described later, the sheet resistance becomes sufficiently low,
Even if the grain size is small, it hardly affects the characteristics of the TFT.

As the polycrystallization annealing, RTA using a halogen lamp or the like can be applied. When performing polycrystallization annealing by RTA, the region where the opaque material exists below, that is, in the first embodiment, the a-Si region in the region where the gate electrode and the gate dummy film are formed is formed.
Annealing conditions such as lamp power are set according to the polycrystallization speed of the region.

It should be noted that for lamp light of RTA, EL
Contrary to A, it can be said that the gate electrode material, which is an opaque material, has a higher absorptance of lamp light and a larger heat capacity than a glass substrate. Therefore, when the gate electrode and the gate dummy film are formed of an opaque conductive material (for example, Cr), the a-Si region above them, that is, the TFT channel region and the LD region around the TFT are preferentially increased. It will be crystallized. Therefore, in the case of performing polycrystallization using RTA, a necessary region, that is, a channel region of a TFT and a-Si around the TFT can be efficiently formed without setting a lamp power or a processing atmosphere temperature so high. And a polycrystalline silicon TFT having excellent characteristics can be obtained. Also, RTA makes it easy to form a polycrystalline silicon TFT on an inexpensive glass substrate having a low melting point.

After the poly-crystallization treatment of the a-Si film 20 is completed by the above-described poly-crystal anneal treatment, the gate electrode 12 is then formed by using a photolithography process using both back exposure and front exposure. A photoresist is formed only on top. Then, using this as a mask, the p-Si film 24 is formed as shown in FIG.
An injection stopper film 30 made of SiO ₂ is formed at a position facing the upper gate electrode 12. Injection stopper film 30
Is formed so that the edge thereof coincides with the edge of the gate electrode 12 by back surface exposure, and is not left on the gate dummy film 16 by surface exposure.

Then, using the formed implantation stopper film 30 as a mask, the p-Si film 24 is doped with an impurity (P or B), and the region except the region (channel region) 34 immediately below the implantation stopper film 30 has a low concentration. An (for example, N−) impurity-doped region is formed. Next, the TFT with LDD structure
In order to form the LD region, the channel region and the region to be the LD region are covered with a mask, and the p-Si film 24 is heavily doped with the same conductivity type impurity as in the case of low concentration doping. As a result, a heavily doped region (for example, N +) is formed outside the LD region covered with the mask.

After low and high concentration impurity doping,
As shown in FIG. 3, an activation annealing treatment by ELA is performed to activate the doped impurities (however, EL
A or RTA may be used). Then, by this annealing process, the LD source / drain regions 32LS and 32LD of the TFT and the source / drain regions 3
6S and 36D are formed respectively. Note that the annealing temperature in this activation annealing is p-
The film temperature of the Si film 24 is set to be about 900 degrees (however, the ambient temperature is about 300 degrees), and in the case of RTA, the ambient temperature (heating area temperature) is set to be about 600 degrees. You.

After the activation of the impurities, the p-Si film 24 is patterned into a desired shape, and as shown in FIG.
_{2. An} interlayer insulating film 50 is formed by laminating SiN, and a contact hole is opened at a position of the source region 36S of the interlayer insulating film 50. Then, a source electrode 70 made of Al or the like is formed thereon, and is connected to the source region 36S.

As shown in FIG. 4, when forming a liquid crystal driving TFT in a pixel portion of an LCD, a flattening film 52 is further formed by using an acrylic resin on the upper layer, and the flattening film 52 and the interlayer are formed. A contact hole is opened in the insulating film 50, and an ITO 60 serving as a pixel electrode is formed thereon.
The TO 60 and the drain region 36D are connected.

As described above, a TFT as shown in FIG. 4 is formed for each pixel in a matrix on the image display section of the LCD panel, and one substrate of the LCD is obtained. By bonding this substrate and the opposite substrate 80 on which the common electrode 86 and the color filter 82 are formed, and sealing liquid crystal therebetween, an LCD device is obtained. And each pixel part TFT
By controlling the potential of the pixel electrode 60 using
A desired voltage is applied to the liquid crystal to perform display. In FIG. 4, the source region 36S is connected to the source electrode 70, and the drain region 36D is connected to the ITO 60. However, the present invention is not limited to this, and the source region 36S may be connected to the ITO 60.

Here, as shown in FIG. 1, the gate dummy films 16 having a planar configuration arranged for each TFT are commonly connected in the row direction of the pixel TFTs of the LCD panel by, for example, dummy wirings 16L. The plurality of dummy wirings 16L provided in the row direction are commonly connected at an end of the LCD panel. Then, these dummy wirings 16L
Is connected to the common electrode 86 on the counter substrate 80 shown in FIG. 4 to apply a common electrode potential. Alternatively, it may be grounded to a ground potential. As described above, by controlling the gate dummy film 16 to a predetermined potential via the gate dummy wiring 16L, malfunction of the TFT can be prevented.

The TFT obtained by the above-described steps
Is not used for driving the liquid crystal, but the ITO 60 is unnecessary when the memory is used as various memory elements and logic circuit elements in an IC or as elements of a logic circuit of a driving circuit of a liquid crystal display device. In this case, at the same time as the formation of the source electrode 70, a drain electrode is formed in the same manner and connected to the drain region 36D. After the formation of the source / drain electrodes,
Connect to corresponding source / drain wiring. However, when the electrode and the wiring are formed integrally, a necessary wiring pattern is formed simultaneously with the formation of the source / drain electrodes.

The polycrystalline silicon TFT according to the present embodiment
For example, a CMOS (Complementary Metal Oxide Semiconducto
r), the n-channel (n-ch) TF
T and p-channel (p-ch) TFTs are formed. Specifically, when the n-type impurity is doped first, p-chTF
The region where T is to be formed is covered with a mask material, and after doping n-type impurities, the mask material covering the p-ch TFT is peeled off. Conversely, the n-ch TFT region is masked, and p-type impurities are doped in this state. After the end of the n-type and p-type impurity doping, the n-ch TFT and the p-ch TFT are simultaneously activated to form a TFT.

Embodiment 2 In the first embodiment, the gate dummy film 16 is formed independently around the gate electrode 12. On the other hand, in the second embodiment, the shape of the gate electrode 12 in the region covered with the a-Si film is changed so that the heat capacity in this region is increased and averaged.
When polycrystallizing Si, a uniform p-Si film is formed in the channel region and its peripheral region.

FIGS. 5, 6 and 7 show examples of the shape of the gate electrode for averaging the heat capacity in the gate formation region.

In the example shown in FIG. 5, the gate electrode 1 of the TFT is
In the pattern 8, a region where the gate electrode material does not exist, that is, a gate opening 18 a is formed. FIG.
5A is a plan view of the TFT structure of each pixel in the LCD pixel portion, and FIG. 5B is a plan view of X2 in FIG. 5A.
The cross-sectional structure along line -X2 is shown.

The gate opening 18a in FIG. 5 can be formed by patterning at the same time when the gate electrode 18 is formed on the substrate 10, and can be formed without adding a special step. In the example of FIG. 5, since the area of the gate electrode 18 is set to be substantially the same as the gate electrode 12 of FIG. 1, for example, the pattern width of the gate electrode 18 is reduced by the area of the gate opening 18a. doing. Therefore, the thermal conductivity of the gate electrode 18 is lower than that of the gate electrode 12.
Therefore, a-S is formed above the gate electrode 18 having the gate opening 18a as shown in FIG.
When an i-film is formed and polycrystallized by, for example, ELA, the heat capacity is increased by the reduced thermal conductivity, and the film temperature at the time of annealing the a-Si in the region above the gate electrode 18 can be increased. .

Further, in addition to the decrease in the thermal conductivity of the gate electrode 18, the gate opening 18 a having a low thermal conductivity is formed in a region where the upper portion is covered with the a-Si film, that is, in the gate formation region 19.
Is present, the heat capacity in the formation region 19 is increased as a whole. Therefore, also from this point, the annealing film temperature of the a-Si film above the formation region 19 can be increased, and the a-Si film in the portion to be the channel region of the TFT can be formed.
Can be promoted.

From the viewpoint of forming more uniform p-Si, a plurality of gate openings 18a are provided in the gate formation region 19 in order to reduce the deviation of the heat capacity in the gate formation region 19 in the plane direction. Preferably (three in the example of FIG. 5).

Next, in the example shown in FIG. 6, first, as in FIG. 5, the formation area of the gate electrode 21 is set to, for example, about the same as the gate electrode 12 in FIG. Further, a plurality of comb-shaped protrusions 21a are formed at predetermined intervals on the gate electrode 21, and the width of the gate electrode is reduced accordingly. With such a shape, the thermal conductivity of the gate electrode 21 decreases as in FIG. Since the gate electrode material does not exist in the protrusion gap 21b, the heat capacity in the protrusion gap 21b is high, and the heat capacity in the gate formation region 19 as a whole increases.
The polycrystallization of a-Si in this region proceeds efficiently and uniformly. FIG. 6A shows the positional relationship between the comb-shaped protruding portions 21a of the gate electrode 21 extending left and right in the drawing.
The arrangement is not limited to the left-right symmetric arrangement as shown in FIG. 6, but may be left-right asymmetric as shown in FIG. Further, a gate opening as shown in FIG. 5 may be further provided in the gate electrode 21 having a pattern as shown in FIG.

In the example of the shape of the gate electrode shown in FIG. 7, the gate electrode 23 is a narrow band-shaped electrode, and the band-shaped gate electrode 23 is bent a plurality of times. By providing a region where the gate electrode material is not present in the gate forming region with a narrow electrode width and a bent shape in this manner, the gate electrode 23 is formed in the same manner as in FIGS. 5 and 6 described above.
, And the heat capacity in the gate formation region 19 as a whole increases. Therefore, even with the gate electrode pattern as shown in FIG. 7, it is possible to rapidly and uniformly polycrystallize the a-Si film formed thereon by performing polycrystallization annealing. Becomes

In the second embodiment, the first embodiment is also used.
Similarly to the polycrystallization annealing, not only ELA,
It is possible to employ RTA.

[0054]

According to the present invention, as described above, in a polycrystalline silicon TFT having a bottom gate structure, a material film having the same heat capacity as that of a gate electrode formed on a substrate is disposed in close proximity to the gate electrode. Then, an a-Si film is formed above the material film, and this is polycrystallized. Therefore,
At the time of polycrystallization annealing, annealing conditions, ie, a
The film temperature of the -Si film can be made substantially the same in the region above the gate electrode and the region above the material film, and a uniform p-Si film can be formed over a wide range. Further, by applying a predetermined common potential or ground potential to this material film and controlling the potential, it is possible to prevent the TFT operation from being adversely affected.

If a gate opening where no electrode material is present is provided in the gate electrode formation region, a protruding portion is provided in the gate electrode, or the gate electrode is formed in a band-like bent shape, the gate formation can be performed by these structures. The heat capacity in the region can be made uniform. Therefore, uniform p-Si can be formed on the gate electrode formation region.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a polycrystalline silicon TFT having a bottom gate structure according to a first embodiment of the present invention.

FIG. 2 shows a polycrystalline silicon T according to the first embodiment of the present invention.
It is a figure showing the manufacturing process of FT.

FIG. 3 shows a polycrystalline silicon T according to the first embodiment of the present invention.
It is a figure showing the manufacturing process of FT.

FIG. 4 shows a polycrystalline silicon T according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration when an FT is used as a TFT in an LCD pixel portion.

FIG. 5 shows a polycrystalline silicon T according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an FT.

FIG. 6 shows a polycrystalline silicon T according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an FT.

FIG. 7 shows a polycrystalline silicon T according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an FT.

FIG. 8 is a diagram showing a conventional manufacturing process of a polycrystalline silicon TFT having a bottom gate structure.

FIG. 9 is a diagram illustrating a planar configuration of a liquid crystal driving TFT having a bottom gate structure.

FIG. 10 shows a graph of p- obtained by a conventional polycrystallization method.
FIG. 3 is a diagram showing a polycrystallized state of a Si film.

FIG. 11 is a diagram illustrating a relationship between ELA energy and grain size of p-Si.

[Explanation of symbols]

10 Substrate, 12, 18, 21, 23 Gate electrode, 1
4 gate insulating film, 18b opening, 19 gate formation region, 20a-Si film, 21a protrusion, 21b protrusion gap, 24p-Si film, 30 injection stopper film,
34 channel region, 36S source region, 36D drain region, 60 ITO.

Claims (4)

[Claims] 1. A gate electrode patterned on a substrate, and a material film formed in a region adjacent to the gate electrode and having a heat capacity similar to that of the gate electrode, wherein the gate electrode and the material film A polycrystalline silicon thin film formed by forming an amorphous silicon film above the polycrystalline silicon film, polycrystallizing the amorphous silicon film by annealing, and using the obtained polycrystalline silicon film as an active layer of the thin film transistor. 2. A polycrystalline silicon thin film transistor according to claim 1, wherein a predetermined common potential or a ground potential of a device including said polycrystalline silicon thin film transistor is applied to a material film formed in a region adjacent to said gate electrode. A polycrystalline silicon thin film transistor characterized by the above-mentioned. 3. In a polycrystalline silicon thin film transistor, an amorphous silicon film is formed above a gate electrode patterned on a substrate, and the amorphous silicon film is polycrystallized by an annealing treatment. A polycrystalline silicon thin film transistor using a silicon film as an active layer of the thin film transistor, wherein the gate electrode is provided with one or both of a protrusion and a gate opening in a region covered with the amorphous silicon film. A polycrystalline silicon thin film transistor characterized by the above-mentioned. 4. In a polycrystalline silicon thin film transistor, an amorphous silicon film is formed above a gate electrode patterned on a substrate, and the amorphous silicon film is polycrystallized by an annealing treatment. A polycrystalline silicon thin film transistor using a silicon film as an active layer of the thin film transistor, wherein the gate electrode has a bent band pattern in a region covered with the amorphous silicon film.